[U-Boot-Users] [PATCH] 83xx: Add Vitesse VSC7385 firmware uploading

[U-Boot-Users] [PATCH] 83xx: Add Vitesse VSC7385 firmware uploading

[Timur Tabi]

The Vitesse VSC7385 is a 5-port switch found on the Freescale MPC8349E-mITX
and other boards.  A small firwmare must be uploaded to its on-board memory
before it can be enabled.  This patch adds the code which uploads firmware
(but not the firmware itself) and updates the MPC8349E-mITX, MPC8313E-RDB,
and MPC837XE-RDB boards to use that code.

Previously, this feature was provided by a U-Boot application that was
made available only on Freescale BSPs.  The VSC7385 firmware must still
be obtained separately, but at least there is no longer a need for a separate
application.

Changed CONFIG_VSC7385 to CONFIG_VSC7385_ENET.  Also cleaned up the board
header files to make selecting the VSC7385 easier to control.

Signed-off-by: Timur Tabi <timur@freescale.com>
---

This patch is for U-Boot 1.3.3

 board/freescale/mpc8313erdb/mpc8313erdb.c |   21 ++++++
 board/freescale/mpc8349itx/mpc8349itx.c   |   15 ++++-
 board/freescale/mpc837xerdb/mpc837xerdb.c |   27 ++++++--
 drivers/net/Makefile                      |    1 +
 drivers/net/vsc7385.c                     |  100 +++++++++++++++++++++++++++++
 include/configs/MPC8313ERDB.h             |   88 +++++++++++++++++--------
 include/configs/MPC8349ITX.h              |   33 +++++++---
 include/configs/MPC837XERDB.h             |   83 ++++++++++++++++--------
 include/vsc7385.h                         |   13 ++++
 9 files changed, 310 insertions(+), 71 deletions(-)
 create mode 100644 drivers/net/vsc7385.c
 create mode 100644 include/vsc7385.h

diff --git a/board/freescale/mpc8313erdb/mpc8313erdb.c b/board/freescale/mpc8313erdb/mpc8313erdb.c
index 42019fb..7cbdb7b 100644
--- a/board/freescale/mpc8313erdb/mpc8313erdb.c
+++ b/board/freescale/mpc8313erdb/mpc8313erdb.c
@@ -28,6 +28,7 @@
 #endif
 #include <pci.h>
 #include <mpc83xx.h>
+#include <vsc7385.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -98,6 +99,26 @@ void pci_init_board(void)
 	mpc83xx_pci_init(1, reg, warmboot);
 }
 
+/*
+ * Miscellaneous late-boot configurations
+ *
+ * If a VSC7385 microcode image is present, then upload it.
+*/
+int misc_init_r(void)
+{
+	int rc = 0;
+
+#ifdef CONFIG_VSC7385_IMAGE
+	if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE,
+		CONFIG_VSC7385_IMAGE_SIZE)) {
+		puts("Failure uploading VSC7385 microcode.\n");
+		rc = 1;
+	}
+#endif
+
+	return rc;
+}
+
 #if defined(CONFIG_OF_BOARD_SETUP)
 void ft_board_setup(void *blob, bd_t *bd)
 {
diff --git a/board/freescale/mpc8349itx/mpc8349itx.c b/board/freescale/mpc8349itx/mpc8349itx.c
index 8c19ad6..5571248 100644
--- a/board/freescale/mpc8349itx/mpc8349itx.c
+++ b/board/freescale/mpc8349itx/mpc8349itx.c
@@ -26,6 +26,7 @@
 #include <i2c.h>
 #include <spd.h>
 #include <miiphy.h>
+#include <vsc7385.h>
 
 #ifdef CONFIG_PCI
 #include <asm/mpc8349_pci.h>
@@ -183,7 +184,7 @@ int checkboard(void)
  */
 int misc_init_f(void)
 {
-#ifdef CONFIG_VSC7385
+#ifdef CONFIG_VSC7385_ENET
 	volatile u32 *vsc7385_cpuctrl;
 
 	/* 0x1c0c0 is the VSC7385 CPU Control (CPUCTRL) Register.  The power up
@@ -245,6 +246,8 @@ int misc_init_f(void)
 }
 
 /*
+ * Miscellaneous late-boot configurations
+ *
  * Make sure the EEPROM has the HRCW correctly programmed.
  * Make sure the RTC is correctly programmed.
  *
@@ -256,6 +259,8 @@ int misc_init_f(void)
  *
  * This function makes sure that the I2C EEPROM is programmed
  * correctly.
+ *
+ * If a VSC7385 microcode image is present, then upload it.
  */
 int misc_init_r(void)
 {
@@ -381,6 +386,14 @@ int misc_init_r(void)
 	i2c_set_bus_num(orig_bus);
 #endif
 
+#ifdef CONFIG_VSC7385_IMAGE
+	if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE,
+		CONFIG_VSC7385_IMAGE_SIZE)) {
+		puts("Failure uploading VSC7385 microcode.\n");
+		rc = 1;
+	}
+#endif
+
 	return rc;
 }
 
diff --git a/board/freescale/mpc837xerdb/mpc837xerdb.c b/board/freescale/mpc837xerdb/mpc837xerdb.c
index 2d42595..1ab7be4 100644
--- a/board/freescale/mpc837xerdb/mpc837xerdb.c
+++ b/board/freescale/mpc837xerdb/mpc837xerdb.c
@@ -16,6 +16,8 @@
 #include <i2c.h>
 #include <spd.h>
 #include <asm/io.h>
+#include <vsc7385.h>
+
 #if defined(CONFIG_SPD_EEPROM)
 #include <spd_sdram.h>
 #endif
@@ -59,11 +61,6 @@ testdram(void)
 }
 #endif
 
-int board_early_init_f(void)
-{
-	return 0;
-}
-
 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
 void ddr_enable_ecc(unsigned int dram_size);
 #endif
@@ -138,6 +135,26 @@ int checkboard(void)
 	return 0;
 }
 
+/*
+ * Miscellaneous late-boot configurations
+ *
+ * If a VSC7385 microcode image is present, then upload it.
+*/
+int misc_init_r(void)
+{
+	int rc = 0;
+
+#ifdef CONFIG_VSC7385_IMAGE
+	if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE,
+		CONFIG_VSC7385_IMAGE_SIZE)) {
+		puts("Failure uploading VSC7385 microcode.\n");
+		rc = 1;
+	}
+#endif
+
+	return rc;
+}
+
 #if defined(CONFIG_OF_BOARD_SETUP)
 
 void ft_board_setup(void *blob, bd_t *bd)
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index b9723fa..5ae7cb7 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -57,6 +57,7 @@ COBJS-y += tigon3.o
 COBJS-y += tsec.o
 COBJS-y += tsi108_eth.o
 COBJS-y += uli526x.o
+COBJS-y += vsc7385.o
 
 COBJS	:= $(COBJS-y)
 SRCS 	:= $(COBJS:.o=.c)
diff --git a/drivers/net/vsc7385.c b/drivers/net/vsc7385.c
new file mode 100644
index 0000000..39b077f
--- /dev/null
+++ b/drivers/net/vsc7385.c
@@ -0,0 +1,100 @@
+/*
+ * Vitesse 7385 Switch Firmware Upload
+ *
+ * Author: Timur Tabi <timur@freescale.com>
+ *
+ * Copyright 2008 Freescale Semiconductor, Inc.  This file is licensed
+ * under the terms of the GNU General Public License version 2.  This
+ * program is licensed "as is" without any warranty of any kind, whether
+ * express or implied.
+ *
+ * This module uploads proprietary firmware for the Vitesse VSC7385 5-port
+ * switch.
+ */
+
+#include <config.h>
+#include <common.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+
+#ifdef CONFIG_VSC7385_ENET
+
+/*
+ * Upload a Vitesse VSC7385 firmware image to the hardware
+ *
+ * This function takes a pointer to a VSC7385 firmware image and a size, and
+ * uploads that firmware to the VSC7385.
+ *
+ * This firmware is typically located at a board-specific flash address,
+ * and the size is typically 8KB.
+ *
+ * The firmware is Vitesse proprietary.
+ *
+ * Further details on the register information can be obtained from Vitesse.
+ */
+int vsc7385_upload_firmware(void *firmware, unsigned int size)
+{
+	u8 *fw = firmware;
+
+	u32 *gloreset = (u32 *) (CFG_VSC7385_BASE + 0x1c050);
+	u32 *icpu_ctrl = (u32 *) (CFG_VSC7385_BASE + 0x1c040);
+	u32 *icpu_addr = (u32 *) (CFG_VSC7385_BASE + 0x1c044);
+	u32 *icpu_data = (u32 *) (CFG_VSC7385_BASE + 0x1c048);
+	u32 *chipid = (u32 *) (CFG_VSC7385_BASE + 0x1c060);
+	u32 *icpu_rom_map = (u32 *) (CFG_VSC7385_BASE + 0x1c070);
+
+	unsigned int i;
+	int ret = 0;
+
+	out_be32(gloreset, 3);
+	udelay(200);
+
+	out_be32(icpu_ctrl, 142);
+	udelay(20);
+
+	out_be32(icpu_rom_map, 1);
+	udelay(20);
+
+        /* Write the firmware to I-RAM */
+	out_be32(icpu_addr, 0);
+	udelay(20);
+
+	for (i = 0; i < size; i++) {
+		out_be32(icpu_data, fw[i]);
+		udelay(20);
+		if (ctrlc())
+			return -EINTR;
+	}
+
+	/* Read back and compare */
+	out_be32(icpu_addr, 0);
+	udelay(20);
+
+	for (i = 0; i < size; i++) {
+		u8 value;
+
+		value = (u8) in_be32(icpu_data);
+		udelay(20);
+		if (value != fw[i]) {
+			debug("VSC7385: Upload mismatch: address 0x%x, "
+                              "read value 0x%x, image value 0x%x\n",
+                              i, value, fw[i]);
+
+			return -EIO;
+		}
+		if (ctrlc())
+			break;
+	}
+
+	out_be32(icpu_ctrl, 11);
+	udelay(20);
+
+#ifdef DEBUG
+	printf("VSC7385: Chip ID is %08x\n", in_be32(chipid));
+	udelay(20);
+#endif
+
+	return 0;
+}
+
+#endif
diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h
index f12a3e6..9576fa5 100644
--- a/include/configs/MPC8313ERDB.h
+++ b/include/configs/MPC8313ERDB.h
@@ -38,6 +38,14 @@
 #define CONFIG_PCI
 #define CONFIG_83XX_GENERIC_PCI
 
+#define CONFIG_MISC_INIT_R
+
+/*
+ * On-board devices
+ */
+#define CONFIG_VSC7385_ENET
+
+
 #ifdef CFG_66MHZ
 #define CONFIG_83XX_CLKIN	66666667	/* in Hz */
 #elif defined(CFG_33MHZ)
@@ -65,6 +73,22 @@
 #define CFG_ACR_RPTCNT		3	/* Arbiter repeat count (0-7) */
 
 /*
+ * Device configurations
+ */
+
+/* Vitesse 7385 */
+
+#ifdef CONFIG_VSC7385_ENET
+
+#define CONFIG_TSEC2
+
+/* The flash address and size of the VSC7385 firmware image */
+#define CONFIG_VSC7385_IMAGE		0xFE7FE000
+#define CONFIG_VSC7385_IMAGE_SIZE	8192
+
+#endif
+
+/*
  * DDR Setup
  */
 #define CFG_DDR_BASE		0x00000000	/* DDR is system memory*/
@@ -214,19 +238,24 @@
 #define CFG_LBLAWBAR1_PRELIM	CFG_NAND_BASE
 #define CFG_LBLAWAR1_PRELIM	0x8000000E	/* 32KB  */
 
+/* local bus read write buffer mapping */
+#define CFG_BR3_PRELIM		0xFA000801	/* map at 0xFA000000 */
+#define CFG_OR3_PRELIM		0xFFFF8FF7	/* 32kB */
+#define CFG_LBLAWBAR3_PRELIM	0xFA000000
+#define CFG_LBLAWAR3_PRELIM	0x8000000E	/* 32KB  */
+
+/* Vitesse 7385 */
+
 #define CFG_VSC7385_BASE	0xF0000000
 
-#define CONFIG_VSC7385_ENET			/* VSC7385 ethernet support */
+#ifdef CONFIG_VSC7385_ENET
+
 #define CFG_BR2_PRELIM		0xf0000801	/* VSC7385 Base address */
 #define CFG_OR2_PRELIM		0xfffe09ff	/* VSC7385, 128K bytes*/
 #define CFG_LBLAWBAR2_PRELIM	CFG_VSC7385_BASE/* Access window base at VSC7385 base */
 #define CFG_LBLAWAR2_PRELIM	0x80000010	/* Access window size 128K */
 
-/* local bus read write buffer mapping */
-#define CFG_BR3_PRELIM		0xFA000801	/* map at 0xFA000000 */
-#define CFG_OR3_PRELIM		0xFFFF8FF7	/* 32kB */
-#define CFG_LBLAWBAR3_PRELIM	0xFA000000
-#define CFG_LBLAWAR3_PRELIM	0x8000000E	/* 32KB  */
+#endif
 
 /* pass open firmware flat tree */
 #define CONFIG_OF_LIBFDT	1
@@ -263,13 +292,6 @@
 #define CFG_I2C_OFFSET		0x3000
 #define CFG_I2C2_OFFSET		0x3100
 
-/* TSEC */
-#define CFG_TSEC1_OFFSET	0x24000
-#define CFG_TSEC1		(CFG_IMMR+CFG_TSEC1_OFFSET)
-#define CFG_TSEC2_OFFSET	0x25000
-#define CFG_TSEC2		(CFG_IMMR+CFG_TSEC2_OFFSET)
-#define CONFIG_NET_MULTI
-
 /*
  * General PCI
  * Addresses are mapped 1-1.
@@ -288,26 +310,31 @@
 #define CFG_PCI_SUBSYS_VENDORID 0x1057	/* Motorola */
 
 /*
- * TSEC configuration
+ * TSEC
  */
 #define CONFIG_TSEC_ENET		/* TSEC ethernet support */
 
-#ifndef CONFIG_NET_MULTI
-#define CONFIG_NET_MULTI		1
-#endif
-
-#define CONFIG_GMII			1	/* MII PHY management */
-#define CONFIG_TSEC1		1
+#define CONFIG_NET_MULTI
+#define CONFIG_GMII			/* MII PHY management */
 
+#ifdef CONFIG_TSEC1
+#define CONFIG_HAS_ETH0
 #define CONFIG_TSEC1_NAME	"TSEC0"
-#define CONFIG_TSEC2		1
+#define CFG_TSEC1_OFFSET	0x24000
+#define TSEC1_PHY_ADDR		0x1c
+#define TSEC1_FLAGS		TSEC_GIGABIT
+#define TSEC1_PHYIDX		0
+#endif
+
+#ifdef CONFIG_TSEC2
+#define CONFIG_HAS_ETH1
 #define CONFIG_TSEC2_NAME	"TSEC1"
-#define TSEC1_PHY_ADDR			0x1c
-#define TSEC2_PHY_ADDR			4
-#define TSEC1_FLAGS			TSEC_GIGABIT
-#define TSEC2_FLAGS			TSEC_GIGABIT
-#define TSEC1_PHYIDX			0
-#define TSEC2_PHYIDX			0
+#define CFG_TSEC2_OFFSET	0x25000
+#define TSEC2_PHY_ADDR		4
+#define TSEC2_FLAGS		TSEC_GIGABIT
+#define TSEC2_PHYIDX		0
+#endif
+
 
 /* Options are: TSEC[0-1] */
 #define CONFIG_ETHPRIME			"TSEC1"
@@ -496,10 +523,13 @@
  */
 #define CONFIG_ENV_OVERWRITE
 
+#ifdef CONFIG_HAS_ETH0
 #define CONFIG_ETHADDR		00:E0:0C:00:95:01
-#define CONFIG_HAS_ETH1
-#define CONFIG_HAS_ETH0
+#endif
+
+#ifdef CONFIG_HAS_ETH1
 #define CONFIG_ETH1ADDR		00:E0:0C:00:95:02
+#endif
 
 #define CONFIG_IPADDR		10.0.0.2
 #define CONFIG_SERVERIP		10.0.0.1
diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h
index 48c2736..0e50186 100644
--- a/include/configs/MPC8349ITX.h
+++ b/include/configs/MPC8349ITX.h
@@ -68,12 +68,16 @@
 
 #define CFG_IMMR		0xE0000000	/* The IMMR is relocated to here */
 
+#define CONFIG_MISC_INIT_F
+#define CONFIG_MISC_INIT_R
 
-/* On-board devices */
+/*
+ * On-board devices
+ */
 
 #ifdef CONFIG_MPC8349ITX
 #define CONFIG_COMPACT_FLASH	/* The CF card interface on the back of the board */
-#define CONFIG_VSC7385		/* The Vitesse 7385 5-port switch */
+#define CONFIG_VSC7385_ENET	/* VSC7385 ethernet support */
 #endif
 
 #define CONFIG_PCI
@@ -88,9 +92,6 @@
 /* I2C */
 #ifdef CONFIG_HARD_I2C
 
-#define CONFIG_MISC_INIT_F
-#define CONFIG_MISC_INIT_R
-
 #define CONFIG_FSL_I2C
 #define CONFIG_I2C_MULTI_BUS
 #define CONFIG_I2C_CMD_TREE
@@ -190,6 +191,18 @@ boards, we say we have two, but don't display a message if we find only one. */
 #define CFG_FLASH_SIZE		16		/* FLASH size in MB */
 #define CFG_FLASH_SIZE_SHIFT	4		/* log2 of the above value */
 
+/* Vitesse 7385 */
+
+#ifdef CONFIG_VSC7385_ENET
+
+#define CONFIG_TSEC2
+
+/* The flash address and size of the VSC7385 firmware image */
+#define CONFIG_VSC7385_IMAGE		0xFEFFE000
+#define CONFIG_VSC7385_IMAGE_SIZE	8192
+
+#endif
+
 /*
  * BRx, ORx, LBLAWBARx, and LBLAWARx
  */
@@ -205,10 +218,10 @@ boards, we say we have two, but don't display a message if we find only one. */
 
 /* Vitesse 7385 */
 
-#ifdef CONFIG_VSC7385
-
 #define CFG_VSC7385_BASE	0xF8000000
 
+#ifdef CONFIG_VSC7385_ENET
+
 #define CFG_BR1_PRELIM		(CFG_VSC7385_BASE | BR_PS_8 | BR_V)
 #define CFG_OR1_PRELIM		(OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
 				OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX | \
@@ -384,7 +397,7 @@ boards, we say we have two, but don't display a message if we find only one. */
 #define CONFIG_HAS_ETH1
 #define CONFIG_TSEC2_NAME  "TSEC1"
 #define CFG_TSEC2_OFFSET	0x25000
-#define CONFIG_UNKNOWN_TSEC	/* TSEC2 is proprietary */
+
 #define TSEC2_PHY_ADDR		4
 #define TSEC2_PHYIDX		0
 #define TSEC2_FLAGS		TSEC_GIGABIT
@@ -619,11 +632,11 @@ boards, we say we have two, but don't display a message if we find only one. */
  */
 #define CONFIG_ENV_OVERWRITE
 
-#ifdef CONFIG_TSEC1
+#ifdef CONFIG_HAS_ETH0
 #define CONFIG_ETHADDR		00:E0:0C:00:8C:01
 #endif
 
-#ifdef CONFIG_TSEC2
+#ifdef CONFIG_HAS_ETH1
 #define CONFIG_ETH1ADDR		00:E0:0C:00:8C:02
 #endif
 
diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h
index 2da4f29..066197f 100644
--- a/include/configs/MPC837XERDB.h
+++ b/include/configs/MPC837XERDB.h
@@ -32,6 +32,14 @@
 
 #define CONFIG_PCI	1
 
+#define CONFIG_MISC_INIT_R
+
+/*
+ * On-board devices
+ */
+#define CONFIG_TSEC_ENET		/* TSEC Ethernet support */
+#define CONFIG_VSC7385_ENET
+
 /*
  * System Clock Setup
  */
@@ -118,6 +126,22 @@
 #define CFG_IMMR		0xE0000000
 
 /*
+ * Device configurations
+ */
+
+/* Vitesse 7385 */
+
+#ifdef CONFIG_VSC7385_ENET
+
+#define CONFIG_TSEC2
+
+/* The flash address and size of the VSC7385 firmware image */
+#define CONFIG_VSC7385_IMAGE		0xFE7FE000
+#define CONFIG_VSC7385_IMAGE_SIZE	8192
+
+#endif
+
+/*
  * DDR Setup
  */
 #define CFG_DDR_BASE		0x00000000 /* DDR is system memory */
@@ -251,15 +275,19 @@
 #define CFG_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
 #define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
 
+/* Vitesse 7385 */
+
 #define CFG_VSC7385_BASE	0xF0000000
 
-/* VSC7385 Gigabit Switch support */
-#define CONFIG_VSC7385_ENET
+#ifdef CONFIG_VSC7385_ENET
+
 #define CFG_BR2_PRELIM		0xf0000801		/* Base address */
 #define CFG_OR2_PRELIM		0xfffe09ff		/* 128K bytes*/
 #define CFG_LBLAWBAR2_PRELIM	CFG_VSC7385_BASE	/* Access Base */
 #define CFG_LBLAWAR2_PRELIM	0x80000010		/* Access Size 128K */
 
+#endif
+
 /*
  * Serial Port
  */
@@ -324,43 +352,43 @@
 #define CONFIG_NET_MULTI
 #define CONFIG_PCI_PNP		/* do pci plug-and-play */
 
-#undef CONFIG_EEPRO100
 #undef CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
 #define CFG_PCI_SUBSYS_VENDORID 0x1957	/* Freescale */
 #endif	/* CONFIG_PCI */
 
-#ifndef CONFIG_NET_MULTI
-#define CONFIG_NET_MULTI	1
-#endif
-
 /*
  * TSEC
  */
-#define CONFIG_TSEC_ENET	/* TSEC ethernet support */
-#define CFG_TSEC1_OFFSET	0x24000
-#define CFG_TSEC1		(CFG_IMMR+CFG_TSEC1_OFFSET)
-#define CFG_TSEC2_OFFSET	0x25000
-#define CFG_TSEC2		(CFG_IMMR+CFG_TSEC2_OFFSET)
+#ifdef CONFIG_TSEC_ENET
 
-/*
- * TSEC ethernet configuration
- */
-#define CONFIG_GMII			1	/* MII PHY management */
-#define CONFIG_TSEC1			1
+#define CONFIG_NET_MULTI
+#define CONFIG_GMII			/* MII PHY management */
+
+#define CONFIG_TSEC1
+
+#ifdef CONFIG_TSEC1
+#define CONFIG_HAS_ETH0
 #define CONFIG_TSEC1_NAME		"TSEC0"
-#define CONFIG_TSEC2			1
-#define CONFIG_TSEC2_NAME		"TSEC1"
+#define CFG_TSEC1_OFFSET		0x24000
 #define TSEC1_PHY_ADDR			2
-#define TSEC2_PHY_ADDR			0x1c
 #define TSEC1_FLAGS			(TSEC_GIGABIT | TSEC_REDUCED)
-#define TSEC2_FLAGS			(TSEC_GIGABIT | TSEC_REDUCED)
 #define TSEC1_PHYIDX			0
-#define TSEC2_PHYIDX			0
+#endif
 
+#ifdef CONFIG_TSEC2
+#define CONFIG_HAS_ETH1
+#define CONFIG_TSEC2_NAME		"TSEC1"
+#define CFG_TSEC2_OFFSET		0x25000
+#define TSEC2_PHY_ADDR			0x1c
+#define TSEC2_FLAGS			(TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC2_PHYIDX			0
+#endif
 
 /* Options are: TSEC[0-1] */
 #define CONFIG_ETHPRIME			"TSEC0"
 
+#endif
+
 /*
  * Environment
  */
@@ -529,10 +557,13 @@
  */
 #define CONFIG_ENV_OVERWRITE
 
-#define CONFIG_HAS_ETH0				/* add support for "ethaddr" */
-#define CONFIG_ETHADDR	00:04:9f:ef:04:01
-#define CONFIG_HAS_ETH1				/* add support for "eth1addr" */
-#define CONFIG_ETH1ADDR	00:04:9f:ef:04:02
+#ifdef CONFIG_HAS_ETH0
+#define CONFIG_ETHADDR		00:04:9f:ef:04:01
+#endif
+
+#ifdef CONFIG_HAS_ETH1
+#define CONFIG_ETH1ADDR		00:04:9f:ef:04:02
+#endif
 
 #define CONFIG_IPADDR		10.0.0.2
 #define CONFIG_SERVERIP		10.0.0.1
diff --git a/include/vsc7385.h b/include/vsc7385.h
new file mode 100644
index 0000000..0432499
--- /dev/null
+++ b/include/vsc7385.h
@@ -0,0 +1,13 @@
+/*
+ * Header file for vsc7385.c
+ *
+ * Author: Timur Tabi <timur@freescale.com>
+ *
+ * Copyright 2008 Freescale Semiconductor, Inc.  This file is licensed
+ * under the terms of the GNU General Public License version 2.  This
+ * program is licensed "as is" without any warranty of any kind, whether
+ * express or implied.
+ */
+
+int vsc7385_upload_firmware(void *firmware, unsigned int size);
+
-- 
1.5.2.4

[U-Boot-Users] [PATCH] 83xx: Add Vitesse VSC7385 firmware uploading

[Kim Phillips]

On Wed,  6 Feb 2008 13:19:25 -0600
Timur Tabi <timur@freescale.com> wrote:

> The Vitesse VSC7385 is a 5-port switch found on the Freescale MPC8349E-mITX
> and other boards.  A small firwmare must be uploaded to its on-board memory
> before it can be enabled.  This patch adds the code which uploads firmware
> (but not the firmware itself) and updates the MPC8349E-mITX, MPC8313E-RDB,
> and MPC837XE-RDB boards to use that code.
> 
> Previously, this feature was provided by a U-Boot application that was
> made available only on Freescale BSPs.  The VSC7385 firmware must still
> be obtained separately, but at least there is no longer a need for a separate
> application.

I'd prefer firmware uploading bits remain apps (perhaps in examples/?)
but I don't know the "U-Boot Philosophy" for this area..

> 
> Changed CONFIG_VSC7385 to CONFIG_VSC7385_ENET.  Also cleaned up the board
> header files to make selecting the VSC7385 easier to control.
> 
> Signed-off-by: Timur Tabi <timur@freescale.com>
> ---
> 
> This patch is for U-Boot 1.3.3
> 
>  board/freescale/mpc8313erdb/mpc8313erdb.c |   21 ++++++
>  board/freescale/mpc8349itx/mpc8349itx.c   |   15 ++++-
>  board/freescale/mpc837xerdb/mpc837xerdb.c |   27 ++++++--
>  drivers/net/Makefile                      |    1 +
>  drivers/net/vsc7385.c                     |  100 +++++++++++++++++++++++++++++
>  include/configs/MPC8313ERDB.h             |   88 +++++++++++++++++--------
>  include/configs/MPC8349ITX.h              |   33 +++++++---
>  include/configs/MPC837XERDB.h             |   83 ++++++++++++++++--------
>  include/vsc7385.h                         |   13 ++++
>  9 files changed, 310 insertions(+), 71 deletions(-)
>  create mode 100644 drivers/net/vsc7385.c
>  create mode 100644 include/vsc7385.h

drivers/net bits go through net maintainer, Ben Warren (separate patch).

> diff --git a/drivers/net/vsc7385.c b/drivers/net/vsc7385.c
> new file mode 100644
> index 0000000..39b077f
> --- /dev/null
> +++ b/drivers/net/vsc7385.c
> @@ -0,0 +1,100 @@
> +/*
> + * Vitesse 7385 Switch Firmware Upload
> + *
> + * Author: Timur Tabi <timur@freescale.com>
> + *
> + * Copyright 2008 Freescale Semiconductor, Inc.  This file is licensed
> + * under the terms of the GNU General Public License version 2.  This
> + * program is licensed "as is" without any warranty of any kind, whether
> + * express or implied.
> + *
> + * This module uploads proprietary firmware for the Vitesse VSC7385 5-port
> + * switch.
> + */
> +
> +#include <config.h>
> +#include <common.h>
> +#include <asm/io.h>
> +#include <asm/errno.h>

This breaks some archs.

> +
> +#ifdef CONFIG_VSC7385_ENET
> +
> +/*
> + * Upload a Vitesse VSC7385 firmware image to the hardware
> + *
> + * This function takes a pointer to a VSC7385 firmware image and a size, and
> + * uploads that firmware to the VSC7385.
> + *
> + * This firmware is typically located at a board-specific flash address,
> + * and the size is typically 8KB.
> + *
> + * The firmware is Vitesse proprietary.
> + *
> + * Further details on the register information can be obtained from Vitesse.
> + */
> +int vsc7385_upload_firmware(void *firmware, unsigned int size)
> +{
> +	u8 *fw = firmware;
> +
> +	u32 *gloreset = (u32 *) (CFG_VSC7385_BASE + 0x1c050);
> +	u32 *icpu_ctrl = (u32 *) (CFG_VSC7385_BASE + 0x1c040);
> +	u32 *icpu_addr = (u32 *) (CFG_VSC7385_BASE + 0x1c044);
> +	u32 *icpu_data = (u32 *) (CFG_VSC7385_BASE + 0x1c048);
> +	u32 *chipid = (u32 *) (CFG_VSC7385_BASE + 0x1c060);
> +	u32 *icpu_rom_map = (u32 *) (CFG_VSC7385_BASE + 0x1c070);
> +
> +	unsigned int i;
> +	int ret = 0;
> +
> +	out_be32(gloreset, 3);
> +	udelay(200);
> +
> +	out_be32(icpu_ctrl, 142);
> +	udelay(20);
> +
> +	out_be32(icpu_rom_map, 1);
> +	udelay(20);
> +
> +        /* Write the firmware to I-RAM */
> +	out_be32(icpu_addr, 0);
> +	udelay(20);
> +
> +	for (i = 0; i < size; i++) {
> +		out_be32(icpu_data, fw[i]);
> +		udelay(20);
> +		if (ctrlc())
> +			return -EINTR;
> +	}
> +
> +	/* Read back and compare */
> +	out_be32(icpu_addr, 0);
> +	udelay(20);
> +
> +	for (i = 0; i < size; i++) {
> +		u8 value;
> +
> +		value = (u8) in_be32(icpu_data);
> +		udelay(20);
> +		if (value != fw[i]) {
> +			debug("VSC7385: Upload mismatch: address 0x%x, "
> +                              "read value 0x%x, image value 0x%x\n",
> +                              i, value, fw[i]);
> +
> +			return -EIO;
> +		}
> +		if (ctrlc())
> +			break;
> +	}
> +
> +	out_be32(icpu_ctrl, 11);
> +	udelay(20);
> +
> +#ifdef DEBUG
> +	printf("VSC7385: Chip ID is %08x\n", in_be32(chipid));
> +	udelay(20);
> +#endif
> +
> +	return 0;
> +}
> +
> +#endif

who is the original author of this code?

Kim

[U-Boot-Users] [PATCH] 83xx: Add Vitesse VSC7385 firmware uploading

[Timur Tabi]

Kim Phillips wrote:

> I'd prefer firmware uploading bits remain apps (perhaps in examples/?)
> but I don't know the "U-Boot Philosophy" for this area..

The whole point behind this patch is to get rid of the currently application and 
make this a native feature of U-Boot.

In this regard, it is no different than my QE firmware patch.

> drivers/net bits go through net maintainer, Ben Warren (separate patch).

I can break it into two patches.

>> +#include <config.h>
>> +#include <common.h>
>> +#include <asm/io.h>
>> +#include <asm/errno.h>
> 
> This breaks some archs.

Which ones?  How?  These header files look pretty harmless to me.  What if I did 
this:

#include <config.h>

#ifdef CONFIG_VSC7385_ENET

#include <common.h>
#include <asm/io.h>
#include <asm/errno.h>

> who is the original author of this code?

One of our BSP developers.  I took the code from his application and cleaned it up.

-- 
Timur Tabi
Linux kernel developer at Freescale

[U-Boot-Users] [PATCH] 83xx: Add Vitesse VSC7385 firmware uploading

[Wolfgang Denk]

In message <20080207162910.9d78d106.kim.phillips@freescale.com> you wrote:
>
> > Previously, this feature was provided by a U-Boot application that was
> > made available only on Freescale BSPs.  The VSC7385 firmware must still
> > be obtained separately, but at least there is no longer a need for a separate
> > application.
> 
> I'd prefer firmware uploading bits remain apps (perhaps in examples/?)
> but I don't know the "U-Boot Philosophy" for this area..

When loading the firmare is required (or  desirable)  in  U-Boot,  it
should  be  integral  part  of U-Boot. Loading the switch FW might be
needed for network operations in U-Boot, so it makes sense to  me  to
add this to regular U-Boot code.


Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
... Jesus cried with a loud voice: Lazarus, come forth; the bug  hath
been  found  and  thy  program  runneth.  And  he  that was dead came
forth...                              -- John 11:43-44 [version 2.0?]

[U-Boot-Users] [PATCH] 83xx: Add Vitesse VSC7385 firmware uploading

[Ben Warren]

Hi Timur,

Just some nit-picking...

Timur Tabi wrote:
> The Vitesse VSC7385 is a 5-port switch found on the Freescale MPC8349E-mITX
> and other boards.  A small firwmare must be uploaded to its on-board memory
> before it can be enabled.  This patch adds the code which uploads firmware
> (but not the firmware itself) and updates the MPC8349E-mITX, MPC8313E-RDB,
> and MPC837XE-RDB boards to use that code.
>
>   
Is this switch able to pass traffic in a default configuration without 
this firmware or is it dead?
<snip>
> diff --git a/drivers/net/Makefile b/drivers/net/Makefile
> index b9723fa..5ae7cb7 100644
> --- a/drivers/net/Makefile
> +++ b/drivers/net/Makefile
> @@ -57,6 +57,7 @@ COBJS-y += tigon3.o
>  COBJS-y += tsec.o
>  COBJS-y += tsi108_eth.o
>  COBJS-y += uli526x.o
> +COBJS-y += vsc7385.o
>  
>  COBJS	:= $(COBJS-y)
>  SRCS 	:= $(COBJS:.o=.c)
> diff --git a/drivers/net/vsc7385.c b/drivers/net/vsc7385.c
> new file mode 100644
> index 0000000..39b077f
> --- /dev/null
> +++ b/drivers/net/vsc7385.c
>   
I'm not 100% convinced that this is network code, but my opinion isn't 
very strong and I can't really think of a better place (maybe 
device/misc or device/non_free?)
> @@ -0,0 +1,100 @@
> +/*
> + * Vitesse 7385 Switch Firmware Upload
> + *
> + * Author: Timur Tabi <timur@freescale.com>
> + *
> + * Copyright 2008 Freescale Semiconductor, Inc.  This file is licensed
> + * under the terms of the GNU General Public License version 2.  This
> + * program is licensed "as is" without any warranty of any kind, whether
> + * express or implied.
> + *
> + * This module uploads proprietary firmware for the Vitesse VSC7385 5-port
> + * switch.
> + */
> +
> +#include <config.h>
> +#include <common.h>
> +#include <asm/io.h>
> +#include <asm/errno.h>
> +
>   
I think Kim mentioned this will break some architectures. Just repeating it.
> +#ifdef CONFIG_VSC7385_ENET
> +
> +/*
> + * Upload a Vitesse VSC7385 firmware image to the hardware
> + *
> + * This function takes a pointer to a VSC7385 firmware image and a size, and
> + * uploads that firmware to the VSC7385.
> + *
> + * This firmware is typically located at a board-specific flash address,
> + * and the size is typically 8KB.
> + *
> + * The firmware is Vitesse proprietary.
> + *
> + * Further details on the register information can be obtained from Vitesse.
> + */
> +int vsc7385_upload_firmware(void *firmware, unsigned int size)
> +{
> +	u8 *fw = firmware;
> +
> +	u32 *gloreset = (u32 *) (CFG_VSC7385_BASE + 0x1c050);
> +	u32 *icpu_ctrl = (u32 *) (CFG_VSC7385_BASE + 0x1c040);
> +	u32 *icpu_addr = (u32 *) (CFG_VSC7385_BASE + 0x1c044);
> +	u32 *icpu_data = (u32 *) (CFG_VSC7385_BASE + 0x1c048);
> +	u32 *chipid = (u32 *) (CFG_VSC7385_BASE + 0x1c060);
> +	u32 *icpu_rom_map = (u32 *) (CFG_VSC7385_BASE + 0x1c070);
> +
>   
It looks to me that the data bus is 8 bits. Why are you defining 
registers as 32 bits and using 32-bit accessors?
> +	unsigned int i;
> +	int ret = 0;
> +
> +	out_be32(gloreset, 3);
> +	udelay(200);
> +
> +	out_be32(icpu_ctrl, 142);
>   
When you write to the device, can you express the value in hex? It's 
quicker for the reader (who has Vitesse datasheets, of course) to figure 
out what you're doing.
> +	udelay(20);
> +
> +	out_be32(icpu_rom_map, 1);
> +	udelay(20);
> +
> +        /* Write the firmware to I-RAM */
> +	out_be32(icpu_addr, 0);
> +	udelay(20);
> +
> +	for (i = 0; i < size; i++) {
> +		out_be32(icpu_data, fw[i]);
> +		udelay(20);
> +		if (ctrlc())
> +			return -EINTR;
> +	}
> +
> +	/* Read back and compare */
> +	out_be32(icpu_addr, 0);
> +	udelay(20);
> +
> +	for (i = 0; i < size; i++) {
> +		u8 value;
> +
> +		value = (u8) in_be32(icpu_data);
> +		udelay(20);
> +		if (value != fw[i]) {
> +			debug("VSC7385: Upload mismatch: address 0x%x, "
> +                              "read value 0x%x, image value 0x%x\n",
> +                              i, value, fw[i]);
> +
> +			return -EIO;
> +		}
> +		if (ctrlc())
> +			break;
> +	}
> +
> +	out_be32(icpu_ctrl, 11);
> +	udelay(20);
> +
> +#ifdef DEBUG
> +	printf("VSC7385: Chip ID is %08x\n", in_be32(chipid));
> +	udelay(20);
> +#endif
> +
> +	return 0;
> +}
> +
> +#endif
> diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h
> index f12a3e6..9576fa5 100644
> --- a/include/configs/MPC8313ERDB.h
> +++ b/include/configs/MPC8313ERDB.h
> @@ -38,6 +38,14 @@
>  #define CONFIG_PCI
>  #define CONFIG_83XX_GENERIC_PCI
>  
> +#define CONFIG_MISC_INIT_R
> +
> +/*
> + * On-board devices
> + */
> +#define CONFIG_VSC7385_ENET
> +
> +
>  #ifdef CFG_66MHZ
>  #define CONFIG_83XX_CLKIN	66666667	/* in Hz */
>  #elif defined(CFG_33MHZ)
> @@ -65,6 +73,22 @@
>  #define CFG_ACR_RPTCNT		3	/* Arbiter repeat count (0-7) */
>  
>  /*
> + * Device configurations
> + */
> +
> +/* Vitesse 7385 */
> +
> +#ifdef CONFIG_VSC7385_ENET
> +
> +#define CONFIG_TSEC2
> +
> +/* The flash address and size of the VSC7385 firmware image */
> +#define CONFIG_VSC7385_IMAGE		0xFE7FE000
> +#define CONFIG_VSC7385_IMAGE_SIZE	8192
> +
> +#endif
> +
> +/*
>   * DDR Setup
>   */
>  #define CFG_DDR_BASE		0x00000000	/* DDR is system memory*/
> @@ -214,19 +238,24 @@
>  #define CFG_LBLAWBAR1_PRELIM	CFG_NAND_BASE
>  #define CFG_LBLAWAR1_PRELIM	0x8000000E	/* 32KB  */
>  
> +/* local bus read write buffer mapping */
> +#define CFG_BR3_PRELIM		0xFA000801	/* map at 0xFA000000 */
>   
Like here, bits 19-20 are 01, meaning an 8-bit port
> +#define CFG_OR3_PRELIM		0xFFFF8FF7	/* 32kB */
> +#define CFG_LBLAWBAR3_PRELIM	0xFA000000
> +#define CFG_LBLAWAR3_PRELIM	0x8000000E	/* 32KB  */
> +
> +/* Vitesse 7385 */
> +
>  #define CFG_VSC7385_BASE	0xF0000000
>  
> -#define CONFIG_VSC7385_ENET			/* VSC7385 ethernet support */
> +#ifdef CONFIG_VSC7385_ENET
> +
>  #define CFG_BR2_PRELIM		0xf0000801	/* VSC7385 Base address */
>  #define CFG_OR2_PRELIM		0xfffe09ff	/* VSC7385, 128K bytes*/
>  #define CFG_LBLAWBAR2_PRELIM	CFG_VSC7385_BASE/* Access window base at VSC7385 base */
>  #define CFG_LBLAWAR2_PRELIM	0x80000010	/* Access window size 128K */
>  
> -/* local bus read write buffer mapping */
> -#define CFG_BR3_PRELIM		0xFA000801	/* map at 0xFA000000 */
> -#define CFG_OR3_PRELIM		0xFFFF8FF7	/* 32kB */
> -#define CFG_LBLAWBAR3_PRELIM	0xFA000000
> -#define CFG_LBLAWAR3_PRELIM	0x8000000E	/* 32KB  */
> +#endif
>  
>  /* pass open firmware flat tree */
>  #define CONFIG_OF_LIBFDT	1
> @@ -263,13 +292,6 @@
>  #define CFG_I2C_OFFSET		0x3000
>  #define CFG_I2C2_OFFSET		0x3100
>  
> -/* TSEC */
> -#define CFG_TSEC1_OFFSET	0x24000
> -#define CFG_TSEC1		(CFG_IMMR+CFG_TSEC1_OFFSET)
> -#define CFG_TSEC2_OFFSET	0x25000
> -#define CFG_TSEC2		(CFG_IMMR+CFG_TSEC2_OFFSET)
> -#define CONFIG_NET_MULTI
> -
>  /*
>   * General PCI
>   * Addresses are mapped 1-1.
> @@ -288,26 +310,31 @@
>  #define CFG_PCI_SUBSYS_VENDORID 0x1057	/* Motorola */
>  
>  /*
> - * TSEC configuration
> + * TSEC
>   */
>  #define CONFIG_TSEC_ENET		/* TSEC ethernet support */
>  
> -#ifndef CONFIG_NET_MULTI
> -#define CONFIG_NET_MULTI		1
> -#endif
> -
> -#define CONFIG_GMII			1	/* MII PHY management */
> -#define CONFIG_TSEC1		1
> +#define CONFIG_NET_MULTI
> +#define CONFIG_GMII			/* MII PHY management */
>  
> +#ifdef CONFIG_TSEC1
> +#define CONFIG_HAS_ETH0
>  #define CONFIG_TSEC1_NAME	"TSEC0"
> -#define CONFIG_TSEC2		1
> +#define CFG_TSEC1_OFFSET	0x24000
> +#define TSEC1_PHY_ADDR		0x1c
> +#define TSEC1_FLAGS		TSEC_GIGABIT
> +#define TSEC1_PHYIDX		0
> +#endif
> +
> +#ifdef CONFIG_TSEC2
> +#define CONFIG_HAS_ETH1
>  #define CONFIG_TSEC2_NAME	"TSEC1"
> -#define TSEC1_PHY_ADDR			0x1c
> -#define TSEC2_PHY_ADDR			4
> -#define TSEC1_FLAGS			TSEC_GIGABIT
> -#define TSEC2_FLAGS			TSEC_GIGABIT
> -#define TSEC1_PHYIDX			0
> -#define TSEC2_PHYIDX			0
> +#define CFG_TSEC2_OFFSET	0x25000
> +#define TSEC2_PHY_ADDR		4
> +#define TSEC2_FLAGS		TSEC_GIGABIT
> +#define TSEC2_PHYIDX		0
> +#endif
> +
>  
>  /* Options are: TSEC[0-1] */
>  #define CONFIG_ETHPRIME			"TSEC1"
> @@ -496,10 +523,13 @@
>   */
>  #define CONFIG_ENV_OVERWRITE
>  
> +#ifdef CONFIG_HAS_ETH0
>  #define CONFIG_ETHADDR		00:E0:0C:00:95:01
> -#define CONFIG_HAS_ETH1
> -#define CONFIG_HAS_ETH0
> +#endif
> +
> +#ifdef CONFIG_HAS_ETH1
>  #define CONFIG_ETH1ADDR		00:E0:0C:00:95:02
> +#endif
>  
>  #define CONFIG_IPADDR		10.0.0.2
>  #define CONFIG_SERVERIP		10.0.0.1
> diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h
> index 48c2736..0e50186 100644
> --- a/include/configs/MPC8349ITX.h
> +++ b/include/configs/MPC8349ITX.h
> @@ -68,12 +68,16 @@
>  
>  #define CFG_IMMR		0xE0000000	/* The IMMR is relocated to here */
>  
> +#define CONFIG_MISC_INIT_F
> +#define CONFIG_MISC_INIT_R
>  
> -/* On-board devices */
> +/*
> + * On-board devices
> + */
>  
>  #ifdef CONFIG_MPC8349ITX
>  #define CONFIG_COMPACT_FLASH	/* The CF card interface on the back of the board */
> -#define CONFIG_VSC7385		/* The Vitesse 7385 5-port switch */
> +#define CONFIG_VSC7385_ENET	/* VSC7385 ethernet support */
>  #endif
>  
>  #define CONFIG_PCI
> @@ -88,9 +92,6 @@
>  /* I2C */
>  #ifdef CONFIG_HARD_I2C
>  
> -#define CONFIG_MISC_INIT_F
> -#define CONFIG_MISC_INIT_R
> -
>  #define CONFIG_FSL_I2C
>  #define CONFIG_I2C_MULTI_BUS
>  #define CONFIG_I2C_CMD_TREE
> @@ -190,6 +191,18 @@ boards, we say we have two, but don't display a message if we find only one. */
>  #define CFG_FLASH_SIZE		16		/* FLASH size in MB */
>  #define CFG_FLASH_SIZE_SHIFT	4		/* log2 of the above value */
>  
> +/* Vitesse 7385 */
> +
> +#ifdef CONFIG_VSC7385_ENET
> +
> +#define CONFIG_TSEC2
> +
> +/* The flash address and size of the VSC7385 firmware image */
> +#define CONFIG_VSC7385_IMAGE		0xFEFFE000
> +#define CONFIG_VSC7385_IMAGE_SIZE	8192
> +
> +#endif
> +
>  /*
>   * BRx, ORx, LBLAWBARx, and LBLAWARx
>   */
> @@ -205,10 +218,10 @@ boards, we say we have two, but don't display a message if we find only one. */
>  
>  /* Vitesse 7385 */
>  
> -#ifdef CONFIG_VSC7385
> -
>  #define CFG_VSC7385_BASE	0xF8000000
>  
> +#ifdef CONFIG_VSC7385_ENET
> +
>  #define CFG_BR1_PRELIM		(CFG_VSC7385_BASE | BR_PS_8 | BR_V)
>   
Here you use mnemonics for describing the base register settings. I know 
it's not new code, but it would be nice to be consistent
>  #define CFG_OR1_PRELIM		(OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
>  				OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX | \
> @@ -384,7 +397,7 @@ boards, we say we have two, but don't display a message if we find only one. */
>  #define CONFIG_HAS_ETH1
>  #define CONFIG_TSEC2_NAME  "TSEC1"
>  #define CFG_TSEC2_OFFSET	0x25000
> -#define CONFIG_UNKNOWN_TSEC	/* TSEC2 is proprietary */
> +
>  #define TSEC2_PHY_ADDR		4
>  #define TSEC2_PHYIDX		0
>  #define TSEC2_FLAGS		TSEC_GIGABIT
> @@ -619,11 +632,11 @@ boards, we say we have two, but don't display a message if we find only one. */
>   */
>  #define CONFIG_ENV_OVERWRITE
>  
> -#ifdef CONFIG_TSEC1
> +#ifdef CONFIG_HAS_ETH0
>  #define CONFIG_ETHADDR		00:E0:0C:00:8C:01
>  #endif
>  
> -#ifdef CONFIG_TSEC2
> +#ifdef CONFIG_HAS_ETH1
>  #define CONFIG_ETH1ADDR		00:E0:0C:00:8C:02
>  #endif
>  
> diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h
> index 2da4f29..066197f 100644
> --- a/include/configs/MPC837XERDB.h
> +++ b/include/configs/MPC837XERDB.h
> @@ -32,6 +32,14 @@
>  
>  #define CONFIG_PCI	1
>  
> +#define CONFIG_MISC_INIT_R
> +
> +/*
> + * On-board devices
> + */
> +#define CONFIG_TSEC_ENET		/* TSEC Ethernet support */
> +#define CONFIG_VSC7385_ENET
> +
>  /*
>   * System Clock Setup
>   */
> @@ -118,6 +126,22 @@
>  #define CFG_IMMR		0xE0000000
>  
>  /*
> + * Device configurations
> + */
> +
> +/* Vitesse 7385 */
> +
> +#ifdef CONFIG_VSC7385_ENET
> +
> +#define CONFIG_TSEC2
> +
> +/* The flash address and size of the VSC7385 firmware image */
> +#define CONFIG_VSC7385_IMAGE		0xFE7FE000
> +#define CONFIG_VSC7385_IMAGE_SIZE	8192
> +
> +#endif
> +
> +/*
>   * DDR Setup
>   */
>  #define CFG_DDR_BASE		0x00000000 /* DDR is system memory */
> @@ -251,15 +275,19 @@
>  #define CFG_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
>  #define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
>  
> +/* Vitesse 7385 */
> +
>  #define CFG_VSC7385_BASE	0xF0000000
>  
> -/* VSC7385 Gigabit Switch support */
> -#define CONFIG_VSC7385_ENET
> +#ifdef CONFIG_VSC7385_ENET
> +
>  #define CFG_BR2_PRELIM		0xf0000801		/* Base address */
>  #define CFG_OR2_PRELIM		0xfffe09ff		/* 128K bytes*/
>  #define CFG_LBLAWBAR2_PRELIM	CFG_VSC7385_BASE	/* Access Base */
>  #define CFG_LBLAWAR2_PRELIM	0x80000010		/* Access Size 128K */
>  
> +#endif
> +
>  /*
>   * Serial Port
>   */
> @@ -324,43 +352,43 @@
>  #define CONFIG_NET_MULTI
>  #define CONFIG_PCI_PNP		/* do pci plug-and-play */
>  
> -#undef CONFIG_EEPRO100
>  #undef CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
>  #define CFG_PCI_SUBSYS_VENDORID 0x1957	/* Freescale */
>  #endif	/* CONFIG_PCI */
>  
> -#ifndef CONFIG_NET_MULTI
> -#define CONFIG_NET_MULTI	1
> -#endif
> -
>  /*
>   * TSEC
>   */
> -#define CONFIG_TSEC_ENET	/* TSEC ethernet support */
> -#define CFG_TSEC1_OFFSET	0x24000
> -#define CFG_TSEC1		(CFG_IMMR+CFG_TSEC1_OFFSET)
> -#define CFG_TSEC2_OFFSET	0x25000
> -#define CFG_TSEC2		(CFG_IMMR+CFG_TSEC2_OFFSET)
> +#ifdef CONFIG_TSEC_ENET
>  
> -/*
> - * TSEC ethernet configuration
> - */
> -#define CONFIG_GMII			1	/* MII PHY management */
> -#define CONFIG_TSEC1			1
> +#define CONFIG_NET_MULTI
> +#define CONFIG_GMII			/* MII PHY management */
> +
> +#define CONFIG_TSEC1
> +
> +#ifdef CONFIG_TSEC1
> +#define CONFIG_HAS_ETH0
>  #define CONFIG_TSEC1_NAME		"TSEC0"
> -#define CONFIG_TSEC2			1
> -#define CONFIG_TSEC2_NAME		"TSEC1"
> +#define CFG_TSEC1_OFFSET		0x24000
>  #define TSEC1_PHY_ADDR			2
> -#define TSEC2_PHY_ADDR			0x1c
>  #define TSEC1_FLAGS			(TSEC_GIGABIT | TSEC_REDUCED)
> -#define TSEC2_FLAGS			(TSEC_GIGABIT | TSEC_REDUCED)
>  #define TSEC1_PHYIDX			0
> -#define TSEC2_PHYIDX			0
> +#endif
>  
> +#ifdef CONFIG_TSEC2
> +#define CONFIG_HAS_ETH1
> +#define CONFIG_TSEC2_NAME		"TSEC1"
> +#define CFG_TSEC2_OFFSET		0x25000
> +#define TSEC2_PHY_ADDR			0x1c
> +#define TSEC2_FLAGS			(TSEC_GIGABIT | TSEC_REDUCED)
> +#define TSEC2_PHYIDX			0
> +#endif
>  
>  /* Options are: TSEC[0-1] */
>  #define CONFIG_ETHPRIME			"TSEC0"
>  
> +#endif
> +
>  /*
>   * Environment
>   */
> @@ -529,10 +557,13 @@
>   */
>  #define CONFIG_ENV_OVERWRITE
>  
> -#define CONFIG_HAS_ETH0				/* add support for "ethaddr" */
> -#define CONFIG_ETHADDR	00:04:9f:ef:04:01
> -#define CONFIG_HAS_ETH1				/* add support for "eth1addr" */
> -#define CONFIG_ETH1ADDR	00:04:9f:ef:04:02
> +#ifdef CONFIG_HAS_ETH0
> +#define CONFIG_ETHADDR		00:04:9f:ef:04:01
> +#endif
> +
> +#ifdef CONFIG_HAS_ETH1
> +#define CONFIG_ETH1ADDR		00:04:9f:ef:04:02
> +#endif
>  
>  #define CONFIG_IPADDR		10.0.0.2
>  #define CONFIG_SERVERIP		10.0.0.1
> diff --git a/include/vsc7385.h b/include/vsc7385.h
> new file mode 100644
> index 0000000..0432499
> --- /dev/null
> +++ b/include/vsc7385.h
> @@ -0,0 +1,13 @@
> +/*
> + * Header file for vsc7385.c
> + *
> + * Author: Timur Tabi <timur@freescale.com>
> + *
> + * Copyright 2008 Freescale Semiconductor, Inc.  This file is licensed
> + * under the terms of the GNU General Public License version 2.  This
> + * program is licensed "as is" without any warranty of any kind, whether
> + * express or implied.
> + */
> +
> +int vsc7385_upload_firmware(void *firmware, unsigned int size);
> +
>   

[U-Boot-Users] [PATCH] 83xx: Add Vitesse VSC7385 firmware uploading

[Timur Tabi]

Ben Warren wrote:

> Is this switch able to pass traffic in a default configuration without 
> this firmware or is it dead?

Without the firmware, the switch is completely dead.

> I'm not 100% convinced that this is network code, but my opinion isn't 
> very strong and I can't really think of a better place (maybe 
> device/misc or device/non_free?)

I'll move it to device/misc if you want.  device/non_free doesn't exist so I
don't want to create it.

>> +#include <config.h>
>> +#include <common.h>
>> +#include <asm/io.h>
>> +#include <asm/errno.h>
>> +
>>   
> I think Kim mentioned this will break some architectures. Just repeating it.

Yeah, I'm still waiting for someone to tell me why.  In the meantime, I've done 
this:

#include <config.h>

#ifdef CONFIG_VSC7385_ENET

#include <common.h>
#include <asm/io.h>
#include <asm/errno.h>

> It looks to me that the data bus is 8 bits. Why are you defining 
> registers as 32 bits and using 32-bit accessors?

Beats me.  The programming for this chip is really weird, the documentation is
under NDA, and I didn't write the original code.  Mine is a little prettier than
the original
(http://www.bitshrine.org/gpp/u-boot-1.2.0-mpc837xerdb-vsc7385-load.patch), but
I'm not going to change the actual I/O operations.

> When you write to the device, can you express the value in hex? It's 
> quicker for the reader (who has Vitesse datasheets, of course) to figure 
> out what you're doing.

Sure, I'll change it.

> Here you use mnemonics for describing the base register settings. I know 
> it's not new code, but it would be nice to be consistent

All of the Freescale header files could be scrubbed.  I figured I was already
making enough changes.  They *should* be using mnemonics for everything.

-- 
Timur Tabi
Linux kernel developer at Freescale

[U-Boot-Users] [PATCH] 83xx: Add Vitesse VSC7385 firmware uploading

[Scott Wood]

Timur Tabi wrote:
>>> +#include <config.h>
>>> +#include <common.h>
>>> +#include <asm/io.h>
>>> +#include <asm/errno.h>
>>> +
>>>   
>> I think Kim mentioned this will break some architectures. Just repeating it.
> 
> Yeah, I'm still waiting for someone to tell me why.

Not every architecture has an io.h and an errno.h.

-Scott

[U-Boot-Users] [PATCH] 83xx: Add Vitesse VSC7385 firmware uploading

[Ben Warren]

On Feb 8, 2008 11:44 AM, Timur Tabi <timur@freescale.com> wrote:
> Ben Warren wrote:
>
> > Is this switch able to pass traffic in a default configuration without
> > this firmware or is it dead?
>
> Without the firmware, the switch is completely dead.

OK, good to know.  What a lovely feature.
>
> > I'm not 100% convinced that this is network code, but my opinion isn't
> > very strong and I can't really think of a better place (maybe
> > device/misc or device/non_free?)
>
> I'll move it to device/misc if you want.  device/non_free doesn't exist so I
> don't want to create it.
>
Don't worry about it.  drivers/net is OK
> >> +#include <config.h>
> >> +#include <common.h>
> >> +#include <asm/io.h>
> >> +#include <asm/errno.h>
> >> +
> >>
> > I think Kim mentioned this will break some architectures. Just repeating it.
>
> Yeah, I'm still waiting for someone to tell me why.  In the meantime, I've done
> this:
>
> #include <config.h>
>
> #ifdef CONFIG_VSC7385_ENET
>
> #include <common.h>
> #include <asm/io.h>
> #include <asm/errno.h>
>
> > It looks to me that the data bus is 8 bits. Why are you defining
> > registers as 32 bits and using 32-bit accessors?
>
> Beats me.  The programming for this chip is really weird, the documentation is
> under NDA, and I didn't write the original code.  Mine is a little prettier than
> the original
> (http://www.bitshrine.org/gpp/u-boot-1.2.0-mpc837xerdb-vsc7385-load.patch), but
> I'm not going to change the actual I/O operations.
>
The problem is that you're artificially making this a PowerPC-only
part.  If you used 8-bit accessors endianness wouldn't matter and
other architectures could use this without changes (notwithstanding
the #includes...)

> > When you write to the device, can you express the value in hex? It's
> > quicker for the reader (who has Vitesse datasheets, of course) to figure
> > out what you're doing.
>
> Sure, I'll change it.
>
Cool, thanks.

> > Here you use mnemonics for describing the base register settings. I know
> > it's not new code, but it would be nice to be consistent
>
> All of the Freescale header files could be scrubbed.  I figured I was already
> making enough changes.  They *should* be using mnemonics for everything.
>

Problem certainly not limited to Freescale code :)

[U-Boot-Users] [PATCH] 83xx: Add Vitesse VSC7385 firmware uploading

[Timur Tabi]

Ben Warren wrote:

> The problem is that you're artificially making this a PowerPC-only
> part.  If you used 8-bit accessors endianness wouldn't matter and
> other architectures could use this without changes (notwithstanding
> the #includes...)

Ok, I will try to figure out how to make 8-bit accesses work.  I'll post an 
update later this week.

-- 
Timur Tabi
Linux kernel developer at Freescale

[U-Boot-Users] [PATCH] 83xx: Add Vitesse VSC7385 firmware uploading

[Ben Warren]

Timur Tabi wrote:
> Ben Warren wrote:
>
>> The problem is that you're artificially making this a PowerPC-only
>> part.  If you used 8-bit accessors endianness wouldn't matter and
>> other architectures could use this without changes (notwithstanding
>> the #includes...)
>
> Ok, I will try to figure out how to make 8-bit accesses work.  I'll 
> post an update later this week.
>
Thanks buddy.  It should be pretty easy.  Sorry for making this such a 
long and drawn-out process.

regards,
Ben