From mboxrd@z Thu Jan 1 00:00:00 1970 From: Luigi 'Comio' Mantellini Date: Thu, 28 Feb 2008 09:23:53 +0100 Subject: [U-Boot-Users] UNCACHED_SDRAM macro issue In-Reply-To: <47B6A7AB.2060603@ruby.dti.ne.jp> References: <1202893181.26414.141.camel@cartesio> <47B3BBBD.7090707@necel.com> <1202979717.29669.87.camel@cartesio> <47B4E023.3080305@necel.com> <47B55738.9020701@necel.com> <47B6A7AB.2060603@ruby.dti.ne.jp> Message-ID: <1204187033.21855.5.camel@localhost> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Hi Shinya, I found the error... but it's not an u-boot issue. I'm using a (old) customized linux 2.6.10 (from my vendor) that also adds the 0xa0000000 offset to the pointers passed by u-boot, assuming that address is expressed in termos of physical address. I corrected the linux code masking and (after) addind the segment. Thanks a lot for your help. luigi On sab, 2008-02-16 at 18:06 +0900, Shinya Kuribayashi wrote: > Shinya Kuribayashi wrote: > > Shinya Kuribayashi wrote: > >>> I think that on my application the UNCACHED_SDRAM should map the address > >>> on KSEG1 (how it is now) but this simply doesn't work. Instead, using > >>> the PHYSADDR(a) macro... the kernel is able to start. > >>> > >>> I suspect that there are issues on cache management. Can be? > >> IMHO it's not related to cache. > > > > How do you set ERL and EXL bits? Please try to clear them at the > > STATUS register initialization like: > > > > reset: > > > > > > /* STATUS register */ > > mfc0 k0, CP0_STATUS > > - li k1, ~ST0_IE > > + li k1, ~(ST0_ERL | ST0_EXL | ST0_IE) > > and k0, k1 > > mtc0 k0, CP0_STATUS > > > > ERL and EXL disable exceptions. Due to this spec, we are in danger > > of overlooking something critical. If this change brings in new > > exception(s), please fix the causes of them first. Hope this helps. > > Err, sorry for confusing example. Here's the right one: > > diff --git a/cpu/mips/start.S b/cpu/mips/start.S > index c92b162..02797f7 100644 > --- a/cpu/mips/start.S > +++ b/cpu/mips/start.S > @@ -211,14 +211,20 @@ reset: > mtc0 zero, CP0_WATCHLO > mtc0 zero, CP0_WATCHHI > > + /* Inhibit deffered WATCH exception */ > + mfc0 k0, CP0_CAUSE > + li k1, ~(1UL << 22) # CP0.Cause.WP = 0 > + and k0, k0, k1 > + mtc0 k0, CP0_CAUSE > + > /* STATUS register */ > #ifdef CONFIG_TB0229 > li k0, ST0_CU0 > #else > mfc0 k0, CP0_STATUS > #endif > - li k1, ~ST0_IE > - and k0, k1 > + ori k0, (ST0_ERL | ST0_EXL | ST0_IE) > + xori k0, (ST0_ERL | ST0_EXL) > mtc0 k0, CP0_STATUS > > /* CAUSE register */ > > Again, it's highy recommended to make sure U-Boot works fine under > interrupts enabled (CP0.Status.IE=1), before digging into UNCACHED_ > SDRAM problem. > > Shinya > Industrie Dial Face S.p.A. Luigi Mantellini R&D - Software Industrie Dial Face S.p.A. Via Canzo, 4 20068 Peschiera Borromeo (MI), Italy Tel.: +39 02 5167 2813 Fax: +39 02 5167 2459 E-mail: luigi.mantellini at idf-hit.com GPG fingerprint: 3DD1 7B71 FBDF 6376 1B4A B003 175F E979 907E 1650 -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.denx.de/pipermail/u-boot/attachments/20080228/0b332f66/attachment.htm -------------- next part -------------- A non-text attachment was scrubbed... Name: idf_logo.gif Type: image/gif Size: 4122 bytes Desc: not available Url : http://lists.denx.de/pipermail/u-boot/attachments/20080228/0b332f66/attachment.gif