[U-Boot-Users] [PATCH] Some fixes to dspic, fpga, and gdc post tests for lwmon5.

Wolfgang Denk
2008-04-22T14:24:45Z

From: Yuri Tikhonov <yur@pollux.denx.de>

Signed-off-by: Dmitry Rakhchev <rda@emcraft.com>
Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
---
post/board/lwmon5/dspic.c | 2 +-
post/board/lwmon5/fpga.c | 4 ++++
post/board/lwmon5/gdc.c | 2 +-
3 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/post/board/lwmon5/dspic.c b/post/board/lwmon5/dspic.c
index e8fed89..f1c9c15 100644
--- a/post/board/lwmon5/dspic.c
+++ b/post/board/lwmon5/dspic.c
@@ -94,9 +94,9 @@ int dspic_post_test(int flags)
}

data = dspic_read(DSPIC_SYS_ERROR_REG);
- if (data != 0) ret = 1;
if (data == -1) {
post_log("dsPIC : failed read system error\n");
+ ret = 1;
} else {
post_log("dsPIC SYS-ERROR code: 0x%04X\n", data);
}
diff --git a/post/board/lwmon5/fpga.c b/post/board/lwmon5/fpga.c
index 4e3f1d5..b87fc52 100644
--- a/post/board/lwmon5/fpga.c
+++ b/post/board/lwmon5/fpga.c
@@ -39,6 +39,7 @@ DECLARE_GLOBAL_DATA_PTR;
#define FPGA_VERSION_REG 0xC4000040
#define FPGA_RAM_START 0xC4200000
#define FPGA_RAM_END 0xC4203FFF
+#define FPGA_STAT 0xC400000C

#define FPGA_PWM_CTRL_REG 0xC4000020
#define FPGA_PWM_TV_REG 0xC4000024
@@ -93,6 +94,9 @@ int fpga_post_test(int flags)
post_log("FPGA : version %u.%u\n",
(version >> 8) & 0xFF, version & 0xFF);

+ /* Enable write to FPGA RAM */
+ out_be32((void *)FPGA_STAT, in_be32((void *)FPGA_STAT) | 0x1000);
+
read_value = get_ram_size((void *)CFG_FPGA_BASE_1, 0x4000);
post_log("FPGA RAM size: %d bytes\n", read_value);

diff --git a/post/board/lwmon5/gdc.c b/post/board/lwmon5/gdc.c
index 76e5dd6..0e4f0fd 100644
--- a/post/board/lwmon5/gdc.c
+++ b/post/board/lwmon5/gdc.c
@@ -35,7 +35,7 @@

DECLARE_GLOBAL_DATA_PTR;

-#define GDC_SCRATCH_REG 0xC1FF8044
+#define GDC_SCRATCH_REG 0xC1FF8008
#define GDC_VERSION_REG 0xC1FF8084
#define GDC_RAM_START 0xC0000000
#define GDC_RAM_END 0xC2000000
--
1.5.4.2