From mboxrd@z Thu Jan 1 00:00:00 1970 From: kenneth johansson Date: Tue, 29 Apr 2008 00:59:47 +0200 Subject: [U-Boot-Users] [PATCH v2] PPC405EX(r) ECC and SDRAM Initialization Clean-ups In-Reply-To: References: Message-ID: <1209423587.8866.15.camel@duo> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On Mon, 2008-04-28 at 14:47 -0700, Grant Erickson wrote: > On 4/28/08 2:27 PM, Wolfgang Denk wrote: > > In message <1209401636-9846-1-git-send-email-gerickson@nuovations.com> you > > wrote: > >> The primary goal of these changes is to unify some of the low-level > >> SDRAM and ECC initialization code for the PPC4xx processors that use a > >> common DDR2 SDRAM controller. > >> > >> In particular, in the case of the 405EX[r], it must initialize SDRAM > >> before a primordial stack is available since OCM doesn't exist and the > >> data cache does not work for such a purpose. As a consequence, the ECC > >> (and SDRAM) initialization code must be stack-free. > > > > Stefan already asked this... I would also like to understand why the > > data cache cannot be used for initial RAM as we do on so many other > > systems? > > Agreed. The changes were based on the comments in the Kilauea and Makalu > board ports indicating that this had been attempted--twice--and didn't work. > > I am escalating with AMCC to find out if this is a processor errata, board > issue or just a programming issue that needs to be investigated further. The cache trick works fine on 405CR/405GP. Is the cache redesigned for 405EX. Why would they still call it a 405 if the core was redesigned?