* [U-Boot-Users] Adding DIU support for FSL MPC5121ADS board @ 2008-05-05 15:19 York Sun 2008-05-05 15:19 ` [U-Boot-Users] [PATCH 1/3 v2] Move pixel clock setting to board file York Sun 2008-05-09 20:10 ` [U-Boot-Users] Adding DIU support for FSL MPC5121ADS board Wolfgang Denk 0 siblings, 2 replies; 6+ messages in thread From: York Sun @ 2008-05-05 15:19 UTC (permalink / raw) To: u-boot Wolfgang, Please review the following patchset. It adds DIU support to 5121ADS board, using the existing DIU driver. Regards, York ^ permalink raw reply [flat|nested] 6+ messages in thread
* [U-Boot-Users] [PATCH 1/3 v2] Move pixel clock setting to board file 2008-05-05 15:19 [U-Boot-Users] Adding DIU support for FSL MPC5121ADS board York Sun @ 2008-05-05 15:19 ` York Sun 2008-05-05 15:20 ` [U-Boot-Users] [PATCH 2/3] Replace DPRINTF with debug York Sun 2008-05-09 20:10 ` [U-Boot-Users] Adding DIU support for FSL MPC5121ADS board Wolfgang Denk 1 sibling, 1 reply; 6+ messages in thread From: York Sun @ 2008-05-05 15:19 UTC (permalink / raw) To: u-boot The clock divider has different format in 5121 and 8610. This patch moves it to board specific code. Signed-off-by: York Sun <yorksun@freescale.com> --- board/freescale/common/fsl_diu_fb.c | 39 +++--------------------- board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c | 20 +++++++++++++ 2 files changed, 25 insertions(+), 34 deletions(-) diff --git a/board/freescale/common/fsl_diu_fb.c b/board/freescale/common/fsl_diu_fb.c index 2336f6b..9bdd4b9 100644 --- a/board/freescale/common/fsl_diu_fb.c +++ b/board/freescale/common/fsl_diu_fb.c @@ -163,8 +163,6 @@ struct diu_addr { unsigned int offset; }; -#define FSL_DIU_BASE_OFFSET 0x2C000 /* Offset of Display Interface Unit */ - /* * Modes of operation of DIU */ @@ -197,7 +195,7 @@ static void disable_lcdc(void); static int fsl_diu_enable_panel(struct fb_info *info); static int fsl_diu_disable_panel(struct fb_info *info); static int allocate_buf(struct diu_addr *buf, u32 size, u32 bytes_align); -static u32 get_busfreq(void); +void diu_set_pixel_clock(unsigned int pixclock); int fsl_diu_init(int xres, unsigned int pixel_format, @@ -209,15 +207,11 @@ int fsl_diu_init(int xres, struct diu *hw; struct fb_info *info = &fsl_fb_info; struct fb_var_screeninfo *var = &info->var; - volatile immap_t *immap = (immap_t *)CFG_IMMR; - volatile ccsr_gur_t *gur = &immap->im_gur; - volatile unsigned int *guts_clkdvdr = &gur->clkdvdr; unsigned char *gamma_table_base; unsigned int i, j; - unsigned long speed_ccb, temp, pixval; DPRINTF("Enter fsl_diu_init\n"); - dr.diu_reg = (struct diu *) (CFG_IMMR + FSL_DIU_BASE_OFFSET); + dr.diu_reg = (struct diu *) (CFG_DIU_ADDR); hw = (struct diu *) dr.diu_reg; disable_lcdc(); @@ -336,30 +330,15 @@ int fsl_diu_init(int xres, var->vsync_len << 11 | /* PW_V */ var->lower_margin; /* FP_V */ - /* Pixel Clock configuration */ - DPRINTF("DIU: Bus Frequency = %d\n", get_busfreq()); - speed_ccb = get_busfreq(); - - DPRINTF("DIU pixclock in ps - %d\n", var->pixclock); - temp = 1; - temp *= 1000000000; - temp /= var->pixclock; - temp *= 1000; - pixval = speed_ccb / temp; - DPRINTF("DIU pixval = %lu\n", pixval); - hw->syn_pol = 0; /* SYNC SIGNALS POLARITY */ hw->thresholds = 0x00037800; /* The Thresholds */ hw->int_status = 0; /* INTERRUPT STATUS */ hw->int_mask = 0; /* INT MASK */ hw->plut = 0x01F5F666; - /* Modify PXCLK in GUTS CLKDVDR */ - DPRINTF("DIU: Current value of CLKDVDR = 0x%08x\n", *guts_clkdvdr); - temp = *guts_clkdvdr & 0x2000FFFF; - *guts_clkdvdr = temp; /* turn off clock */ - *guts_clkdvdr = temp | 0x80000000 | ((pixval & 0x1F) << 16); - DPRINTF("DIU: Modified value of CLKDVDR = 0x%08x\n", *guts_clkdvdr); + /* Pixel Clock configuration */ + DPRINTF("DIU pixclock in ps - %d\n", var->pixclock); + diu_set_pixel_clock(var->pixclock); fb_initialized = 1; @@ -466,14 +445,6 @@ static void disable_lcdc(void) } } -static u32 get_busfreq(void) -{ - u32 fs_busfreq = 0; - - fs_busfreq = get_bus_freq(0); - return fs_busfreq; -} - /* * Align to 64-bit(8-byte), 32-byte, etc. */ diff --git a/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c b/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c index b70637f..4db941c 100644 --- a/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c +++ b/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c @@ -41,6 +41,26 @@ extern unsigned int FSL_Logo_BMP[]; static int xres, yres; +void diu_set_pixel_clock(unsigned int pixclock) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile ccsr_gur_t *gur = &immap->im_gur; + volatile unsigned int *guts_clkdvdr = &gur->clkdvdr; + unsigned long speed_ccb, temp, pixval; + + speed_ccb = get_bus_freq(0); + temp = 1000000000/pixclock; + temp *= 1000; + pixval = speed_ccb / temp; + debug("DIU pixval = %lu\n", pixval); + + /* Modify PXCLK in GUTS CLKDVDR */ + debug("DIU: Current value of CLKDVDR = 0x%08x\n", *guts_clkdvdr); + temp = *guts_clkdvdr & 0x2000FFFF; + *guts_clkdvdr = temp; /* turn off clock */ + *guts_clkdvdr = temp | 0x80000000 | ((pixval & 0x1F) << 16); + debug("DIU: Modified value of CLKDVDR = 0x%08x\n", *guts_clkdvdr); +} void mpc8610hpcd_diu_init(void) { -- 1.5.2.2 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* [U-Boot-Users] [PATCH 2/3] Replace DPRINTF with debug 2008-05-05 15:19 ` [U-Boot-Users] [PATCH 1/3 v2] Move pixel clock setting to board file York Sun @ 2008-05-05 15:20 ` York Sun 2008-05-05 15:20 ` [U-Boot-Users] [PATCH 3/3] Adding DIU support for Freescale 5121ADS York Sun 0 siblings, 1 reply; 6+ messages in thread From: York Sun @ 2008-05-05 15:20 UTC (permalink / raw) To: u-boot Remove DPRINTF macro and replace it with generic debug macro. Signed-off-by: York Sun <yorksun@freescale.com> --- board/freescale/common/fsl_diu_fb.c | 64 ++++++++++++++++------------------- 1 files changed, 29 insertions(+), 35 deletions(-) diff --git a/board/freescale/common/fsl_diu_fb.c b/board/freescale/common/fsl_diu_fb.c index 9bdd4b9..2e0075a 100644 --- a/board/freescale/common/fsl_diu_fb.c +++ b/board/freescale/common/fsl_diu_fb.c @@ -29,12 +29,6 @@ #include "fsl_diu_fb.h" -#ifdef DEBUG -#define DPRINTF(fmt, args...) printf("%s: " fmt,__FUNCTION__,## args) -#else -#define DPRINTF(fmt, args...) -#endif - struct fb_videomode { const char *name; /* optional */ unsigned int refresh; /* optional */ @@ -210,7 +204,7 @@ int fsl_diu_init(int xres, unsigned char *gamma_table_base; unsigned int i, j; - DPRINTF("Enter fsl_diu_init\n"); + debug("Enter fsl_diu_init\n"); dr.diu_reg = (struct diu *) (CFG_DIU_ADDR); hw = (struct diu *) dr.diu_reg; @@ -224,10 +218,10 @@ int fsl_diu_init(int xres, if (0 == fb_initialized) { allocate_buf(&gamma, 768, 32); - DPRINTF("gamma is allocated @ 0x%x\n", + debug("gamma is allocated @ 0x%x\n", (unsigned int)gamma.paddr); allocate_buf(&cursor, MAX_CURS * MAX_CURS * 2, 32); - DPRINTF("curosr is allocated @ 0x%x\n", + debug("curosr is allocated @ 0x%x\n", (unsigned int)cursor.paddr); /* create a dummy fb and dummy ad */ @@ -255,8 +249,8 @@ int fsl_diu_init(int xres, dr.diu_reg->desc[0] = (unsigned int) &dummy_ad; dr.diu_reg->desc[1] = (unsigned int) &dummy_ad; dr.diu_reg->desc[2] = (unsigned int) &dummy_ad; - DPRINTF("dummy dr.diu_reg->desc[0] = 0x%x\n", dr.diu_reg->desc[0]); - DPRINTF("dummy desc[0] = 0x%x\n", hw->desc[0]); + debug("dummy dr.diu_reg->desc[0] = 0x%x\n", dr.diu_reg->desc[0]); + debug("dummy desc[0] = 0x%x\n", hw->desc[0]); /* read mode info */ var->xres = fsl_diu_mode_db->xres; @@ -294,7 +288,7 @@ int fsl_diu_init(int xres, ad->ckmin_b = 255; gamma_table_base = gamma.paddr; - DPRINTF("gamma_table_base is allocated @ 0x%x\n", + debug("gamma_table_base is allocated @ 0x%x\n", (unsigned int)gamma_table_base); /* Prep for DIU init - gamma table */ @@ -304,7 +298,7 @@ int fsl_diu_init(int xres, *gamma_table_base++ = j; if (gamma_fix == 1) { /* fix the gamma */ - DPRINTF("Fix gamma table\n"); + debug("Fix gamma table\n"); gamma_table_base = gamma.paddr; for (i = 0; i < 256*3; i++) { gamma_table_base[i] = (gamma_table_base[i] << 2) @@ -312,7 +306,7 @@ int fsl_diu_init(int xres, } } - DPRINTF("update-lcdc: HW - %p\n Disabling DIU\n", hw); + debug("update-lcdc: HW - %p\n Disabling DIU\n", hw); /* Program DIU registers */ @@ -337,7 +331,7 @@ int fsl_diu_init(int xres, hw->plut = 0x01F5F666; /* Pixel Clock configuration */ - DPRINTF("DIU pixclock in ps - %d\n", var->pixclock); + debug("DIU pixclock in ps - %d\n", var->pixclock); diu_set_pixel_clock(var->pixclock); fb_initialized = 1; @@ -345,7 +339,7 @@ int fsl_diu_init(int xres, if (splash_bmp) { info->logo_height = fsl_diu_display_bmp(splash_bmp, 0, 0, 0); info->logo_size = info->logo_height * info->line_length; - DPRINTF("logo height %d, logo_size 0x%x\n", + debug("logo height %d, logo_size 0x%x\n", info->logo_height,info->logo_size); } @@ -374,10 +368,10 @@ static int fsl_diu_enable_panel(struct fb_info *info) struct diu *hw = dr.diu_reg; struct diu_ad *ad = &fsl_diu_fb_ad; - DPRINTF("Entered: enable_panel\n"); + debug("Entered: enable_panel\n"); if (hw->desc[0] != (unsigned int)ad) hw->desc[0] = (unsigned int)ad; - DPRINTF("desc[0] = 0x%x\n", hw->desc[0]); + debug("desc[0] = 0x%x\n", hw->desc[0]); return 0; } @@ -385,7 +379,7 @@ static int fsl_diu_disable_panel(struct fb_info *info) { struct diu *hw = dr.diu_reg; - DPRINTF("Entered: disable_panel\n"); + debug("Entered: disable_panel\n"); if (hw->desc[0] != (unsigned int)&dummy_ad) hw->desc[0] = (unsigned int)&dummy_ad; return 0; @@ -396,10 +390,10 @@ static int map_video_memory(struct fb_info *info, unsigned long bytes_align) unsigned long offset; unsigned long mask; - DPRINTF("Entered: map_video_memory\n"); + debug("Entered: map_video_memory\n"); /* allocate maximum 1280*1024 with 32bpp */ info->smem_len = 1280 * 4 *1024 + bytes_align; - DPRINTF("MAP_VIDEO_MEMORY: smem_len = %d\n", info->smem_len); + debug("MAP_VIDEO_MEMORY: smem_len = %d\n", info->smem_len); info->screen_base = malloc(info->smem_len); if (info->screen_base == NULL) { printf("Unable to allocate fb memory\n"); @@ -416,7 +410,7 @@ static int map_video_memory(struct fb_info *info, unsigned long bytes_align) info->screen_size = info->smem_len; - DPRINTF("Allocated fb @ 0x%08lx, size=%d.\n", + debug("Allocated fb @ 0x%08lx, size=%d.\n", info->smem_start, info->smem_len); return 0; @@ -426,19 +420,19 @@ static void enable_lcdc(void) { struct diu *hw = dr.diu_reg; - DPRINTF("Entered: enable_lcdc, fb_enabled = %d\n", fb_enabled); + debug("Entered: enable_lcdc, fb_enabled = %d\n", fb_enabled); if (!fb_enabled) { hw->diu_mode = dr.mode; fb_enabled++; } - DPRINTF("diu_mode = %d\n", hw->diu_mode); + debug("diu_mode = %d\n", hw->diu_mode); } static void disable_lcdc(void) { struct diu *hw = dr.diu_reg; - DPRINTF("Entered: disable_lcdc, fb_enabled = %d\n", fb_enabled); + debug("Entered: disable_lcdc, fb_enabled = %d\n", fb_enabled); if (fb_enabled) { hw->diu_mode = 0; fb_enabled = 0; @@ -453,7 +447,7 @@ static int allocate_buf(struct diu_addr *buf, u32 size, u32 bytes_align) u32 offset, ssize; u32 mask; - DPRINTF("Entered: allocate_buf\n"); + debug("Entered: allocate_buf\n"); ssize = size + bytes_align; buf->paddr = malloc(ssize); if (!buf->paddr) @@ -495,16 +489,16 @@ int fsl_diu_display_bmp(unsigned char *bmp, bitmap = bmp + raster; cpp = info->var.bits_per_pixel / 8; - DPRINTF("bmp = 0x%08x\n", (unsigned int)bmp); - DPRINTF("bitmap = 0x%08x\n", (unsigned int)bitmap); - DPRINTF("width = %d\n", width); - DPRINTF("height = %d\n", height); - DPRINTF("bpp = %d\n", bpp); - DPRINTF("ncolors = %d\n", ncolors); + debug("bmp = 0x%08x\n", (unsigned int)bmp); + debug("bitmap = 0x%08x\n", (unsigned int)bitmap); + debug("width = %d\n", width); + debug("height = %d\n", height); + debug("bpp = %d\n", bpp); + debug("ncolors = %d\n", ncolors); - DPRINTF("xres = %d\n", info->var.xres); - DPRINTF("yres = %d\n", info->var.yres); - DPRINTF("Screen_base = 0x%x\n", (unsigned int)info->screen_base); + debug("xres = %d\n", info->var.xres); + debug("yres = %d\n", info->var.yres); + debug("Screen_base = 0x%x\n", (unsigned int)info->screen_base); if (((width+xoffset) > info->var.xres) || ((height+yoffset) > info->var.yres)) { -- 1.5.2.2 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* [U-Boot-Users] [PATCH 3/3] Adding DIU support for Freescale 5121ADS 2008-05-05 15:20 ` [U-Boot-Users] [PATCH 2/3] Replace DPRINTF with debug York Sun @ 2008-05-05 15:20 ` York Sun 2008-05-09 20:10 ` Wolfgang Denk 0 siblings, 1 reply; 6+ messages in thread From: York Sun @ 2008-05-05 15:20 UTC (permalink / raw) To: u-boot Add DIU and cfb console support to FSL 5121ADS board. Use #define CONFIG_VIDEO in config file to enable fb console. Signed-off-by: York Sun <yorksun@freescale.com> --- board/ads5121/Makefile | 2 +- board/ads5121/ads5121.c | 62 ++++++++++++++++- board/ads5121/ads5121_diu.c | 165 +++++++++++++++++++++++++++++++++++++++++++ include/configs/ads5121.h | 53 +++++++++----- 4 files changed, 261 insertions(+), 21 deletions(-) create mode 100644 board/ads5121/ads5121_diu.c diff --git a/board/ads5121/Makefile b/board/ads5121/Makefile index b93bee1..8ace8a1 100644 --- a/board/ads5121/Makefile +++ b/board/ads5121/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS-y := $(BOARD).o +COBJS-y := $(BOARD).o ads5121_diu.o ../freescale/common/fsl_diu_fb.o ../freescale/common/fsl_logo_bmp.o COBJS-$(CONFIG_PCI) += pci.o COBJS := $(COBJS-y) diff --git a/board/ads5121/ads5121.c b/board/ads5121/ads5121.c index 8629b03..2892665 100644 --- a/board/ads5121/ads5121.c +++ b/board/ads5121/ads5121.c @@ -39,17 +39,35 @@ #define SCCR2_CLOCKS_EN (CLOCK_SCCR2_MEM_EN | \ CLOCK_SCCR2_SPDIF_EN | \ + CLOCK_SCCR2_DIU_EN | \ CLOCK_SCCR2_I2C_EN) #define CSAW_START(start) ((start) & 0xFFFF0000) #define CSAW_STOP(start, size) (((start) + (size) - 1) >> 16) +#define MPC5121_IOCTL_PSC6_0 (0x284/4) +#define MPC5121_IO_DIU_START (0x288/4) +#define MPC5121_IO_DIU_END (0x2fc/4) + +/* Functional pin muxing */ +#define MPC5121_IO_FUNC1 (0 << 7) +#define MPC5121_IO_FUNC2 (1 << 7) +#define MPC5121_IO_FUNC3 (2 << 7) +#define MPC5121_IO_FUNC4 (3 << 7) +#define MPC5121_IO_ST (1 << 2) +#define MPC5121_IO_DS_1 (0) +#define MPC5121_IO_DS_2 (1) +#define MPC5121_IO_DS_3 (2) +#define MPC5121_IO_DS_4 (3) + long int fixed_sdram(void); int board_early_init_f (void) { volatile immap_t *im = (immap_t *) CFG_IMMR; - u32 lpcaw; + u32 lpcaw, tmp32; + volatile ioctrl512x_t *ioctl = &(im->io_ctrl); + int i; /* * Initialize Local Window for the CPLD registers access (CS2 selects @@ -81,6 +99,16 @@ int board_early_init_f (void) im->clk.sccr[0] = SCCR1_CLOCKS_EN; im->clk.sccr[1] = SCCR2_CLOCKS_EN; + /* Configure DIU clock pin */ + tmp32 = ioctl->regs[MPC5121_IOCTL_PSC6_0]; + tmp32 &= ~0x1ff; + tmp32 |= MPC5121_IO_FUNC3 | MPC5121_IO_DS_4; + ioctl->regs[MPC5121_IOCTL_PSC6_0] = tmp32; + + /* Initialize IO pins (pin mux) for DIU function */ + for (i = MPC5121_IO_DIU_START; i < MPC5121_IO_DIU_END; i++) + ioctl->regs[i] |= (MPC5121_IO_FUNC3 | MPC5121_IO_DS_4); + return 0; } @@ -186,6 +214,38 @@ long int fixed_sdram (void) return msize; } +int misc_init_r(void) +{ + u8 tmp_val; + + /* Using this for DIU init before the driver in linux takes over + * Enable the TFP410 Encoder (I2C address 0x38) + */ + + i2c_set_bus_num(2); + tmp_val = 0xBF; + i2c_write(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val)); + /* Verify if enabled */ + tmp_val = 0; + i2c_read(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val)); + debug("DVI Encoder Read: 0x%02lx\n", tmp_val); + + tmp_val = 0x10; + i2c_write(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val)); + /* Verify if enabled */ + tmp_val = 0; + i2c_read(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val)); + debug("DVI Encoder Read: 0x%02lx\n", tmp_val); + +#ifdef CONFIG_FSL_DIU_FB +#if !(defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE)) + ads5121_diu_init(); +#endif +#endif + + return 0; +} + int checkboard (void) { ushort brd_rev = *(vu_short *) (CFG_CPLD_BASE + 0x00); diff --git a/board/ads5121/ads5121_diu.c b/board/ads5121/ads5121_diu.c new file mode 100644 index 0000000..87cf0cb --- /dev/null +++ b/board/ads5121/ads5121_diu.c @@ -0,0 +1,165 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * York Sun <yorksun@freescale.com> + * + * FSL DIU Framebuffer driver + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <command.h> +#include <asm/io.h> + +#ifdef CONFIG_FSL_DIU_FB + +#include "../freescale/common/pixis.h" +#include "../freescale/common/fsl_diu_fb.h" + +#if defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE) +#include <devices.h> +#include <video_fb.h> +#endif + +extern unsigned int FSL_Logo_BMP[]; + +static int xres, yres; + +void diu_set_pixel_clock(unsigned int pixclock) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile clk512x_t *clk = &immap->clk; + volatile unsigned int *clkdvdr = &clk->scfr[0]; + unsigned long speed_ccb, temp, pixval; + + speed_ccb = get_bus_freq(0) * 4; + temp = 1000000000/pixclock; + temp *= 1000; + pixval = speed_ccb / temp; + debug("DIU pixval = %lu\n", pixval); + + /* Modify PXCLK in GUTS CLKDVDR */ + debug("DIU: Current value of CLKDVDR = 0x%08x\n", *clkdvdr); + temp = *clkdvdr & 0xFFFFFF00; + *clkdvdr = temp | (pixval & 0x1F); + debug("DIU: Modified value of CLKDVDR = 0x%08x\n", *clkdvdr); +} + +int ads5121_diu_init(void) +{ + unsigned int pixel_format; + + xres = 1024; + yres = 768; + pixel_format = 0x88883316; + + return fsl_diu_init(xres, pixel_format, 0, + (unsigned char *)FSL_Logo_BMP); +} + +int ads5121diu_init_show_bmp(cmd_tbl_t *cmdtp, + int flag, int argc, char *argv[]) +{ + unsigned int addr; + + if (argc < 2) { + printf("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + if (!strncmp(argv[1], "init", 4)) { +#if defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE) + fsl_diu_clear_screen(); + drv_video_init(); +#else + return ads5121_diu_init(); +#endif + } else { + addr = simple_strtoul(argv[1], NULL, 16); + fsl_diu_clear_screen(); + fsl_diu_display_bmp((unsigned char *)addr, 0, 0, 0); + } + + return 0; +} + +U_BOOT_CMD( + diufb, CFG_MAXARGS, 1, ads5121diu_init_show_bmp, + "diufb init | addr - Init or Display BMP file\n", + "init\n - initialize DIU\n" + "addr\n - display bmp at address 'addr'\n" + ); + + +#if defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE) + +/* + * The Graphic Device + */ +GraphicDevice ctfb; +void *video_hw_init(void) +{ + GraphicDevice *pGD = (GraphicDevice *) &ctfb; + struct fb_info *info; + + if (ads5121_diu_init() < 0) + return; + + /* fill in Graphic device struct */ + sprintf(pGD->modeIdent, "%dx%dx%d %ldkHz %ldHz", + xres, yres, 32, 64, 60); + + pGD->frameAdrs = (unsigned int)fsl_fb_open(&info); + pGD->winSizeX = xres; + pGD->winSizeY = yres - info->logo_height; + pGD->plnSizeX = pGD->winSizeX; + pGD->plnSizeY = pGD->winSizeY; + + pGD->gdfBytesPP = 4; + pGD->gdfIndex = GDF_32BIT_X888RGB; + + pGD->isaBase = 0; + pGD->pciBase = 0; + pGD->memSize = info->screen_size - info->logo_size; + + /* Cursor Start Address */ + pGD->dprBase = 0; + pGD->vprBase = 0; + pGD->cprBase = 0; + + return (void *)pGD; +} + +/** + * Set the LUT + * + * @index: color number + * @r: red + * @b: blue + * @g: green + */ +void video_set_lut + (unsigned int index, unsigned char r, unsigned char g, unsigned char b) +{ + return; +} + +#endif /* defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE) */ + +#endif /* CONFIG_FSL_DIU_FB */ diff --git a/include/configs/ads5121.h b/include/configs/ads5121.h index 81e7c1e..fb062f1 100644 --- a/include/configs/ads5121.h +++ b/include/configs/ads5121.h @@ -45,14 +45,25 @@ */ #define CONFIG_E300 1 /* E300 Family */ #define CONFIG_MPC512X 1 /* MPC512X family */ +#define CONFIG_FSL_DIU_FB 1 /* FSL DIU */ + +/* video */ +#undef CONFIG_VIDEO + +#if defined(CONFIG_VIDEO) +#define CONFIG_CFB_CONSOLE +#define CONFIG_VGA_AS_SINGLE_DEVICE +#endif /* CONFIG_PCI is defined at config time */ #define CFG_MPC512X_CLKIN 66000000 /* in Hz */ #define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f() */ +#define CONFIG_MISC_INIT_R #define CFG_IMMR 0x80000000 +#define CFG_DIU_ADDR (CFG_IMMR+0x2100) #define CFG_MEMTEST_START 0x00200000 /* memtest region */ #define CFG_MEMTEST_END 0x00400000 @@ -127,28 +138,28 @@ #define CFG_MICRON_OCD_DEFAULT 0x01010780 /* DDR Priority Manager Configuration */ -#define CFG_MDDRCGRP_PM_CFG1 0x000777AA -#define CFG_MDDRCGRP_PM_CFG2 0x00000055 -#define CFG_MDDRCGRP_HIPRIO_CFG 0x00000000 -#define CFG_MDDRCGRP_LUT0_MU 0x11111117 -#define CFG_MDDRCGRP_LUT0_ML 0x7777777A -#define CFG_MDDRCGRP_LUT1_MU 0x4444EEEE -#define CFG_MDDRCGRP_LUT1_ML 0xEEEEEEEE -#define CFG_MDDRCGRP_LUT2_MU 0x44444444 +#define CFG_MDDRCGRP_PM_CFG1 0x00077777 +#define CFG_MDDRCGRP_PM_CFG2 0x00000000 +#define CFG_MDDRCGRP_HIPRIO_CFG 0x00000001 +#define CFG_MDDRCGRP_LUT0_MU 0xFFEEDDCC +#define CFG_MDDRCGRP_LUT0_ML 0xBBAAAAAA +#define CFG_MDDRCGRP_LUT1_MU 0x66666666 +#define CFG_MDDRCGRP_LUT1_ML 0x55555555 +#define CFG_MDDRCGRP_LUT2_MU 0x44444444 #define CFG_MDDRCGRP_LUT2_ML 0x44444444 -#define CFG_MDDRCGRP_LUT3_MU 0x55555555 +#define CFG_MDDRCGRP_LUT3_MU 0x55555555 #define CFG_MDDRCGRP_LUT3_ML 0x55555558 -#define CFG_MDDRCGRP_LUT4_MU 0x11111111 -#define CFG_MDDRCGRP_LUT4_ML 0x1111117C -#define CFG_MDDRCGRP_LUT0_AU 0x33333377 -#define CFG_MDDRCGRP_LUT0_AL 0x7777EEEE -#define CFG_MDDRCGRP_LUT1_AU 0x11111111 -#define CFG_MDDRCGRP_LUT1_AL 0x11111111 -#define CFG_MDDRCGRP_LUT2_AU 0x11111111 +#define CFG_MDDRCGRP_LUT4_MU 0x11111111 +#define CFG_MDDRCGRP_LUT4_ML 0x11111122 +#define CFG_MDDRCGRP_LUT0_AU 0xaaaaaaaa +#define CFG_MDDRCGRP_LUT0_AL 0xaaaaaaaa +#define CFG_MDDRCGRP_LUT1_AU 0x66666666 +#define CFG_MDDRCGRP_LUT1_AL 0x66666666 +#define CFG_MDDRCGRP_LUT2_AU 0x11111111 #define CFG_MDDRCGRP_LUT2_AL 0x11111111 -#define CFG_MDDRCGRP_LUT3_AU 0x11111111 +#define CFG_MDDRCGRP_LUT3_AU 0x11111111 #define CFG_MDDRCGRP_LUT3_AL 0x11111111 -#define CFG_MDDRCGRP_LUT4_AU 0x11111111 +#define CFG_MDDRCGRP_LUT4_AU 0x11111111 #define CFG_MDDRCGRP_LUT4_AL 0x11111111 /* @@ -189,7 +200,11 @@ #define CFG_MONITOR_BASE TEXT_BASE /* Start of monitor */ #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CFG_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ +#ifdef CONFIG_FSL_DIU_FB +#define CFG_MALLOC_LEN (6 * 1024 * 1024) /* Reserved for malloc */ +#else +#define CFG_MALLOC_LEN (512 * 1024) +#endif /* * Serial Port -- 1.5.2.2 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* [U-Boot-Users] [PATCH 3/3] Adding DIU support for Freescale 5121ADS 2008-05-05 15:20 ` [U-Boot-Users] [PATCH 3/3] Adding DIU support for Freescale 5121ADS York Sun @ 2008-05-09 20:10 ` Wolfgang Denk 0 siblings, 0 replies; 6+ messages in thread From: Wolfgang Denk @ 2008-05-09 20:10 UTC (permalink / raw) To: u-boot In message <1210000803219-git-send-email-yorksun@freescale.com> you wrote: > Add DIU and cfb console support to FSL 5121ADS board. > > Use #define CONFIG_VIDEO in config file to enable fb console. > > Signed-off-by: York Sun <yorksun@freescale.com> > --- > board/ads5121/Makefile | 2 +- > board/ads5121/ads5121.c | 62 ++++++++++++++++- > board/ads5121/ads5121_diu.c | 165 +++++++++++++++++++++++++++++++++++++++++++ > include/configs/ads5121.h | 53 +++++++++----- > 4 files changed, 261 insertions(+), 21 deletions(-) > create mode 100644 board/ads5121/ads5121_diu.c > > diff --git a/board/ads5121/Makefile b/board/ads5121/Makefile > index b93bee1..8ace8a1 100644 > --- a/board/ads5121/Makefile > +++ b/board/ads5121/Makefile > @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk > > LIB = $(obj)lib$(BOARD).a > > -COBJS-y := $(BOARD).o > +COBJS-y := $(BOARD).o ads5121_diu.o ../freescale/common/fsl_diu_fb.o ../freescale/common/fsl_logo_bmp.o This line is way too long, and it doesn't work with out-of-tree builds. Try something like: make O=/tmp/ads5121 ads5121_config make O=/tmp/ads5121 all and you will get: make[1]: Entering directory `/home/wd/git/u-boot/testing/board/ads5121' ppc_6xx-gcc -g -Os -fPIC -ffixed-r14 -meabi -D__KERNEL__ -DTEXT_BASE=0xFFF00000 -I/tmp/ads5121/include2 -I/tmp/ads5121/include -I/home/wd/git/u-boot/testing/include -fno-builtin -ffreestanding -nostdinc -isystem /opt/eldk-4.2-2008-03-27/usr/bin/../lib/gcc/powerpc-linux/4.2.2/include -pipe -DCONFIG_PPC -D__powerpc__ -DCONFIG_MPC512X -DCONFIG_E300 -ffixed-r2 -msoft-float -mcpu=603e -Wall -Wstrict-prototypes -c -o /tmp/ads5121/board/ads5121/ads5121.o ads5121.c ads5121.c: In function 'misc_init_r': ads5121.c:225: warning: implicit declaration of function 'i2c_set_bus_num' ads5121.c:227: warning: implicit declaration of function 'i2c_write' ads5121.c:230: warning: implicit declaration of function 'i2c_read' ppc_6xx-gcc -g -Os -fPIC -ffixed-r14 -meabi -D__KERNEL__ -DTEXT_BASE=0xFFF00000 -I/tmp/ads5121/include2 -I/tmp/ads5121/include -I/home/wd/git/u-boot/testing/include -fno-builtin -ffreestanding -nostdinc -isystem /opt/eldk-4.2-2008-03-27/usr/bin/../lib/gcc/powerpc-linux/4.2.2/include -pipe -DCONFIG_PPC -D__powerpc__ -DCONFIG_MPC512X -DCONFIG_E300 -ffixed-r2 -msoft-float -mcpu=603e -Wall -Wstrict-prototypes -c -o /tmp/ads5121/board/ads5121/ads5121_diu.o ads5121_diu.c ads5121_diu.c: In function 'video_hw_init': ads5121_diu.c:122: warning: 'return' with no value, in function returning non-void ppc_6xx-gcc -g -Os -fPIC -ffixed-r14 -meabi -D__KERNEL__ -DTEXT_BASE=0xFFF00000 -I/tmp/ads5121/include2 -I/tmp/ads5121/include -I/home/wd/git/u-boot/testing/include -fno-builtin -ffreestanding -nostdinc -isystem /opt/eldk-4.2-2008-03-27/usr/bin/../lib/gcc/powerpc-linux/4.2.2/include -pipe -DCONFIG_PPC -D__powerpc__ -DCONFIG_MPC512X -DCONFIG_E300 -ffixed-r2 -msoft-float -mcpu=603e -Wall -Wstrict-prototypes -c -o /tmp/ads5121/board/ads5121/../freescale/common/fsl_diu_fb.o ../freescale/common/fsl_diu_fb.c Assembler messages: Fatal error: can't create /tmp/ads5121/board/ads5121/../freescale/common/fsl_diu_fb.o: No such file or directory make[1]: *** [/tmp/ads5121/board/ads5121/../freescale/common/fsl_diu_fb.o] Error 2 make[1]: Leaving directory `/home/wd/git/u-boot/testing/board/ads5121' make: *** [/tmp/ads5121/board/ads5121/libads5121.a] Error 2 Please also fix the warnings, when you are at it... Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de "I think trash is the most important manifestation of culture we have in my lifetime." - Johnny Legend ^ permalink raw reply [flat|nested] 6+ messages in thread
* [U-Boot-Users] Adding DIU support for FSL MPC5121ADS board 2008-05-05 15:19 [U-Boot-Users] Adding DIU support for FSL MPC5121ADS board York Sun 2008-05-05 15:19 ` [U-Boot-Users] [PATCH 1/3 v2] Move pixel clock setting to board file York Sun @ 2008-05-09 20:10 ` Wolfgang Denk 1 sibling, 0 replies; 6+ messages in thread From: Wolfgang Denk @ 2008-05-09 20:10 UTC (permalink / raw) To: u-boot Dear York, in message <12100008011000-git-send-email-yorksun@freescale.com> you wrote: > > Please review the following patchset. It adds DIU support to > 5121ADS board, using the existing DIU driver. I really appreciate these patches. With a little cleanup they will go into the next release. There is just a Makefile issue with patch #3 (breaks out-of-tree builds, see next message). It will be sufficient to submit an incremental patch, though. Note: I added the code (as is) to the "ads5121" branch of the u-boot-testing repository, see http://git.denx.de/?p=u-boot/u-boot-testing.git;a=shortlog;h=refs/heads/ads5121 Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de On my planet, to rest is to rest -- to cease using energy. To me, it is quite illogical to run up and down on green grass, using energy, instead of saving it. -- Spock, "Shore Leave", stardate 3025.2 ^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2008-05-09 20:10 UTC | newest] Thread overview: 6+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2008-05-05 15:19 [U-Boot-Users] Adding DIU support for FSL MPC5121ADS board York Sun 2008-05-05 15:19 ` [U-Boot-Users] [PATCH 1/3 v2] Move pixel clock setting to board file York Sun 2008-05-05 15:20 ` [U-Boot-Users] [PATCH 2/3] Replace DPRINTF with debug York Sun 2008-05-05 15:20 ` [U-Boot-Users] [PATCH 3/3] Adding DIU support for Freescale 5121ADS York Sun 2008-05-09 20:10 ` Wolfgang Denk 2008-05-09 20:10 ` [U-Boot-Users] Adding DIU support for FSL MPC5121ADS board Wolfgang Denk
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