[U-Boot-Users] [PATCH 5/8] ppc4xx: Fix common ECC generation code for 440GP style platforms

Stefan Roese
2008-06-02T19:02:33Z

This patch makes the common 4xx ECC code really usable on 440GP style
platforms.

Since the IBM DDR controller used on 440GP/GX/EP/GR is not register
compatible to the IBM DDR/2 controller used on 405EX/440SP/SPe/460EX/GT
we need to make some processor dependant defines used later on by the
driver.

Signed-off-by: Stefan Roese <sr@denx.de>
---
cpu/ppc4xx/ecc.c | 14 +++++++-------
cpu/ppc4xx/ecc.h | 27 +++++++++++++++++++++++++++
2 files changed, 34 insertions(+), 7 deletions(-)

diff --git a/cpu/ppc4xx/ecc.c b/cpu/ppc4xx/ecc.c
index 95b941d..3e87c84 100644
--- a/cpu/ppc4xx/ecc.c
+++ b/cpu/ppc4xx/ecc.c
@@ -76,7 +76,7 @@
void ecc_init(unsigned long * const start, unsigned long size)
{
const unsigned long pattern = CFG_ECC_PATTERN;
- unsigned * const end = (unsigned long * const)((long)start + size);
+ unsigned long * const end = (unsigned long * const)((long)start + size);
unsigned long * current = start;
unsigned long mcopt1;
long increment;
@@ -84,12 +84,12 @@ void ecc_init(unsigned long * const start, unsigned long size)
if (start >= end)
return;

- mfsdram(SDRAM_MCOPT1, mcopt1);
+ mfsdram(SDRAM_ECC_CFG, mcopt1);

/* Enable ECC generation without checking or reporting */

- mtsdram(SDRAM_MCOPT1, ((mcopt1 & ~SDRAM_MCOPT1_MCHK_MASK) |
- SDRAM_MCOPT1_MCHK_GEN));
+ mtsdram(SDRAM_ECC_CFG, ((mcopt1 & ~SDRAM_ECC_CFG_MCHK_MASK) |
+ SDRAM_ECC_CFG_MCHK_GEN));

increment = sizeof(u32);

@@ -99,7 +99,7 @@ void ecc_init(unsigned long * const start, unsigned long size)
* can skip words when writing.
*/

- if ((mcopt1 & SDRAM_MCOPT1_DMWD_MASK) != SDRAM_MCOPT1_DMWD_32)
+ if ((mcopt1 & SDRAM_ECC_CFG_DMWD_MASK) != SDRAM_ECC_CFG_DMWD_32)
increment = sizeof(u64);
#endif /* defined(CONFIG_440) */

@@ -114,8 +114,8 @@ void ecc_init(unsigned long * const start, unsigned long size)

/* Enable ECC generation with checking and no reporting */

- mtsdram(SDRAM_MCOPT1, ((mcopt1 & ~SDRAM_MCOPT1_MCHK_MASK) |
- SDRAM_MCOPT1_MCHK_CHK));
+ mtsdram(SDRAM_ECC_CFG, ((mcopt1 & ~SDRAM_ECC_CFG_MCHK_MASK) |
+ SDRAM_ECC_CFG_MCHK_CHK));
}
#endif /* defined(CONFIG_DDR_ECC) || defined(CONFIG_SDRAM_ECC) */
#endif /* !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) */
diff --git a/cpu/ppc4xx/ecc.h b/cpu/ppc4xx/ecc.h
index da1c4fd..aecf291 100644
--- a/cpu/ppc4xx/ecc.h
+++ b/cpu/ppc4xx/ecc.h
@@ -37,6 +37,33 @@
#define CFG_ECC_PATTERN 0x00000000
#endif /* !defined(CFG_ECC_PATTERN) */

+/*
+ * Since the IBM DDR controller used on 440GP/GX/EP/GR is not register
+ * compatible to the IBM DDR/2 controller used on 405EX/440SP/SPe/460EX/GT
+ * we need to make some processor dependant defines used later on by the
+ * driver.
+ */
+
+/* For 440GP/GX/EP/GR */
+#if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR)
+#define SDRAM_ECC_CFG SDRAM_CFG0
+#define SDRAM_ECC_CFG_MCHK_MASK SDRAM_CFG0_MCHK_MASK
+#define SDRAM_ECC_CFG_MCHK_GEN SDRAM_CFG0_MCHK_GEN
+#define SDRAM_ECC_CFG_MCHK_CHK SDRAM_CFG0_MCHK_CHK
+#define SDRAM_ECC_CFG_DMWD_MASK SDRAM_CFG0_DMWD_MASK
+#define SDRAM_ECC_CFG_DMWD_32 SDRAM_CFG0_DMWD_32
+#endif
+
+/* For 405EX/440SP/SPe/460EX/GT */
+#if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR2)
+#define SDRAM_ECC_CFG SDRAM_MCOPT1
+#define SDRAM_ECC_CFG_MCHK_MASK SDRAM_MCOPT1_MCHK_MASK
+#define SDRAM_ECC_CFG_MCHK_GEN SDRAM_MCOPT1_MCHK_GEN
+#define SDRAM_ECC_CFG_MCHK_CHK SDRAM_MCOPT1_MCHK_CHK
+#define SDRAM_ECC_CFG_DMWD_MASK SDRAM_MCOPT1_DMWD_MASK
+#define SDRAM_ECC_CFG_DMWD_32 SDRAM_MCOPT1_DMWD_32
+#endif
+
extern void ecc_init(unsigned long * const start, unsigned long size);

#endif /* _ECC_H_ */
--
1.5.5.3