[U-Boot] [PATCH v5 00/10] FSL DDR rework

[Kumar Gala <galak@kernel.crashing.org>]

01 - Add proper SPD definitions for DDR1/2/3
02 - FSL DDR: Provide a generic set_ddr_laws()
03 - FSL DDR: Rewrite the FSL mpc8xxx DDR controller setup code.
04 - FSL DDR: Add DDR1 DIMM paramter support
05 - FSL DDR: Add DDR2 DIMM paramter support
06 - FSL DDR: Add 86xx specific register setting
07 - FSL DDR: Convert MPC8641HPCN to new DDR code.
08 - FSL DDR: Convert MPC8610HPCD to new DDR code.
09 - FSL DDR: Convert SBC8641D to new DDR code.
10 - FSL DDR: Remove old SPD support from cpu/mpc86xx

This is the latest spin of the DDR work and hopefully address some of the
comments we discussioned on IRC.

I've converted ALL 86xx platforms and if these patches are acceptable I'll
go ahead and do the 85xx platforms as a followup.

I've dropped the interactive change at this point.

Patches 03..05 are the core of the DDR support.  These patches are split
up so they can be 

Here is some size data for building the MPC8641HPCN_config:

   text	   data	    bss	    dec	    hex	filename
 315244	  29044	  98960	 443248	  6c370	u-boot (baseline)
 320356	  29096	  98960	 448412	  6d79c	u-boot (w/o DDR changes)
------------------------------------------------
   5122      52            5164         delta

I think an increase of 5k is worth is for the improvements we get.

- k