[U-Boot] [PATCH v3] Support for multiple SGMII/TBI interfaces for TSEC ethernet

[Peter Tyser <ptyser@xes-inc.com>]

On Mon, 2008-09-15 at 16:13 -0500, Andy Fleming wrote:
> > @@ -299,12 +301,10 @@ static int init_phy(struct eth_device *dev)
> >  {
> >        struct tsec_private *priv = (struct tsec_private *)dev->priv;
> >        struct phy_info *curphy;
> > -       volatile tsec_t *phyregs = priv->phyregs;
> >        volatile tsec_t *regs = priv->regs;
> >
> >        /* Assign a Physical address to the TBI */
> >        regs->tbipa = CFG_TBIPA_VALUE;
> > -       phyregs->tbipa = CFG_TBIPA_VALUE;
> >        asm("sync");
> 
> 
> What was the purpose of doing this?  The problem I have with it is in
> the odd situation where the TSEC whose MII regs are connected to the
> bus is not enabled.  It would mean that the TBIPA would never be set
> to CFG_TBIPA_VALUE.

I don't quite understand what you mean.  My understanding was that if a
TSEC is not enabled, the TBIPA for that TSEC should not be enabled
either.

The original code was writing the TBIPA value 2 times for every TSEC -
once at the TSEC register address in cpu space, and a second time at the
TSEC's MII register address in cpu space.

For example, if a board had 4 sgmii interfaces with 4 external PHYs on
an mpc8572 - all 4 PHYs could be physically connected to the MDIO bus of
TSEC1.  The cpu address offsets of the 4 TSECs would be:
TSEC1 regs    = 0x24000
TSEC1 phyregs = 0x24000
TSEC2 regs    = 0x25000
TSEC2 phyregs = 0x24000
TSEC3 regs    = 0x26000
TSEC3 phyregs = 0x24000
TSEC4 regs    = 0x27000
TSEC4 phyregs = 0x24000

With the old code, on bootup the ethernet initialization would go like:

configure TSEC1 - write TSEC1's TBIPA address, write TSEC1's TBIPA
address (2nd write to TSEC1 TBIPA)

configure TSEC2 - write TSEC2's TBIPA address, write TSEC1's TBIPA
address (3rd time)

configure TSEC3 - write TSEC3's TBIPA address, write TSEC1's TBIPA
address (4th time)

configure TSEC4 - write TSEC4's TBIPA address, write TSEC1's TBIPA
address (5th time)

So the old code would write TSEC1's TBIPA address 5 times.

The patch I submitted does the following:
configure TSEC1 - write TSEC1's TBIPA address

configure TSEC2 - write TSEC2's TBIPA address

configure TSEC3 - write TSEC3's TBIPA address

configure TSEC4 - write TSEC4's TBIPA address

This 2nd method seems correct to me - each TSECs TBIPA address should
only be set for itself, not itself as well as the TSEC its using to
access its external PHY.

Best,
Peter