[U-Boot] [PATCH 1/2] Change DDR tlb start entry to CONFIG param for 85xx

[U-Boot] [PATCH 1/2] Change DDR tlb start entry to CONFIG param for 85xx

[Haiying Wang]

So that we can locate the DDR tlb start entry to the value other than 8. By
default, it is still 8.

Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
---
 cpu/mpc85xx/tlb.c |    6 +++++-
 1 files changed, 5 insertions(+), 1 deletions(-)

diff --git a/cpu/mpc85xx/tlb.c b/cpu/mpc85xx/tlb.c
index a2d16ae..32a7f5c 100644
--- a/cpu/mpc85xx/tlb.c
+++ b/cpu/mpc85xx/tlb.c
@@ -91,6 +91,10 @@ void init_tlbs(void)
 	return ;
 }
 
+#ifndef CONFIG_SYS_DDR_TLB_START
+#define CONFIG_SYS_DDR_TLB_START 8
+#endif
+
 unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg)
 {
 	unsigned int tlb_size;
@@ -137,7 +141,7 @@ unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg)
 	 * Configure DDR TLB1 entries.
 	 * Starting at TLB1 8, use no more than 8 TLB1 entries.
 	 */
-	ram_tlb_index = 8;
+	ram_tlb_index = CONFIG_SYS_DDR_TLB_START;
 	ram_tlb_address = (unsigned int)CONFIG_SYS_DDR_SDRAM_BASE;
 	while (ram_tlb_address < (memsize_in_meg * 1024 * 1024)
 	      && ram_tlb_index < 16) {
-- 
1.6.0.2

[U-Boot] [PATCH 1/2] Change DDR tlb start entry to CONFIG param for85xx

[Liu Dave]

> +#ifndef CONFIG_SYS_DDR_TLB_START
> +#define CONFIG_SYS_DDR_TLB_START 8
> +#endif
> +
>  unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg)
>  {
>  	unsigned int tlb_size;
> @@ -137,7 +141,7 @@ unsigned int setup_ddr_tlbs(unsigned int 
> memsize_in_meg)
>  	 * Configure DDR TLB1 entries.
>  	 * Starting at TLB1 8, use no more than 8 TLB1 entries.
>  	 */
> -	ram_tlb_index = 8;
> +	ram_tlb_index = CONFIG_SYS_DDR_TLB_START;
>  	ram_tlb_address = (unsigned int)CONFIG_SYS_DDR_SDRAM_BASE;
>  	while (ram_tlb_address < (memsize_in_meg * 1024 * 1024)
>  	      && ram_tlb_index < 16) {

Kumar,

is it possible to change TLB alloc way?
current u-boot TLB is easy to conflict/confus to users.
there are two limitations
1) the magic number 8 for DDR
2) the TLB14/TLB15 never can be used to board code.

These are TLBs that board code can use just like
0,1....7,skip DDR(8....), skip 14 and 15.

Basically it is limited to 0-7.

[U-Boot] [PATCH 1/2] Change DDR tlb start entry to CONFIG param for85xx

[Kumar Gala]

On Jan 13, 2009, at 7:08 PM, Liu Dave wrote:

>> +#ifndef CONFIG_SYS_DDR_TLB_START
>> +#define CONFIG_SYS_DDR_TLB_START 8
>> +#endif
>> +
>> unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg)
>> {
>> 	unsigned int tlb_size;
>> @@ -137,7 +141,7 @@ unsigned int setup_ddr_tlbs(unsigned int
>> memsize_in_meg)
>> 	 * Configure DDR TLB1 entries.
>> 	 * Starting at TLB1 8, use no more than 8 TLB1 entries.
>> 	 */
>> -	ram_tlb_index = 8;
>> +	ram_tlb_index = CONFIG_SYS_DDR_TLB_START;
>> 	ram_tlb_address = (unsigned int)CONFIG_SYS_DDR_SDRAM_BASE;
>> 	while (ram_tlb_address < (memsize_in_meg * 1024 * 1024)
>> 	      && ram_tlb_index < 16) {
>
> Kumar,
>
> is it possible to change TLB alloc way?
> current u-boot TLB is easy to conflict/confus to users.
> there are two limitations
> 1) the magic number 8 for DDR
> 2) the TLB14/TLB15 never can be used to board code.
>
> These are TLBs that board code can use just like
> 0,1....7,skip DDR(8....), skip 14 and 15.
>
> Basically it is limited to 0-7.

I'm not sure what you are asking about.  I agree we have some  
limitations but for the vast majority of boards 8 entries has been  
enough.

I'm all for any patches that try and make the allocation a bit more  
dynamic.  We can do something similar to the LAW code if someone wants  
to work up patches.

- k

[U-Boot] [PATCH 1/2] Change DDR tlb start entry to CONFIG param for85xx

[Liu Dave]

> I'm not sure what you are asking about.  I agree we have some  
> limitations but for the vast majority of boards 8 entries has been  
> enough.

It is not real case. If the MP enable, only 7 entries the board can use.

> I'm all for any patches that try and make the allocation a bit more  
> dynamic.  We can do something similar to the LAW code if 
> someone wants to work up patches.

Yes, it is exactly our needs. I expect it is dynamic and transparent to
user.
If TLB alloc is transparent, the users don't have to know the TLB14/15
and
TLB8... is occupied by early code.