From mboxrd@z Thu Jan 1 00:00:00 1970 From: Peter Tyser Date: Wed, 04 Feb 2009 14:22:52 -0600 Subject: [U-Boot] [PATCH] nand_base: Add timeout for NAND reset command In-Reply-To: <4989F25A.6090400@freescale.com> References: <1233776842-23379-1-git-send-email-ptyser@xes-inc.com> <4989F25A.6090400@freescale.com> Message-ID: <1233778972.7067.261.camel@localhost.localdomain> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On Wed, 2009-02-04 at 13:54 -0600, Scott Wood wrote: > Peter Tyser wrote: > > +/* > > + * CONFIG_SYS_NAND_RESET_CNT is used as a timeout mechanism when resetting > > + * a flash. NAND flash is initialized prior to interrupts so standard timers > > + * can't be used. CONFIG_SYS_NAND_RESET_CNT should be set to a value > > + * which is greater than (max NAND reset time / NAND status read time). > > + * A conservative default of 200000 (500 us / 25 ns) is used as a default. > > + */ > > +#ifndef CONFIG_SYS_NAND_RESET_CNT > > +#define CONFIG_SYS_NAND_RESET_CNT 200000 > > +#endif > > Where does 25 ns come from? Should the timeout be in terms of real time > rather than iterations (we use get_ticks() for this purpose in > fsl_elbc_nand.c)? The 25ns was calculated based on the addition of trp and trhoh from the Micron MT29F8G08 datasheet. Based on the timing diagram for a "Read Status" cycle I thought this would be the minimum cycle time needed to read the chip's status. Other chips (ST, Samsung) I glanced at had > 25 ns read status times as well. I had tried using get_timer() (I believe nand_wait() would have been perfect to use), but that didn't work due to interrupts being disabled when NAND is probed. I didn't consider using get_ticks()... That seems much better. Is get_ticks() available for all platforms when NAND is initialized? Assuming get_ticks() is available for all platforms, would you prefer I: 1. re-do the patch using get_ticks() 2. update nand_wait() to use get_ticks instead of get_timer() and use it Thanks, Peter