[U-Boot] [PATCH 3/3][v2] qong: support for Dave/DENX QongEVB-LITE board

Jean-Christophe PLAGNIOL-VILLARD
2009-02-05T21:17:48Z

On 06:32 Thu 05 Feb , Ilya Yanok wrote:
> This patch adds support for Dave/DENX QongEVB-LITE i.MX31-based board.
>
> Signed-off-by: Ilya Yanok <yanok@emcraft.com>
> ---
MAITAINER and MAKEALL?
> Makefile | 4 +
> board/davedenx/qong/Makefile | 53 +++++++++
> board/davedenx/qong/config.mk | 1 +
> board/davedenx/qong/lowlevel_init.S | 172 ++++++++++++++++++++++++++++
> board/davedenx/qong/qong.c | 167 +++++++++++++++++++++++++++
> board/davedenx/qong/qong_fpga.h | 41 +++++++
> board/davedenx/qong/u-boot.lds | 58 ++++++++++
> include/configs/qong.h | 215 +++++++++++++++++++++++++++++++++++
> 8 files changed, 711 insertions(+), 0 deletions(-)
> create mode 100644 board/davedenx/qong/Makefile
> create mode 100644 board/davedenx/qong/config.mk
> create mode 100644 board/davedenx/qong/lowlevel_init.S
> create mode 100644 board/davedenx/qong/qong.c
> create mode 100644 board/davedenx/qong/qong_fpga.h
> create mode 100644 board/davedenx/qong/u-boot.lds
> create mode 100644 include/configs/qong.h
>
> diff --git a/Makefile b/Makefile
> index 787c5f2..7508e1d 100644
> --- a/Makefile
> +++ b/Makefile
> @@ -3034,6 +3034,10 @@ mx31ads_config : unconfig
> omap2420h4_config : unconfig
> @$(MKCONFIG) $(@:_config=) arm arm1136 omap2420h4 NULL omap24xx
>
> +qong_config : unconfig
> + @$(MKCONFIG) $(@:_config=) arm arm1136 qong davedenx mx31
> +
> +
> #########################################################################
> ## ARM1176 Systems
> #########################################################################
> new file mode 100644
> index 0000000..ae653ab
> --- /dev/null
> +++ b/board/davedenx/qong/lowlevel_init.S
> @@ -0,0 +1,172 @@
> +/*
> + * Copyright (C) 2009, Emcraft Systems, Ilya Yanok <yanok@emcraft.com>
> + *
> + * Based on board/freescale/mx31ads/lowlevel_init.S
> + * by Guennadi Liakhovetski.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#include <asm/arch/mx31-regs.h>
> +
> +.macro REG reg, val
> + ldr r2, =\reg
> + ldr r3, =\val
> + str r3, [r2]
> +.endm
> +
> +.macro REG8 reg, val
> + ldr r2, =\reg
> + ldr r3, =\val
> + strb r3, [r2]
> +.endm
we have these macro in a lots of place maybe we can create a common hearder as
we do for SH?
> +
> +.macro DELAY loops
> + ldr r2, =\loops
> +1:
> + subs r2, r2, #1
> + nop
> + bcs 1b
> +.endm
> +
> +/* RedBoot: To support 133MHz DDR */
> +.macro init_drive_strength
> + /*
> + * Disable maximum drive strength SDRAM/DDR lines by clearing DSE1 bits
> + * in SW_PAD_CTL registers
> + */
> +
> + /* SDCLK */
> + ldr r1, =0x43FAC200
hardcoded value?
> + ldr r0, [r1, #0x6C]
> + bic r0, r0, #(1 << 12)
> + str r0, [r1, #0x6C]
> +
> + /* CAS */
> + ldr r0, [r1, #0x70]
> + bic r0, r0, #(1 << 22)
> + str r0, [r1, #0x70]
> +
> + /* RAS */
> + ldr r0, [r1, #0x74]
> + bic r0, r0, #(1 << 2)
> + str r0, [r1, #0x74]
> +
> + /* CS2 (CSD0) */
> + ldr r0, [r1, #0x7C]
> + bic r0, r0, #(1 << 22)
> + str r0, [r1, #0x7C]
> +
> + /* DQM3 */
> + ldr r0, [r1, #0x84]
> + bic r0, r0, #(1 << 22)
> + str r0, [r1, #0x84]
> +
> + /* DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC) */
> + ldr r2, =22 /* (0x2E0 - 0x288) / 4 = 22 */
> + str r1, [r0, #0x1c]
> +
> + /* Default: 1, 4, 12, 1 */
> + REG CCM_SPCTL, PLL_PD(1) | PLL_MFD(4) | PLL_MFI(12) | PLL_MFN(1)
> +
> + /* B8xxxxxx - NAND, 8xxxxxxx - CSD0 RAM */
> + REG 0xB8001010, 0x00000004
> + REG 0xB8001004, ((3<<21) | /* tXP */ \
please add space before and after '<<'
> + (0<<20) | /* tWTR */ \
> + (2<<18) | /* tRP */ \
> + (1<<16) | /* tMRD */ \
> + (0<<15) | /* tWR */ \
> + (5<<12) | /* tRAS */ \
> + (1<<10) | /* tRRD */ \
> + (3<<8) | /* tCAS */ \
> + (2<<4) | /* tRCD */ \
> + (7<<0) /* tRC */ )
+
> +#ifdef CONFIG_QONG_FPGA
> + /* CS1: FPGA/Network Controller/GPIO */
> + /* 16-bit, no DTACK */
> + __REG(CSCR_U(1)) = 0x00000A01;
> + __REG(CSCR_L(1)) = 0x20040501;
> + __REG(CSCR_A(1)) = 0x04020C00;
> +
> + /* setup pins for FPGA */
> + mx31_gpio_mux(IOMUX_MODE(0x76, MUX_CTL_GPIO));
> + mx31_gpio_mux(IOMUX_MODE(0x7e, MUX_CTL_GPIO));
> + mx31_gpio_mux(IOMUX_MODE(0x91, MUX_CTL_OUT_FUNC | MUX_CTL_IN_GPIO));
> + mx31_gpio_mux(IOMUX_MODE(0x92, MUX_CTL_GPIO));
> + mx31_gpio_mux(IOMUX_MODE(0x93, MUX_CTL_GPIO));
> +#endif
> +
> + /* setup pins for UART1 */
> + mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX);
> + mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX);
> + mx31_gpio_mux(MUX_RTS1__UART1_RTS_B);
> + mx31_gpio_mux(MUX_CTS1__UART1_CTS_B);
> +
> + gd->bd->bi_arch_number = 1524; /* board id for linux */
please use macro
> + gd->bd->bi_boot_params = (0x80000100); /* adress of boot parameters */
> +
> + return 0;
> +}
> +
> +int checkboard (void)
> +{
> + printf("Board: DAVE/DENX QongEVB-LITE\n");
> + return 0;
> +}
> +
> +int misc_init_r (void)
> +{
> +#ifdef CONFIG_QONG_FPGA
> + u32 tmp;
> +
> + /* FPGA reset */
> + /* rstn = 0 */
> + tmp = __REG(GPIO2_BASE + GPIO_DR);
> + tmp &= (~(1 << QONG_FPGA_RST_PIN));
> + __REG(GPIO2_BASE + GPIO_DR) = tmp;
> + /* set the GPIO as output */
> + tmp = __REG(GPIO2_BASE + GPIO_GDIR);
> + tmp |= (1 << QONG_FPGA_RST_PIN);
> + __REG(GPIO2_BASE + GPIO_GDIR) = tmp;
> + /* wait */
> + udelay(30);
> + /* rstn = 1 */
> + tmp = __REG(GPIO2_BASE + GPIO_DR);
> + tmp |= (1 << QONG_FPGA_RST_PIN);
> + __REG(GPIO2_BASE + GPIO_DR) = tmp;
> + /* set interrupt pin as input */
> + __REG(GPIO2_BASE + GPIO_GDIR) = tmp | (1 << QONG_FPGA_IRQ_PIN);
> + /* wait while the FPGA starts */
> + udelay(300);
> +
> + tmp = *(volatile u32*)QONG_FPGA_CTRL_VERSION;
> + printf("FPGA: ");
> + printf("version register = %u.%u.%u\n",
> + (tmp & 0xF000)>>12, (tmp & 0x0F00) >> 8, tmp & 0x00FF);
please add a space before and after '>>'
> +#endif
> +
> + return 0;
> +}
> +
> +int board_eth_init(bd_t *bis)
> +{
> +#if defined(CONFIG_QONG_FPGA) && defined(CONFIG_DNET)
> + return dnet_eth_initialize(0, (void *)CONFIG_DNET_BASE, -1);
> +#else
> + return 0;
> +#endif
> +}
> +
> +#define CONFIG_ENV_IS_IN_FLASH 1
> +#define CONFIG_ENV_SECT_SIZE 0x20000
> +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
> +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+(0x40000))
please add space before and after '+'
> +
> +/* Address and size of Redundant Environment Sector */
> +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
> +#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
> +
Best Regards,
J.