[U-Boot] [PATCH 0/3] OMAP3:NAND: Cleanup patchset

[U-Boot] [PATCH 0/3] OMAP3:NAND: Cleanup patchset

[Nishanth Menon]

Hi,
The following patch series provides cleanup for making
OMAP3 NAND support more generic. This consists of:
a) OMAP3:NAND: Change the NAND timing assignment
b) OMAP3:NAND: Change the NAND CS handling
c) OMAP3:NAND: rename SMNAND_ENV_OFFSET

Regards,
Nishanth Menon

[U-Boot] [PATCH 1/3] OMAP3:NAND: Change the NAND timing assignment

[Nishanth Menon]

NAND timing is defaulted to Micron NAND. To support
varied boards, this is not scalable.
This patch introduces compile time option to select
the timing to select at the same time allows
platforms to build with custom timing params

Signed-off-by: Nishanth Menon <nm@ti.com>
---
 cpu/arm_cortexa8/omap3/mem.c     |   12 ++++++------
 include/asm-arm/arch-omap3/mem.h |   38 +++++++++++++++++++++++---------------
 include/configs/omap3_beagle.h   |    1 +
 include/configs/omap3_overo.h    |    1 +
 include/configs/omap3_pandora.h  |    1 +
 include/configs/omap3_zoom1.h    |    1 +
 6 files changed, 33 insertions(+), 21 deletions(-)

diff --git a/cpu/arm_cortexa8/omap3/mem.c b/cpu/arm_cortexa8/omap3/mem.c
index 3cc22c4..14cd87d 100644
--- a/cpu/arm_cortexa8/omap3/mem.c
+++ b/cpu/arm_cortexa8/omap3/mem.c
@@ -43,12 +43,12 @@ volatile unsigned int boot_flash_env_addr;
 
 #if defined(CONFIG_CMD_NAND)
 static u32 gpmc_m_nand[GPMC_MAX_REG] = {
-	M_NAND_GPMC_CONFIG1,
-	M_NAND_GPMC_CONFIG2,
-	M_NAND_GPMC_CONFIG3,
-	M_NAND_GPMC_CONFIG4,
-	M_NAND_GPMC_CONFIG5,
-	M_NAND_GPMC_CONFIG6, 0
+	NAND_GPMC_CONFIG1,
+	NAND_GPMC_CONFIG2,
+	NAND_GPMC_CONFIG3,
+	NAND_GPMC_CONFIG4,
+	NAND_GPMC_CONFIG5,
+	NAND_GPMC_CONFIG6, 0
 };
 
 gpmc_csx_t *nand_cs_base;
diff --git a/include/asm-arm/arch-omap3/mem.h b/include/asm-arm/arch-omap3/mem.h
index 6f0f90b..622578e 100644
--- a/include/asm-arm/arch-omap3/mem.h
+++ b/include/asm-arm/arch-omap3/mem.h
@@ -137,21 +137,29 @@ typedef enum {
 #define GPMC_SIZE_32M	0xE
 #define GPMC_SIZE_16M	0xF
 
-#define SMNAND_GPMC_CONFIG1	0x00000800
-#define SMNAND_GPMC_CONFIG2	0x00141400
-#define SMNAND_GPMC_CONFIG3	0x00141400
-#define SMNAND_GPMC_CONFIG4	0x0F010F01
-#define SMNAND_GPMC_CONFIG5	0x010C1414
-#define SMNAND_GPMC_CONFIG6	0x1F0F0A80
-#define SMNAND_GPMC_CONFIG7	0x00000C44
-
-#define M_NAND_GPMC_CONFIG1	0x00001800
-#define M_NAND_GPMC_CONFIG2	0x00141400
-#define M_NAND_GPMC_CONFIG3	0x00141400
-#define M_NAND_GPMC_CONFIG4	0x0F010F01
-#define M_NAND_GPMC_CONFIG5	0x010C1414
-#define M_NAND_GPMC_CONFIG6	0x1f0f0A80
-#define M_NAND_GPMC_CONFIG7	0x00000C44
+/*
+ * Standard OMAP3 NAND device definitions
+ * Define SMNAND_GPMC or M_NAND_GPMC to use the defaults
+ * if your board has a specific timing (such as optimized timing),
+ * define NAND_GPMC_CONFIG1 to 7
+ */
+#ifdef SMNAND_GPMC
+#define NAND_GPMC_CONFIG1	0x00000800
+#define NAND_GPMC_CONFIG2	0x00141400
+#define NAND_GPMC_CONFIG3	0x00141400
+#define NAND_GPMC_CONFIG4	0x0F010F01
+#define NAND_GPMC_CONFIG5	0x010C1414
+#define NAND_GPMC_CONFIG6	0x1F0F0A80
+#define NAND_GPMC_CONFIG7	0x00000C44
+#elif defined(M_NAND_GPMC)
+#define NAND_GPMC_CONFIG1	0x00001800
+#define NAND_GPMC_CONFIG2	0x00141400
+#define NAND_GPMC_CONFIG3	0x00141400
+#define NAND_GPMC_CONFIG4	0x0F010F01
+#define NAND_GPMC_CONFIG5	0x010C1414
+#define NAND_GPMC_CONFIG6	0x1f0f0A80
+#define NAND_GPMC_CONFIG7	0x00000C44
+#endif
 
 #define STNOR_GPMC_CONFIG1	0x3
 #define STNOR_GPMC_CONFIG2	0x00151501
diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h
index 5a948e4..3f47b7a 100644
--- a/include/configs/omap3_beagle.h
+++ b/include/configs/omap3_beagle.h
@@ -126,6 +126,7 @@
  * Board NAND Info.
  */
 #define CONFIG_NAND_OMAP_GPMC
+#define M_NAND_GPMC
 #define CONFIG_SYS_NAND_ADDR		NAND_BASE	/* physical address */
 							/* to access nand */
 #define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h
index 51b04b6..093f922 100644
--- a/include/configs/omap3_overo.h
+++ b/include/configs/omap3_overo.h
@@ -113,6 +113,7 @@
  * Board NAND Info.
  */
 #define CONFIG_NAND_OMAP_GPMC
+#define M_NAND_GPMC
 #define CONFIG_SYS_NAND_ADDR		NAND_BASE	/* physical address */
 							/* to access nand */
 #define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
diff --git a/include/configs/omap3_pandora.h b/include/configs/omap3_pandora.h
index 40107a6..7c3d2f0 100644
--- a/include/configs/omap3_pandora.h
+++ b/include/configs/omap3_pandora.h
@@ -116,6 +116,7 @@
  * Board NAND Info.
  */
 #define CONFIG_NAND_OMAP_GPMC
+#define M_NAND_GPMC
 #define CONFIG_SYS_NAND_ADDR		NAND_BASE	/* physical address */
 							/* to access nand */
 #define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
diff --git a/include/configs/omap3_zoom1.h b/include/configs/omap3_zoom1.h
index 8e984b4..794ad96 100644
--- a/include/configs/omap3_zoom1.h
+++ b/include/configs/omap3_zoom1.h
@@ -123,6 +123,7 @@
  * Board NAND Info.
  */
 #define CONFIG_NAND_OMAP_GPMC
+#define M_NAND_GPMC
 #define CONFIG_SYS_NAND_ADDR		NAND_BASE	/* physical address */
 							/* to access nand */
 #define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
-- 
1.5.4.3

[U-Boot] [PATCH 2/3] OMAP3:NAND: Change the NAND CS handling

[Nishanth Menon]

NAND CS is assumed to be CS0 while we could have
choice b/w 0 to 7. This patch enables board files
to handle varied CS on a need basis.

Signed-off-by: Nishanth Menon <nm@ti.com>
---
 cpu/arm_cortexa8/omap3/mem.c     |    8 +-------
 include/asm-arm/arch-omap3/mem.h |    8 ++++++++
 2 files changed, 9 insertions(+), 7 deletions(-)

diff --git a/cpu/arm_cortexa8/omap3/mem.c b/cpu/arm_cortexa8/omap3/mem.c
index 14cd87d..9c90f32 100644
--- a/cpu/arm_cortexa8/omap3/mem.c
+++ b/cpu/arm_cortexa8/omap3/mem.c
@@ -54,12 +54,6 @@ static u32 gpmc_m_nand[GPMC_MAX_REG] = {
 gpmc_csx_t *nand_cs_base;
 gpmc_t *gpmc_cfg_base;
 
-#if defined(CONFIG_ENV_IS_IN_NAND)
-#define GPMC_CS 0
-#else
-#define GPMC_CS 1
-#endif
-
 #endif
 
 #if defined(CONFIG_CMD_ONENAND)
@@ -249,7 +243,7 @@ void gpmc_init(void)
 	gpmc_config = gpmc_m_nand;
 	gpmc_cfg_base = gpmc_base;
 	nand_cs_base = (gpmc_csx_t *)(GPMC_CONFIG_CS0_BASE +
-					(GPMC_CS * GPMC_CONFIG_WIDTH));
+					(NAND_GPMC_CS * GPMC_CONFIG_WIDTH));
 	base = PISMO1_NAND_BASE;
 	size = PISMO1_NAND_SIZE;
 	enable_gpmc_config(gpmc_config, nand_cs_base, base, size);
diff --git a/include/asm-arm/arch-omap3/mem.h b/include/asm-arm/arch-omap3/mem.h
index 622578e..1c4abe7 100644
--- a/include/asm-arm/arch-omap3/mem.h
+++ b/include/asm-arm/arch-omap3/mem.h
@@ -216,6 +216,14 @@ typedef enum {
 /* max number of GPMC regs */
 #define GPMC_MAX_REG	7
 
+#if defined(CONFIG_ENV_IS_IN_NAND)
+#define NAND_GPMC_CS 0
+#else
+#ifndef NAND_GPMC_CS
+#define NAND_GPMC_CS 1
+#endif		/* NAND_GPMC_CS */
+#endif		/* CONFIG_ENV_IS_IN_NAND */
+
 #define PISMO1_NOR	1
 #define PISMO1_NAND	2
 #define PISMO2_CS0	3
-- 
1.5.4.3

[U-Boot] [PATCH 3/3] OMAP3:NAND: rename SMNAND_ENV_OFFSET

[Nishanth Menon]

SMNAND_ENV_OFFSET is more specific to Samsung
NAND, rename it to NAND_ENV_OFFSET

Signed-off-by: Nishanth Menon <nm@ti.com>
---
 cpu/arm_cortexa8/omap3/mem.c    |    2 +-
 include/configs/omap3_beagle.h  |    4 ++--
 include/configs/omap3_evm.h     |    2 +-
 include/configs/omap3_overo.h   |    4 ++--
 include/configs/omap3_pandora.h |    4 ++--
 include/configs/omap3_zoom1.h   |    4 ++--
 6 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/cpu/arm_cortexa8/omap3/mem.c b/cpu/arm_cortexa8/omap3/mem.c
index 9c90f32..ac126fd 100644
--- a/cpu/arm_cortexa8/omap3/mem.c
+++ b/cpu/arm_cortexa8/omap3/mem.c
@@ -248,7 +248,7 @@ void gpmc_init(void)
 	size = PISMO1_NAND_SIZE;
 	enable_gpmc_config(gpmc_config, nand_cs_base, base, size);
 #if defined(CONFIG_ENV_IS_IN_NAND)
-	f_off = SMNAND_ENV_OFFSET;
+	f_off = NAND_ENV_OFFSET;
 	f_sec = SZ_128K;
 	/* env setup */
 	boot_flash_base = base;
diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h
index 3f47b7a..30b2cfd 100644
--- a/include/configs/omap3_beagle.h
+++ b/include/configs/omap3_beagle.h
@@ -276,11 +276,11 @@
 
 #define CONFIG_ENV_IS_IN_NAND		1
 #define ONENAND_ENV_OFFSET		0x260000 /* environment starts here */
-#define SMNAND_ENV_OFFSET		0x260000 /* environment starts here */
+#define NAND_ENV_OFFSET			0x260000 /* environment starts here */
 
 #define CONFIG_SYS_ENV_SECT_SIZE	boot_flash_sec
 #define CONFIG_ENV_OFFSET		boot_flash_off
-#define CONFIG_ENV_ADDR			SMNAND_ENV_OFFSET
+#define CONFIG_ENV_ADDR			NAND_ENV_OFFSET
 
 /*-----------------------------------------------------------------------
  * CFI FLASH driver setup
diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h
index 8cd8a1b..c33d981 100644
--- a/include/configs/omap3_evm.h
+++ b/include/configs/omap3_evm.h
@@ -268,7 +268,7 @@
 
 #define CONFIG_ENV_IS_IN_ONENAND	1
 #define ONENAND_ENV_OFFSET		0x260000 /* environment starts here */
-#define SMNAND_ENV_OFFSET		0x260000 /* environment starts here */
+#define NAND_ENV_OFFSET			0x260000 /* environment starts here */
 
 #define CONFIG_SYS_ENV_SECT_SIZE	boot_flash_sec
 #define CONFIG_ENV_OFFSET		boot_flash_off
diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h
index 093f922..259b864 100644
--- a/include/configs/omap3_overo.h
+++ b/include/configs/omap3_overo.h
@@ -263,11 +263,11 @@
 
 #define CONFIG_ENV_IS_IN_NAND		1
 #define ONENAND_ENV_OFFSET		0x240000 /* environment starts here */
-#define SMNAND_ENV_OFFSET		0x240000 /* environment starts here */
+#define NAND_ENV_OFFSET			0x240000 /* environment starts here */
 
 #define CONFIG_SYS_ENV_SECT_SIZE	boot_flash_sec
 #define CONFIG_ENV_OFFSET		boot_flash_off
-#define CONFIG_ENV_ADDR			SMNAND_ENV_OFFSET
+#define CONFIG_ENV_ADDR			NAND_ENV_OFFSET
 
 /*-----------------------------------------------------------------------
  * CFI FLASH driver setup
diff --git a/include/configs/omap3_pandora.h b/include/configs/omap3_pandora.h
index 7c3d2f0..7deecb7 100644
--- a/include/configs/omap3_pandora.h
+++ b/include/configs/omap3_pandora.h
@@ -265,11 +265,11 @@
 
 #define CONFIG_ENV_IS_IN_NAND		1
 #define ONENAND_ENV_OFFSET		0x240000 /* environment starts here */
-#define SMNAND_ENV_OFFSET		0x240000 /* environment starts here */
+#define NAND_ENV_OFFSET			0x240000 /* environment starts here */
 
 #define CONFIG_SYS_ENV_SECT_SIZE	boot_flash_sec
 #define CONFIG_ENV_OFFSET		boot_flash_off
-#define CONFIG_ENV_ADDR			SMNAND_ENV_OFFSET
+#define CONFIG_ENV_ADDR			NAND_ENV_OFFSET
 
 /*-----------------------------------------------------------------------
  * CFI FLASH driver setup
diff --git a/include/configs/omap3_zoom1.h b/include/configs/omap3_zoom1.h
index 794ad96..34e6868 100644
--- a/include/configs/omap3_zoom1.h
+++ b/include/configs/omap3_zoom1.h
@@ -273,11 +273,11 @@
 
 #define CONFIG_ENV_IS_IN_NAND		1
 #define ONENAND_ENV_OFFSET		0x260000 /* environment starts here */
-#define SMNAND_ENV_OFFSET		0x260000 /* environment starts here */
+#define NAND_ENV_OFFSET			0x260000 /* environment starts here */
 
 #define CONFIG_SYS_ENV_SECT_SIZE	boot_flash_sec
 #define CONFIG_ENV_OFFSET		boot_flash_off
-#define CONFIG_ENV_ADDR			SMNAND_ENV_OFFSET
+#define CONFIG_ENV_ADDR			NAND_ENV_OFFSET
 
 /*-----------------------------------------------------------------------
  * CFI FLASH driver setup
-- 
1.5.4.3

[U-Boot] [PATCH 1/3] OMAP3:NAND: Change the NAND timing assignment

[Jean-Christophe PLAGNIOL-VILLARD]

On 15:48 Mon 13 Apr     , Nishanth Menon wrote:
> NAND timing is defaulted to Micron NAND. To support
> varied boards, this is not scalable.
> This patch introduces compile time option to select
> the timing to select at the same time allows
> platforms to build with custom timing params
> 
> Signed-off-by: Nishanth Menon <nm@ti.com>
> ---
>  cpu/arm_cortexa8/omap3/mem.c     |   12 ++++++------
>  include/asm-arm/arch-omap3/mem.h |   38 +++++++++++++++++++++++---------------
>  include/configs/omap3_beagle.h   |    1 +
>  include/configs/omap3_overo.h    |    1 +
>  include/configs/omap3_pandora.h  |    1 +
>  include/configs/omap3_zoom1.h    |    1 +
>  6 files changed, 33 insertions(+), 21 deletions(-)
> 
> diff --git a/cpu/arm_cortexa8/omap3/mem.c b/cpu/arm_cortexa8/omap3/mem.c
> index 3cc22c4..14cd87d 100644
> --- a/cpu/arm_cortexa8/omap3/mem.c
> +++ b/cpu/arm_cortexa8/omap3/mem.c
> @@ -43,12 +43,12 @@ volatile unsigned int boot_flash_env_addr;
>  
>  #if defined(CONFIG_CMD_NAND)
>  static u32 gpmc_m_nand[GPMC_MAX_REG] = {
> -	M_NAND_GPMC_CONFIG1,
> -	M_NAND_GPMC_CONFIG2,
> -	M_NAND_GPMC_CONFIG3,
> -	M_NAND_GPMC_CONFIG4,
> -	M_NAND_GPMC_CONFIG5,
> -	M_NAND_GPMC_CONFIG6, 0
> +	NAND_GPMC_CONFIG1,
> +	NAND_GPMC_CONFIG2,
> +	NAND_GPMC_CONFIG3,
> +	NAND_GPMC_CONFIG4,
> +	NAND_GPMC_CONFIG5,
> +	NAND_GPMC_CONFIG6, 0
>  };
>  
>  gpmc_csx_t *nand_cs_base;
> diff --git a/include/asm-arm/arch-omap3/mem.h b/include/asm-arm/arch-omap3/mem.h
> index 6f0f90b..622578e 100644
> --- a/include/asm-arm/arch-omap3/mem.h
> +++ b/include/asm-arm/arch-omap3/mem.h
> @@ -137,21 +137,29 @@ typedef enum {
>  #define GPMC_SIZE_32M	0xE
>  #define GPMC_SIZE_16M	0xF
>  
> -#define SMNAND_GPMC_CONFIG1	0x00000800
> -#define SMNAND_GPMC_CONFIG2	0x00141400
> -#define SMNAND_GPMC_CONFIG3	0x00141400
> -#define SMNAND_GPMC_CONFIG4	0x0F010F01
> -#define SMNAND_GPMC_CONFIG5	0x010C1414
> -#define SMNAND_GPMC_CONFIG6	0x1F0F0A80
> -#define SMNAND_GPMC_CONFIG7	0x00000C44
> -
> -#define M_NAND_GPMC_CONFIG1	0x00001800
> -#define M_NAND_GPMC_CONFIG2	0x00141400
> -#define M_NAND_GPMC_CONFIG3	0x00141400
> -#define M_NAND_GPMC_CONFIG4	0x0F010F01
> -#define M_NAND_GPMC_CONFIG5	0x010C1414
> -#define M_NAND_GPMC_CONFIG6	0x1f0f0A80
> -#define M_NAND_GPMC_CONFIG7	0x00000C44
> +/*
> + * Standard OMAP3 NAND device definitions
> + * Define SMNAND_GPMC or M_NAND_GPMC to use the defaults
> + * if your board has a specific timing (such as optimized timing),
> + * define NAND_GPMC_CONFIG1 to 7
> + */
> +#ifdef SMNAND_GPMC
> +#define NAND_GPMC_CONFIG1	0x00000800
> +#define NAND_GPMC_CONFIG2	0x00141400
> +#define NAND_GPMC_CONFIG3	0x00141400
> +#define NAND_GPMC_CONFIG4	0x0F010F01
> +#define NAND_GPMC_CONFIG5	0x010C1414
> +#define NAND_GPMC_CONFIG6	0x1F0F0A80
> +#define NAND_GPMC_CONFIG7	0x00000C44
is it possible to use macro insteas of hardcode value?

Best Regards,
J.

[U-Boot] [PATCH 2/3] OMAP3:NAND: Change the NAND CS handling

[Jean-Christophe PLAGNIOL-VILLARD]

On 15:48 Mon 13 Apr     , Nishanth Menon wrote:
> NAND CS is assumed to be CS0 while we could have
> choice b/w 0 to 7. This patch enables board files
> to handle varied CS on a need basis.
> 
> Signed-off-by: Nishanth Menon <nm@ti.com>
> ---
>  cpu/arm_cortexa8/omap3/mem.c     |    8 +-------
>  include/asm-arm/arch-omap3/mem.h |    8 ++++++++
>  2 files changed, 9 insertions(+), 7 deletions(-)
> 
> diff --git a/cpu/arm_cortexa8/omap3/mem.c b/cpu/arm_cortexa8/omap3/mem.c
> index 14cd87d..9c90f32 100644
> --- a/cpu/arm_cortexa8/omap3/mem.c
> +++ b/cpu/arm_cortexa8/omap3/mem.c
> @@ -54,12 +54,6 @@ static u32 gpmc_m_nand[GPMC_MAX_REG] = {
>  gpmc_csx_t *nand_cs_base;
>  gpmc_t *gpmc_cfg_base;
>  
> -#if defined(CONFIG_ENV_IS_IN_NAND)
> -#define GPMC_CS 0
> -#else
> -#define GPMC_CS 1
> -#endif
> -
>  #endif
>  
>  #if defined(CONFIG_CMD_ONENAND)
> @@ -249,7 +243,7 @@ void gpmc_init(void)
>  	gpmc_config = gpmc_m_nand;
>  	gpmc_cfg_base = gpmc_base;
>  	nand_cs_base = (gpmc_csx_t *)(GPMC_CONFIG_CS0_BASE +
> -					(GPMC_CS * GPMC_CONFIG_WIDTH));
> +					(NAND_GPMC_CS * GPMC_CONFIG_WIDTH));
>  	base = PISMO1_NAND_BASE;
>  	size = PISMO1_NAND_SIZE;
>  	enable_gpmc_config(gpmc_config, nand_cs_base, base, size);
> diff --git a/include/asm-arm/arch-omap3/mem.h b/include/asm-arm/arch-omap3/mem.h
> index 622578e..1c4abe7 100644
> --- a/include/asm-arm/arch-omap3/mem.h
> +++ b/include/asm-arm/arch-omap3/mem.h
> @@ -216,6 +216,14 @@ typedef enum {
>  /* max number of GPMC regs */
>  #define GPMC_MAX_REG	7
>  
> +#if defined(CONFIG_ENV_IS_IN_NAND)
> +#define NAND_GPMC_CS 0
please use CONFIG_SYS_

Best Regards,
J.

[U-Boot] [PATCH 3/3] OMAP3:NAND: rename SMNAND_ENV_OFFSET

[Jean-Christophe PLAGNIOL-VILLARD]

On 15:48 Mon 13 Apr     , Nishanth Menon wrote:
> SMNAND_ENV_OFFSET is more specific to Samsung
> NAND, rename it to NAND_ENV_OFFSET
> 
CONFIG_ENV_NAND_OFFSET or something simillar will be beter

Best Regards,
J.