From mboxrd@z Thu Jan 1 00:00:00 1970 From: Steve Chen Date: Tue, 28 Apr 2009 15:54:08 -0500 Subject: [U-Boot] [PATCH] ARM DaVinci: Adding CONFIG options for NAND ALE and CLE In-Reply-To: <1240950794-30050-1-git-send-email-s-paulraj@ti.com> References: <1240950794-30050-1-git-send-email-s-paulraj@ti.com> Message-ID: <1240952049.3101.94.camel@linux-1lbu> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On Tue, 2009-04-28 at 16:33 -0400, s-paulraj at ti.com wrote: > The CLE and ALE for DaVinci DM644x is not the same as DM646x. This patch > adds 2 CONFIG_ options to the config.h header files to all the DM6446 based > boards. These values are then used by the driver. This has been tested on the > DM644x, DM355, DM357 and DM365. Support for the latter 3 will be added soon. > > Signed-off-by: Sandeep Paulraj > --- > drivers/mtd/nand/davinci_nand.c | 6 +++--- > include/asm-arm/arch-davinci/nand_defs.h | 9 ++++----- > include/configs/davinci_dvevm.h | 2 ++ > include/configs/davinci_schmoogie.h | 2 ++ > include/configs/davinci_sffsdr.h | 2 ++ > include/configs/davinci_sonata.h | 2 ++ > 6 files changed, 15 insertions(+), 8 deletions(-) > > diff --git a/drivers/mtd/nand/davinci_nand.c b/drivers/mtd/nand/davinci_nand.c > index a974667..dcc0f39 100644 > --- a/drivers/mtd/nand/davinci_nand.c > +++ b/drivers/mtd/nand/davinci_nand.c > @@ -54,13 +54,13 @@ static void nand_davinci_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int c > struct nand_chip *this = mtd->priv; > u_int32_t IO_ADDR_W = (u_int32_t)this->IO_ADDR_W; > > - IO_ADDR_W &= ~(MASK_ALE|MASK_CLE); > + IO_ADDR_W &= ~(CONFIG_MASK_ALE | CONFIG_MASK_CLE); > > if (ctrl & NAND_CTRL_CHANGE) { > if ( ctrl & NAND_CLE ) > - IO_ADDR_W |= MASK_CLE; > + IO_ADDR_W |= CONFIG_MASK_CLE; > if ( ctrl & NAND_ALE ) > - IO_ADDR_W |= MASK_ALE; > + IO_ADDR_W |= CONFIG_MASK_ALE; When I modified this code in the MV kernel, I remember having to use += and -= instead of |= and &=. The reason is tha DM6467 CLE/ALE mask has large enough that the bits overlaps IO_ADDR_W.