From mboxrd@z Thu Jan 1 00:00:00 1970 From: Peter Tyser Date: Fri, 04 Sep 2009 10:28:12 -0500 Subject: [U-Boot] Odd value for I2C_TIMEOUT in fsl_i2c.c In-Reply-To: <4AA12E52.2080403@freescale.com> References: <4A9FDF1E.4090908@freescale.com> <4AA0BEC5.3010505@denx.de> <20090904092503.058A0832E8DE@gemini.denx.de> <20090904150135.E88CB832E8DE@gemini.denx.de> <4AA12E52.2080403@freescale.com> Message-ID: <1252078092.6005.63.camel@localhost.localdomain> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On Fri, 2009-09-04 at 10:12 -0500, Timur Tabi wrote: > Wolfgang Denk wrote: > > > Wrong Question. I don't know enough about the I2C protocol. Why is > > i2c_wait4bus necessary? > > Ok, why is it necessary? Freescale's I2C core supports multiple masters. I'd guess that i2c_wait4bus() is used to ensure the bus is not in use by a different master before initiating a read or write. Its polling the MBB status bit, which is automatically set/cleared when the controller sees a START/STOP which supports this. If this is the case, the timeout should be the maximum (or reasonable maximum) time an I2C transaction could take. Best, Peter