[U-Boot] [PATCH 6/7] ppc/p4080: Handle timebase enabling and frequency reporting

[Kumar Gala <galak@kernel.crashing.org>]

On CoreNet style platforms the timebase frequency is the bus frequency
defined by 16 (on PQ3 it is divide by 8).  Also on the CoreNet platforms
the core not longer controls the enabling of the timebase.  We now need
to enable the boot core's timebase via CCSR register writes.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
 cpu/mpc85xx/cpu.c      |    4 ++++
 cpu/mpc85xx/cpu_init.c |   12 ++++++++++++
 cpu/mpc85xx/fdt.c      |    7 ++++++-
 3 files changed, 22 insertions(+), 1 deletions(-)

diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c
index bdd9ee4..25c0416 100644
--- a/cpu/mpc85xx/cpu.c
+++ b/cpu/mpc85xx/cpu.c
@@ -184,7 +184,11 @@ int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
  */
 unsigned long get_tbclk (void)
 {
+#ifdef CONFIG_FSL_CORENET
+	return (gd->bus_clk + 8) / 16;
+#else
 	return (gd->bus_clk + 4UL)/8UL;
+#endif
 }
 
 
diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c
index a6d1e99..428b461 100644
--- a/cpu/mpc85xx/cpu_init.c
+++ b/cpu/mpc85xx/cpu_init.c
@@ -229,6 +229,18 @@ void cpu_init_f (void)
 #if defined(CONFIG_FSL_DMA)
 	dma_init();
 #endif
+#ifdef CONFIG_FSL_CORENET
+	{
+		volatile ccsr_rcpm_t *rcpm =
+			(void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
+		volatile ccsr_pic_t *pic =
+			(void *)(CONFIG_SYS_MPC85xx_PIC_ADDR);
+		u32 whoami = in_be32(&pic->whoami);
+
+		/* Enable the timebase register for this core */
+		out_be32(&rcpm->ctbenrl, (1 << whoami));
+	}
+#endif
 }
 
 
diff --git a/cpu/mpc85xx/fdt.c b/cpu/mpc85xx/fdt.c
index 723f473..ff5824b 100644
--- a/cpu/mpc85xx/fdt.c
+++ b/cpu/mpc85xx/fdt.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2007 Freescale Semiconductor, Inc.
+ * Copyright 2007-2009 Freescale Semiconductor, Inc.
  *
  * (C) Copyright 2000
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
@@ -286,8 +286,13 @@ void ft_cpu_setup(void *blob, bd_t *bd)
 
 	fdt_add_enet_stashing(blob);
 
+#ifdef CONFIG_FSL_CORENET
+	do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
+		"timebase-frequency", bd->bi_busfreq / 16, 1);
+#else
 	do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
 		"timebase-frequency", bd->bi_busfreq / 8, 1);
+#endif
 	do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
 		"bus-frequency", bd->bi_busfreq, 1);
 	get_sys_info(&sysinfo);
-- 
1.6.0.6