[U-Boot] [PATCH v3 1/7] ppc/p4080: Add p4080 platform immap definitions

[U-Boot] [PATCH v3 1/7] ppc/p4080: Add p4080 platform immap definitions

[Kumar Gala]

The p4080 SoC has a significant amount of commonality with the 85xx/PQ3
platform.  We reuse the 85xx immap and just add new definitions for
local access and global utils.  The global utils is now broken into
global utils, clocking and run control/power management.

The offsets from CCSR for a number of blocks have also changed.  We
introduce the CONFIG_FSL_CORENET define to distinquish the PQ3 style of
platform from the new p4080 platform.  We don't use QoirQ as there are
products (like p2020) that are PQ3 based platforms but have the QoirQ
name.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
* Moved LAWs to be an array

 include/asm-ppc/fsl_lbc.h    |    4 +
 include/asm-ppc/immap_85xx.h |  287 +++++++++++++++++++++++++++++++++++++++---
 2 files changed, 271 insertions(+), 20 deletions(-)

diff --git a/include/asm-ppc/fsl_lbc.h b/include/asm-ppc/fsl_lbc.h
index 08d31e1..5723de6 100644
--- a/include/asm-ppc/fsl_lbc.h
+++ b/include/asm-ppc/fsl_lbc.h
@@ -317,6 +317,10 @@
 #define LCRR_CLKDIV_2			0x00000002
 #define LCRR_CLKDIV_4			0x00000004
 #define LCRR_CLKDIV_8			0x00000008
+#elif defined(CONFIG_FSL_CORENET)
+#define LCRR_CLKDIV_8			0x00000002
+#define LCRR_CLKDIV_16			0x00000004
+#define LCRR_CLKDIV_32			0x00000008
 #else
 #define LCRR_CLKDIV_4			0x00000002
 #define LCRR_CLKDIV_8			0x00000004
diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h
index e7d412d..3e6ed85 100644
--- a/include/asm-ppc/immap_85xx.h
+++ b/include/asm-ppc/immap_85xx.h
@@ -16,6 +16,29 @@
 #include <asm/fsl_i2c.h>
 #include <asm/fsl_lbc.h>
 
+typedef struct ccsr_local {
+	u32	ccsrbarh;	/* 0x0 - Control Configuration Status Registers Base Address Register High */
+	u32	ccsrbarl;	/* 0x4 - Control Configuration Status Registers Base Address Register Low */
+	u32	ccsrar;		/* 0x8 - Configuration, Control, and Status Attribute Register */
+#define CCSRAR_C	0x80000000	/* Commit */
+	u8	res1[4];
+	u32	altcbarh;	/* 0x10 - Alternate Configuration Base Address Register High */
+	u32	altcbarl;	/* 0x14 - Alternate Configuration Base Address Register Low */
+	u32	altcar;		/* 0x18 - Alternate Configuration Attribute Register */
+	u8	res2[4];
+	u32	bstrh;		/* 0x20 - Boot space translation register high */
+	u32	bstrl;		/* 0x24 - Boot space translation register Low */
+	u32	bstrar;		/* 0x28 - Boot space translation attributes register */
+	u8	res3[0xbd4];
+	struct {
+		u32	lawbarh;	/* 0xc00 + n * 0x10 - LAW0 base address register high */
+		u32	lawbarl;	/* 0xc04 + n * 0x10 - LAW0 base address register low */
+		u32	lawar;		/* 0xc08 + n * 0x10 - LAW0 attributes register */
+		u8	res4[4];
+	} law[32];
+	u8	res35[0x204];
+} ccsr_local_t;
+
 /*
  * Local-Access Registers and ECM Registers(0x0000-0x2000)
  */
@@ -165,7 +188,21 @@ typedef struct ccsr_ddr {
 	uint	debug_2;
 	uint	debug_3;
 	uint	debug_4;
-	char	res12[240];
+	uint	debug_5;
+	uint	debug_6;
+	uint	debug_7;
+	uint	debug_8;
+	uint	debug_9;
+	uint	debug_10;
+	uint	debug_11;
+	uint	debug_12;
+	uint	debug_13;		/* +0xF30 */
+	uint	debug_14;
+	uint	debug_15;
+	uint	debug_16;
+	uint	debug_17;
+	uint    debug_18;               /* +0xF44 */
+	char    res12[184];
 } ccsr_ddr_t;
 
 /*
@@ -1531,6 +1568,193 @@ typedef struct par_io {
 /*
  * Global Utilities Register Block(0xe_0000-0xf_ffff)
  */
+#ifdef CONFIG_FSL_CORENET
+typedef struct ccsr_gur {
+	u32	porsr1;		/* 0xe0000 - POR status register */
+	u8	res1[28];	/* 0xe0004 - 0xe001c Reserved: PORSRn */
+	u32	gpporcr1;	/* 0xe0020 - General-purpose POR configuration register */
+	u8	res2[12];
+	u32	gpiocr;		/* 0xe0030 - GPIO control register */
+	u8	res3[12];
+	u32	gpoutdr;	/* 0xe0040 - General-purpose output data register */
+	u8	res4[12];
+	u32	gpindr;		/* 0xe0050 - General-purpose input data register */
+	u8	res5[12];
+	u32	pmuxcr;		/* 0xe0060 - Alternate function signal multiplex control */
+	u8	res6[12];
+	u32	devdisr;	/* 0xe0070 - Device disable control */
+#define FSL_CORENET_DEVDISR_PCIE1	0x80000000
+#define FSL_CORENET_DEVDISR_PCIE2	0x40000000
+#define FSL_CORENET_DEVDISR_PCIE3	0x20000000
+#define FSL_CORENET_DEVDISR_RMU		0x08000000
+#define FSL_CORENET_DEVDISR_SRIO1	0x04000000
+#define FSL_CORENET_DEVDISR_SRIO2	0x02000000
+#define FSL_CORENET_DEVDISR_DMA1	0x00400000
+#define FSL_CORENET_DEVDISR_DMA2	0x00200000
+#define FSL_CORENET_DEVDISR_DDR1	0x00100000
+#define FSL_CORENET_DEVDISR_DDR2	0x00080000
+#define FSL_CORENET_DEVDISR_DBG		0x00010000
+#define FSL_CORENET_DEVDISR_NAL		0x00008000
+#define FSL_CORENET_DEVDISR_ELBC	0x00001000
+#define FSL_CORENET_DEVDISR_USB1	0x00000800
+#define FSL_CORENET_DEVDISR_USB2	0x00000400
+#define FSL_CORENET_DEVDISR_ESDHC	0x00000100
+#define FSL_CORENET_DEVDISR_GPIO	0x00000080
+#define FSL_CORENET_DEVDISR_ESPI	0x00000040
+#define FSL_CORENET_DEVDISR_I2C1	0x00000020
+#define FSL_CORENET_DEVDISR_I2C2	0x00000010
+#define FSL_CORENET_DEVDISR_DUART1	0x00000002
+#define FSL_CORENET_DEVDISR_DUART2	0x00000001
+	u8	res7[12];
+	u32	powmgtcsr;	/* 0xe0080 - Power management status and control register */
+	u8	res8[12];
+	u32	coredisru;	/* 0xe0090 - uppper portion for support of 64 cores */
+	u32	coredisrl;	/* 0xe0094 - lower portion for support of 64 cores */
+	u8	res9[8];
+	u32	pvr;		/* 0xe00a0 - Processor version register */
+	u32	svr;		/* 0xe00a4 - System version register */
+	u8	res10[8];
+	u32	rstcr;		/* 0xe00b0 - Reset control register */
+	u32	rstrqpblsr;	/* 0xe00b4 - Reset request preboot loader status register */
+	u8	res11[8];
+	u32	rstrqmr1;	/* 0xe00c0 - Reset request mask register */
+	u8	res12[4];	/* Reserved: RSTRQMR2 */
+	u32	rstrqsr1;	/* 0xe00c8 - Reset request status register */
+	u8	res13[4];	/* Reserved: RSTRQSR2 */
+	u8	res14[4];	/* Reserved: RSTRQWDTMRU */
+	u32	rstrqwdtmrl;	/* 0xe00d4 - Reset request WDT mask register */
+	u8	res15[4];	/* Reserved: RSTRQWDTSRU */
+	u32	rstrqwdtsrl;	/* 0xe00dc - Reset request WDT status register */
+	u8	res16[4];	/* Reserved: BRRU max total of  2 for up to 64 cores */
+	u32	brrl;		/* 0xe00e4 Boot release register */
+	u8	res17[24];
+	u32	rcwsr[16];	/* 0xe0100 - 0xe013c: Reset control word status register */
+#define FSL_CORENET_RCWSR4_SRDS_PRTCL		0xfc000000
+#define FSL_CORENET_RCWSR5_DDR_SYNC		0x00008000
+#define FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT		15
+#define FSL_CORENET_RCWSR7_MCK_TO_PLAT_RAT	0x00400000
+#define FSL_CORENET_RCWSR8_HOST_AGT_B1		0x00e00000
+#define FSL_CORENET_RCWSR8_HOST_AGT_B2		0x00100000
+	u8	res18[192];	/* Reserved: RCWSRn (max total of 64)*/
+	u32	scratchrw[4];	/* 0xe0200 - 0xe020c: Scratch Read/Write register */
+	u8	res19[240];	/* Reserved: SCRATCHRWn (max total of 64)*/
+	u32	scratchw1r[4];	/* 0xe0300 - 0xe030c: Scratch Read register (Write once) */
+	u8	res20[240];	/* Reserved: SCRATCHW1Rn (max total of 64)*/
+	u32	scrtsr[8];	/* 0xe0400 - 0xe041c: Core reset status register */
+	u8	res21[224];	/* Reserved: CRSTSRn (max total of 64 for up to 64 cores)*/
+	u32	pex1liodnr;	/* 0xe0500 PCI Express 1 Logical I/O Device Number register*/
+	u32	pex2liodnr;	/* 0xe0504 PCI Express 2 Logical I/O Device Number register*/
+	u32	pex3liodnr;	/* 0xe0508 PCI Express 3 Logical I/O Device Number register*/
+	u32	pex4liodnr;	/* 0xe050c PCI Express 4 Logical I/O Device Number register*/
+	u32	rio1liodnr;	/* 0xe0510 RIO 1 Logical I/O Device Number register*/
+	u32	rio2liodnr;	/* 0xe0514 RIO 2 Logical I/O Device Number register*/
+	u32	rio3liodnr;	/* 0xe0518 RIO 3 Logical I/O Device Number register*/
+	u32	rio4liodnr;	/* 0xe051c RIO 4 Logical I/O Device Number register*/
+	u32	usb1liodnr;	/* 0xe0520 USB 1 Logical I/O Device Number register*/
+	u32	usb2liodnr;	/* 0xe0524 USB 2 Logical I/O Device Number register*/
+	u32	usb3liodnr;	/* 0xe0528 USB 3 Logical I/O Device Number register*/
+	u32	usb4liodnr;	/* 0xe052c USB 4 Logical I/O Device Number register*/
+	u32	sdmmc1liodnr;	/* 0xe0530 SD/MMC 1 Logical I/O Device Number register*/
+	u32	sdmmc2liodnr;	/* 0xe0534 SD/MMC 2 Logical I/O Device Number register*/
+	u32	sdmmc3liodnr;	/* 0xe0538 SD/MMC 3 Logical I/O Device Number register*/
+	u32	sdmmc4liodnr;	/* 0xe053c SD/MMC 4 Logical I/O Device Number register*/
+	u32	rmuliodnr;	/* 0xe0540 RIO Message Unit Logical I/O Device Number register*/
+	u32	rduliodnr;	/* 0xe0544 RIO Doorbell Unit Logical I/O Device Number register*/
+	u32	rpwuliodnr;	/* 0xe0548 RIO Port Write Unit Logical I/O Device Number register*/
+	u8	res22[52];	/* Reserved: for future LIODN register expansion */
+	u32	dma1liodnr;	/* 0xe0580 DMA 1 Logical I/O Device Number register*/
+	u32	dma2liodnr;	/* 0xe0584 DMA 2 Logical I/O Device Number register*/
+	u32	dma3liodnr;	/* 0xe0588 DMA 3 Logical I/O Device Number register*/
+	u32	dma4liodnr;	/* 0xe058c DMA 4 Logical I/O Device Number register*/
+	u8	res23[48];	/* Reserved: for future LIODN register expansion */
+	u8	res24[64];	/* Reserved */
+	u32	pblsr;		/* 0xe0600 Preboot loader status register*/
+	u32	pamubypenr;	/* 0xe0604 PAMU bypass enable register*/
+	u32	dmacr1;		/* 0xe0608 DMA control register*/
+	u8	res25[4];	/* Reserved: DMACR2 (max total of 2)*/
+	u32	gensr1;		/* 0xe0610 General status register*/
+	u8	res26[12];	/* Reserved: GENSRn (max total of 4)*/
+	u32	gencr1;		/* 0xe0620 General control register*/
+	u8	res27[12];	/* Reserved: GENCRn (max total of 4)*/
+	u8	res28[4];	/* Reserved: CGENSRU (upper portion for support of 64 cores) */
+	u32	cgensrl;	/* 0xe0634 Core general status register*/
+	u8	res29[8];	/* Reserved */
+	u8	res30[4];	/* Reserved: CGENCRU (upper portion for support of 64 cores) */
+	u32	cgencrl;	/* 0xe0634 Core general control register*/
+	u8	res31[184];	/* Reserved 0xe0648 - 0xe06fc */
+	u32	sriopstecr;	/* 0xe0700 SRIO prescaler timer enable control register*/
+	u8	res32[2300];	/* Reserved 0xe0704 - 0xe0ffc */
+} ccsr_gur_t;
+
+typedef struct ccsr_clk {
+        u32     clkc0csr;       /* 0xe1000 - Core 0 Clock control/status register */
+        u8      res1[0x1c];
+        u32     clkc1csr;       /* 0xe1020 - Core 1 Clock control/status register */
+        u8      res2[0x1c];
+        u32     clkc2csr;       /* 0xe1040 - Core 2 Clock control/status register */
+        u8      res3[0x1c];
+        u32     clkc3csr;       /* 0xe1060 - Core 3 Clock control/status register */
+        u8      res4[0x1c];
+        u32     clkc4csr;       /* 0xe1080 - Core 4 Clock control/status register */
+        u8      res5[0x1c];
+        u32     clkc5csr;       /* 0xe10a0 - Core 5 Clock control/status register */
+        u8      res6[0x1c];
+        u32     clkc6csr;       /* 0xe10c0 - Core 6 Clock control/status register */
+        u8      res7[0x1c];
+        u32     clkc7csr;       /* 0xe10e0 - Core 7 Clock control/status register */
+        u8      res8[0x71c];
+        u32     pllc1gsr;       /* 0xe1800 - Cluster PLL 1 General Status Register */
+        u8      res10[0x1c];
+        u32     pllc2gsr;       /* 0xe1820 - Cluster PLL 2 General Status Register */
+        u8      res11[0x1c];
+        u32     pllc3gsr;       /* 0xe1840 - Cluster PLL 3 General Status Register */
+        u8      res12[0x1c];
+        u32     pllc4gsr;       /* 0xe1860 - Cluster PLL 4 General Status Register */
+        u8      res13[0x39c];
+        u32     pllpgsr;        /* 0xe1c00 - Platform PLL General Status Register */
+        u8      res14[0x1c];
+        u32     plldgsr;        /* 0xe1c20 - DDR PLL General Status Register */
+        u8      res15[0x3dc];
+} ccsr_clk_t;
+
+typedef struct ccsr_rcpm {
+	u8	res1[4];	/* 0xe2000 - Reserved */
+	u32	cdozsrl;	/* 0xe2004 - Core Doze Status Register */
+	u8	res2[4];	/* 0xe2008 - Reserved */
+	u32	cdozcrl;	/* 0xe200c - Core Doze Control Register */
+	u8	res3[4];	/* 0xe2010 - Reserved */
+	u32	cnapsrl;	/* 0xe2014 - Core Nap Status Register */
+	u8	res4[4];	/* 0xe2018 - Reserved */
+	u32	cnapcrl;	/* 0xe201c - Core Nap Control Register */
+	u8	res5[4];	/* 0xe2020 - Reserved */
+	u32	cdozpsrl;	/* 0xe2024 - Core Doze Previous Status Register */
+	u8	res6[4];	/* 0xe2028 - Reserved */
+	u32	cdozpcrl;	/* 0xe202c - Core Doze Previous Control Register */
+	u8	res7[4];	/* 0xe2030 - Reserved */
+	u32	cwaitsrl;	/* 0xe2034 - Core Wait Status Register */
+	u8	res8[8];	/* Reserved */
+	u32	powmgtcsr;	/* 0xe2040 - Power Mangement Control & Status Register */
+	u8	res9[12];	/* Reserved */
+	u32	ippdexpcr0;	/* 0xe2050 - IP Powerdown Exception Control Register 0 */
+	u8	res10[12];	/* Reserved */
+	u8	res11[4];	/* Reserved */
+	u32	cpmimrl;	/* 0xe2064 - Core Power Management Interrupt Masking Register */
+	u8	res12[4];	/* Reserved */
+	u32	cpmcimrl;	/* 0xe206c - Core Power Management Critical Interrupt Masking Register */
+	u8	res13[4];	/* Reserved */
+	u32	cpmmcimrl;	/* 0xe2074 - Core Power Management Machine Check Interrupt Masking Register */
+	u8	res14[4];	/* Reserved */
+	u32	cpmnmimrl;	/* 0xe207c - Core Power Management NMI Masking Register */
+	u8	res15[4];	/* Reserved */
+	u32	ctbenrl;	/* 0xe2084 - Core Time Base Enable Register */
+	u8	res16[4];	/* Reserved */
+	u32	ctbclkselrl;	/* 0xe208c - Core Time Base Clock Select Register */
+	u8	res17[4];	/* Reserved */
+	u32	ctbhltcrl;	/* 0xe2094 - Core Time Base Halt Control Register */
+	u8	res18[0xf68];
+} ccsr_rcpm_t;
+
+#else
 typedef struct ccsr_gur {
 	uint	porpllsr;	/* 0xe0000 - POR PLL ratio status register */
 #ifdef CONFIG_MPC8536
@@ -1645,42 +1869,65 @@ typedef struct ccsr_gur {
 	uint	tsec34ioovcr;	/* 0xe0f2c - eTSEC 3/4 IO override control */
 	char	res15[61648];	/* 0xe0f30 to 0xefffff */
 } ccsr_gur_t;
+#endif
+
+#ifdef CONFIG_FSL_CORENET
+#define CONFIG_SYS_FSL_CORENET_CCM_OFFSET	0x0000
+#define CONFIG_SYS_MPC85xx_DDR_OFFSET		0x8000
+#define CONFIG_SYS_MPC85xx_DDR2_OFFSET		0x9000
+#define CONFIG_SYS_FSL_CORENET_CLK_OFFSET	0xE1000
+#define CONFIG_SYS_FSL_CORENET_RCPM_OFFSET	0xE2000
+#define CONFIG_SYS_MPC85xx_DMA_OFFSET		0x100000
+#define CONFIG_SYS_MPC85xx_ESPI_OFFSET		0x110000
+#define CONFIG_SYS_MPC85xx_ESDHC_OFFSET		0x114000
+#define CONFIG_SYS_MPC85xx_LBC_OFFSET		0x124000
+#define CONFIG_SYS_MPC85xx_GPIO_OFFSET		0x130000
+#define CONFIG_SYS_MPC85xx_QMAN_OFFSET		0x318000
+#define CONFIG_SYS_MPC85xx_BMAN_OFFSET		0x31a000
+#else
+#define CONFIG_SYS_MPC85xx_ECM_OFFSET		0x0000
+#define CONFIG_SYS_MPC85xx_DDR_OFFSET		0x2000
+#define CONFIG_SYS_MPC85xx_LBC_OFFSET		0x5000
+#define CONFIG_SYS_MPC85xx_DDR2_OFFSET		0x6000
+#define CONFIG_SYS_MPC85xx_ESPI_OFFSET		0x7000
+#define CONFIG_SYS_MPC85xx_PCIX_OFFSET		0x8000
+#define CONFIG_SYS_MPC85xx_PCIX2_OFFSET		0x9000
+#define CONFIG_SYS_MPC85xx_GPIO_OFFSET		0xF000
+#define CONFIG_SYS_MPC85xx_SATA1_OFFSET		0x18000
+#define CONFIG_SYS_MPC85xx_SATA2_OFFSET		0x19000
+#define CONFIG_SYS_MPC85xx_L2_OFFSET		0x20000
+#define CONFIG_SYS_MPC85xx_DMA_OFFSET		0x21000
+#define CONFIG_SYS_MPC85xx_ESDHC_OFFSET		0x2e000
+#define CONFIG_SYS_MPC85xx_SERDES2_OFFSET	0xE3100
+#define CONFIG_SYS_MPC85xx_SERDES1_OFFSET	0xE3000
+#define CONFIG_SYS_MPC85xx_CPM_OFFSET		0x80000
+#endif
+
+#define CONFIG_SYS_MPC85xx_PIC_OFFSET		0x40000
+#define CONFIG_SYS_MPC85xx_GUTS_OFFSET		0xE0000
 
-#define CONFIG_SYS_MPC85xx_GUTS_OFFSET	(0xE0000)
+#define CONFIG_SYS_MPC85xx_QMAN_ADDR	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_QMAN_OFFSET)
+#define CONFIG_SYS_MPC85xx_BMAN_ADDR	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_BMAN_OFFSET)
 #define CONFIG_SYS_MPC85xx_GUTS_ADDR	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GUTS_OFFSET)
-#define CONFIG_SYS_MPC85xx_ECM_OFFSET	(0x0000)
+#define CONFIG_SYS_FSL_CORENET_CCM_ADDR	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_CCM_OFFSET)
+#define CONFIG_SYS_FSL_CORENET_CLK_ADDR	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_CLK_OFFSET)
+#define CONFIG_SYS_FSL_CORENET_RCPM_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_RCPM_OFFSET)
 #define CONFIG_SYS_MPC85xx_ECM_ADDR	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ECM_OFFSET)
-#define CONFIG_SYS_MPC85xx_DDR_OFFSET	(0x2000)
 #define CONFIG_SYS_MPC85xx_DDR_ADDR	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DDR_OFFSET)
-#define CONFIG_SYS_MPC85xx_DDR2_OFFSET	(0x6000)
 #define CONFIG_SYS_MPC85xx_DDR2_ADDR	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DDR2_OFFSET)
-#define CONFIG_SYS_MPC85xx_LBC_OFFSET	(0x5000)
 #define CONFIG_SYS_MPC85xx_LBC_ADDR	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_LBC_OFFSET)
-#define CONFIG_SYS_MPC85xx_ESPI_OFFSET	(0x7000)
 #define CONFIG_SYS_MPC85xx_ESPI_ADDR	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESPI_OFFSET)
-#define CONFIG_SYS_MPC85xx_PCIX_OFFSET	(0x8000)
 #define CONFIG_SYS_MPC85xx_PCIX_ADDR	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX_OFFSET)
-#define CONFIG_SYS_MPC85xx_PCIX2_OFFSET	(0x9000)
 #define CONFIG_SYS_MPC85xx_PCIX2_ADDR	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX2_OFFSET)
-#define CONFIG_SYS_MPC85xx_GPIO_OFFSET	(0xF000)
-#define CONFIG_SYS_MPC85xx_GPIO_ADDR	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GPIO_OFFSET)
-#define CONFIG_SYS_MPC85xx_SATA1_OFFSET	(0x18000)
+#define CONFIG_SYS_MPC85xx_GPIO_ADDR    (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GPIO_OFFSET)
 #define CONFIG_SYS_MPC85xx_SATA1_ADDR	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA1_OFFSET)
-#define CONFIG_SYS_MPC85xx_SATA2_OFFSET	(0x19000)
 #define CONFIG_SYS_MPC85xx_SATA2_ADDR	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA2_OFFSET)
-#define CONFIG_SYS_MPC85xx_L2_OFFSET	(0x20000)
 #define CONFIG_SYS_MPC85xx_L2_ADDR	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_L2_OFFSET)
-#define CONFIG_SYS_MPC85xx_DMA_OFFSET	(0x21000)
 #define CONFIG_SYS_MPC85xx_DMA_ADDR	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DMA_OFFSET)
-#define CONFIG_SYS_MPC85xx_ESDHC_OFFSET	(0x2e000)
 #define CONFIG_SYS_MPC85xx_ESDHC_ADDR	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESDHC_OFFSET)
-#define CONFIG_SYS_MPC85xx_PIC_OFFSET	(0x40000)
 #define CONFIG_SYS_MPC85xx_PIC_ADDR	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PIC_OFFSET)
-#define CONFIG_SYS_MPC85xx_CPM_OFFSET	(0x80000)
 #define CONFIG_SYS_MPC85xx_CPM_ADDR	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_CPM_OFFSET)
-#define CONFIG_SYS_MPC85xx_SERDES1_OFFSET	(0xE3000)
 #define CONFIG_SYS_MPC85xx_SERDES1_ADDR	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET)
-#define CONFIG_SYS_MPC85xx_SERDES2_OFFSET	(0xE3100)
 #define CONFIG_SYS_MPC85xx_SERDES2_ADDR	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET)
 #define CONFIG_SYS_MPC85xx_USB_OFFSET		0x22000
 #define CONFIG_SYS_MPC85xx_USB_ADDR \
-- 
1.6.0.6

[U-Boot] [PATCH v3 2/7] ppc/p4080: Add support for CoreNet style platform LAWs

[Kumar Gala]

On CoreNet based platforms the LAW address is split between an high &
low register and we no longer shift the address.  Also, the target IDs
on CoreNet platforms have been completely re-assigned.

Additionally, added a new find_law() API to which LAW an address hits in.
This is need for the CoreNet style boot release code since it will need
to determine what the target ID should be set to for boot window
translation.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
* Updated based on LAWs being an array

 drivers/misc/fsl_law.c    |   94 ++++++++++++++++++++++++++++++++++++++++++++-
 include/asm-ppc/fsl_law.h |   31 +++++++++++++++
 2 files changed, 123 insertions(+), 2 deletions(-)

diff --git a/drivers/misc/fsl_law.c b/drivers/misc/fsl_law.c
index aa877c6..cbca440 100644
--- a/drivers/misc/fsl_law.c
+++ b/drivers/misc/fsl_law.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2008 Freescale Semiconductor, Inc.
+ * Copyright 2008-2009 Freescale Semiconductor, Inc.
  *
  * (C) Copyright 2000
  * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
@@ -29,7 +29,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define LAWAR_EN	0x80000000
 /* number of LAWs in the hw implementation */
 #if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
     defined(CONFIG_MPC8560) || defined(CONFIG_MPC8555)
@@ -48,6 +47,20 @@ DECLARE_GLOBAL_DATA_PTR;
 
 void set_law(u8 idx, phys_addr_t addr, enum law_size sz, enum law_trgt_if id)
 {
+#ifdef CONFIG_FSL_CORENET
+	volatile ccsr_local_t *ccm = 
+		(void *)(CONFIG_SYS_FSL_CORENET_CCM_ADDR);
+
+	gd->used_laws |= (1 << idx);
+
+	out_be32(&ccm->law[idx].lawar, 0);
+	out_be32(&ccm->law[idx].lawbarh, ((u64)addr >> 32));
+	out_be32(&ccm->law[idx].lawbarl, addr & 0xffffffff);
+	out_be32(&ccm->law[idx].lawar, LAWAR_EN | ((u32)id << 20) | (u32)sz);
+
+	/* Read back so that we sync the writes */
+	in_be32(&ccm->law[idx].lawar);
+#else
 	volatile u32 *base = (volatile u32 *)(CONFIG_SYS_IMMR + 0xc08);
 	volatile u32 *lawbar = base + 8 * idx;
 	volatile u32 *lawar = base + 8 * idx + 2;
@@ -60,6 +73,7 @@ void set_law(u8 idx, phys_addr_t addr, enum law_size sz, enum law_trgt_if id)
 
 	/* Read back so that we sync the writes */
 	in_be32(lawar);
+#endif
 }
 
 int set_next_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id)
@@ -96,6 +110,19 @@ int set_last_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id)
 
 void disable_law(u8 idx)
 {
+#ifdef CONFIG_FSL_CORENET
+	volatile ccsr_local_t *ccm =
+		(void *)(CONFIG_SYS_FSL_CORENET_CCM_ADDR);
+
+	gd->used_laws &= ~(1 << idx);
+
+	out_be32(&ccm->law[idx].lawar, 0);
+	out_be32(&ccm->law[idx].lawbarh, 0);
+	out_be32(&ccm->law[idx].lawbarl, 0);
+
+	/* Read back so that we sync the writes */
+	in_be32(&ccm->law[idx].lawar);
+#else
 	volatile u32 *base = (volatile u32 *)(CONFIG_SYS_IMMR + 0xc08);
 	volatile u32 *lawbar = base + 8 * idx;
 	volatile u32 *lawar = base + 8 * idx + 2;
@@ -105,9 +132,66 @@ void disable_law(u8 idx)
 	out_be32(lawar, 0);
 	out_be32(lawbar, 0);
 
+	/* Read back so that we sync the writes */
+	in_be32(lawar);
+#endif
+
 	return;
 }
 
+#ifdef CONFIG_FSL_CORENET
+#define GET_LAW_ADDR ((u64)in_be32(lawbarh) << 32) | in_be32(lawbarl)
+#else
+#define GET_LAW_ADDR ((u64)in_be32(lawbar) << 12)
+#endif
+
+struct law_entry find_law(phys_addr_t addr)
+{
+	struct law_entry entry;
+	int i;
+
+	entry.index = -1;
+	entry.addr = 0;
+	entry.size = 0;
+	entry.trgt_id = 0;
+
+	for(i = 0; i < FSL_HW_NUM_LAWS; i++) {
+
+		u64 upper;
+		u32 temp;
+#ifdef CONFIG_FSL_CORENET
+		volatile ccsr_local_t *ccm;
+		volatile u32 *lawbarh, *lawbarl, *lawar;
+
+		ccm = (void *)(CONFIG_SYS_FSL_CORENET_CCM_ADDR);
+
+		lawbarh = &ccm->law[i].lawbarh;
+		lawbarl = &ccm->law[i].lawbarl;
+		lawar = &ccm->law[i].lawar;
+#else
+		volatile u32 *base = (volatile u32 *)(CONFIG_SYS_IMMR + 0xc08);
+		volatile u32 *lawbar = base + 8 * i;
+		volatile u32 *lawar = base + 8 * i + 2;
+#endif
+		temp = in_be32(lawar);
+
+		if (!(temp & LAWAR_EN))
+			continue;
+
+		entry.addr = GET_LAW_ADDR;
+		entry.size = temp & 0x3f;
+		entry.trgt_id = (temp >> 20) & 0xff;
+
+		upper = entry.addr + (2ull << entry.size);
+		if ((addr >= entry.addr) && (addr < upper)) {
+			entry.index = i;
+			break;
+		}
+	}
+
+	return entry;
+}
+
 void print_laws(void)
 {
 	volatile u32 *base = (volatile u32 *)(CONFIG_SYS_IMMR + 0xc08);
@@ -173,7 +257,13 @@ void init_laws(void)
 {
 	int i;
 
+#if FSL_HW_NUM_LAWS < 32
 	gd->used_laws = ~((1 << FSL_HW_NUM_LAWS) - 1);
+#elif FSL_HW_NUM_LAWS == 32
+	gd->used_laws = 0;
+#else
+#error FSL_HW_NUM_LAWS can not be greater than 32 w/o code changes
+#endif
 
 	for (i = 0; i < num_law_entries; i++) {
 		if (law_table[i].index == -1)
diff --git a/include/asm-ppc/fsl_law.h b/include/asm-ppc/fsl_law.h
index e06a1a6..f06ede9 100644
--- a/include/asm-ppc/fsl_law.h
+++ b/include/asm-ppc/fsl_law.h
@@ -1,8 +1,18 @@
+/*
+ * Copyright 2008-2009 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
 #ifndef _FSL_LAW_H_
 #define _FSL_LAW_H_
 
 #include <asm/io.h>
 
+#define LAWAR_EN	0x80000000
+
 #define SET_LAW_ENTRY(idx, a, sz, trgt) \
 	{ .index = idx, .addr = a, .size = sz, .trgt_id = trgt }
 
@@ -36,6 +46,25 @@ enum law_size {
 	LAW_SIZE_32G,
 };
 
+#ifdef CONFIG_FSL_CORENET
+enum law_trgt_if {
+	LAW_TRGT_IF_PCIE_1 = 0x00,
+	LAW_TRGT_IF_PCIE_2 = 0x01,
+	LAW_TRGT_IF_PCIE_3 = 0x02,
+	LAW_TRGT_IF_RIO_1 = 0x08,
+	LAW_TRGT_IF_RIO_2 = 0x09,
+
+	LAW_TRGT_IF_DDR_1 = 0x10,
+	LAW_TRGT_IF_DDR_2 = 0x11,	/* 2nd controller */
+	LAW_TRGT_IF_DDR_INTRLV = 0x14,
+
+	LAW_TRGT_IF_BMAN = 0x18,
+	LAW_TRGT_IF_DCSR = 0x1d,
+	LAW_TRGT_IF_LBC = 0x1f,
+	LAW_TRGT_IF_QMAN = 0x3c,
+};
+#define LAW_TRGT_IF_DDR		LAW_TRGT_IF_DDR_1
+#else
 enum law_trgt_if {
 	LAW_TRGT_IF_PCI = 0x00,
 	LAW_TRGT_IF_PCI_2 = 0x01,
@@ -64,6 +93,7 @@ enum law_trgt_if {
 #if defined(CONFIG_MPC8572) || defined(CONFIG_P2020)
 #define LAW_TRGT_IF_PCIE_3	LAW_TRGT_IF_PCI
 #endif
+#endif /* CONFIG_FSL_CORENET */
 
 struct law_entry {
 	int index;
@@ -76,6 +106,7 @@ extern void set_law(u8 idx, phys_addr_t addr, enum law_size sz, enum law_trgt_if
 extern int set_next_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id);
 extern int set_last_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id);
 extern int set_ddr_laws(u64 start, u64 sz, enum law_trgt_if id);
+extern struct law_entry find_law(phys_addr_t addr);
 extern void disable_law(u8 idx);
 extern void init_laws(void);
 extern void print_laws(void);
-- 
1.6.0.6

[U-Boot] [PATCH v3 3/7] ppc/p4080: CoreNet platfrom style CCSRBAR setting

[Kumar Gala]

On CoreNet based platforms the CCSRBAR address is split between an high &
low register and we no longer shift the address.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Scott Wood <scottwood@freescale.com>
---
* Updated based on LAWs being an array

 cpu/mpc85xx/cpu_init_early.c |   29 +++++++++++++++++++++++++++++
 1 files changed, 29 insertions(+), 0 deletions(-)

diff --git a/cpu/mpc85xx/cpu_init_early.c b/cpu/mpc85xx/cpu_init_early.c
index 7886f86..5cd0815 100644
--- a/cpu/mpc85xx/cpu_init_early.c
+++ b/cpu/mpc85xx/cpu_init_early.c
@@ -54,6 +54,9 @@ void cpu_init_early_f(void)
 		u32 temp;
 		volatile u32 *ccsr_virt =
 			(volatile u32 *)(CONFIG_SYS_CCSRBAR + 0x1000);
+#ifdef CONFIG_FSL_CORENET
+		volatile ccsr_local_t *ccm;
+#endif
 
 		mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(1);
 		/* mas1 is the same as above */
@@ -64,9 +67,35 @@ void cpu_init_early_f(void)
 
 		write_tlb(mas0, mas1, mas2, mas3, mas7);
 
+#ifdef CONFIG_FSL_CORENET
+		/*
+		 * We can't call set_law() because we haven't moved
+		 * CCSR yet.
+		 */
+		ccm = (void *)ccsr_virt;
+
+		out_be32(&ccm->law[0].lawbarh,
+			(u64)CONFIG_SYS_CCSRBAR_PHYS >> 32);
+		out_be32(&ccm->law[0].lawbarl, (u32)CONFIG_SYS_CCSRBAR_PHYS);
+		out_be32(&ccm->law[0].lawar,
+			LAWAR_EN | (0x1e << 20) | LAW_SIZE_4K);
+
+		in_be32((u32 *)(ccsr_virt + 0));
+		in_be32((u32 *)(ccsr_virt + 1));
+		isync();
+
+		ccm = (void *)CONFIG_SYS_CCSRBAR;
+		/* Now use the temporary LAW to move CCSR */
+		out_be32(&ccm->ccsrbarh, (u64)CONFIG_SYS_CCSRBAR_PHYS >> 32);
+		out_be32(&ccm->ccsrbarl, (u32)CONFIG_SYS_CCSRBAR_PHYS);
+		out_be32(&ccm->ccsrar, CCSRAR_C);
+		temp = in_be32(&ccm->ccsrar);
+		disable_law(0);
+#else
 		temp = in_be32(ccsr_virt);
 		out_be32(ccsr_virt, CONFIG_SYS_CCSRBAR_PHYS >> 12);
 		temp = in_be32((volatile u32 *)CONFIG_SYS_CCSRBAR);
+#endif
 	}
 #endif
 
-- 
1.6.0.6

[U-Boot] [PATCH v3 4/7] ppc/p4080: CoreNet platfrom style secondary core release

[Kumar Gala]

The CoreNet platform style of bringing secondary cores out of reset is
a bit different that the PQ3 style.  Mostly the registers that we use
to setup boot translation, enable time bases, and boot release the cores
have moved around.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
 cpu/mpc85xx/mp.c |   68 +++++++++++++++++++++++++++++++++++++++++++++++++++++-
 1 files changed, 67 insertions(+), 1 deletions(-)

diff --git a/cpu/mpc85xx/mp.c b/cpu/mpc85xx/mp.c
index fa65bed..b474218 100644
--- a/cpu/mpc85xx/mp.c
+++ b/cpu/mpc85xx/mp.c
@@ -26,6 +26,7 @@
 #include <lmb.h>
 #include <asm/io.h>
 #include <asm/mmu.h>
+#include <asm/fsl_law.h>
 #include "mp.h"
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -135,6 +136,66 @@ ulong get_spin_addr(void)
 	return addr;
 }
 
+#ifdef CONFIG_FSL_CORENET
+static void corenet_mp_up(unsigned long bootpg)
+{
+	u32 up, cpu_up_mask, whoami;
+	u32 *table = (u32 *)get_spin_addr();
+	volatile ccsr_gur_t *gur;
+	volatile ccsr_local_t *ccm;
+	volatile ccsr_rcpm_t *rcpm;
+	volatile ccsr_pic_t *pic;
+	int timeout = 10;
+	u32 nr_cpus;
+	struct law_entry e;
+
+	gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	ccm = (void *)(CONFIG_SYS_FSL_CORENET_CCM_ADDR);
+	rcpm = (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
+	pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR);
+
+	nr_cpus = ((in_be32(&pic->frr) >> 8) & 0xff) + 1;
+
+	whoami = in_be32(&pic->whoami);
+	cpu_up_mask = 1 << whoami;
+	out_be32(&ccm->bstrl, bootpg);
+
+	e = find_law(bootpg);
+	out_be32(&ccm->bstrar, LAWAR_EN | e.trgt_id << 20 | LAWAR_SIZE_4K);
+
+	/* disable time base@the platform */
+	out_be32(&rcpm->ctbenrl, cpu_up_mask);
+
+	/* release the hounds */
+	up = ((1 << nr_cpus) - 1);
+	out_be32(&gur->brrl, up);
+
+	/* wait for everyone */
+	while (timeout) {
+		int i;
+		for (i = 0; i < nr_cpus; i++) {
+			if (table[i * NUM_BOOT_ENTRY + BOOT_ENTRY_ADDR_LOWER])
+				cpu_up_mask |= (1 << i);
+		};
+
+		if ((cpu_up_mask & up) == up)
+			break;
+
+		udelay(100);
+		timeout--;
+	}
+
+	if (timeout == 0)
+		printf("CPU up timeout. CPU up mask is %x should be %x\n",
+			cpu_up_mask, up);
+
+	/* enable time base@the platform */
+	out_be32(&rcpm->ctbenrl, 0);
+	mtspr(SPRN_TBWU, 0);
+	mtspr(SPRN_TBWL, 0);
+	out_be32(&rcpm->ctbenrl, (1 << nr_cpus) - 1);
+}
+#else
 static void pq3_mp_up(unsigned long bootpg)
 {
 	u32 up, cpu_up_mask, whoami;
@@ -196,6 +257,7 @@ static void pq3_mp_up(unsigned long bootpg)
 	devdisr &= ~(MPC85xx_DEVDISR_TB0 | MPC85xx_DEVDISR_TB1);
 	out_be32(&gur->devdisr, devdisr);
 }
+#endif
 
 void cpu_mp_lmb_reserve(struct lmb *lmb)
 {
@@ -217,7 +279,7 @@ void setup_mp(void)
 	if (i != -1) {
 		/* map reset page to bootpg so we can copy code there */
 		disable_tlb(i);
-	
+
 		set_tlb(1, 0xfffff000, bootpg, /* tlb, epn, rpn */
 			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, /* perms, wimge */
 			0, i, BOOKE_PAGESZ_4K, 1); /* ts, esel, tsize, iprot */
@@ -234,7 +296,11 @@ void setup_mp(void)
 			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I, /* perms, wimge */
 			0, i, BOOKE_PAGESZ_4K, 1); /* ts, esel, tsize, iprot */
 
+#ifdef CONFIG_FSL_CORENET
+		corenet_mp_up(bootpg);
+#else
 		pq3_mp_up(bootpg);
+#endif
 	} else {
 		puts("WARNING: No reset page TLB. "
 			"Skipping secondary core setup\n");
-- 
1.6.0.6

[U-Boot] [PATCH v3 5/7] ppc/p4080: Add various p4080 related defines (and p4040)

[Kumar Gala]

There are various locations that we have chip specific info:

* Makefile for which ddr code to build
* Added p4080 & p4040 to cpu_type_list and SVR list
* Added number of LAWs for p4080
* Set CONFIG_MAX_CPUS to 8 for p4080

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
 cpu/mpc85xx/Makefile        |    1 +
 cpu/mpc8xxx/cpu.c           |    4 ++++
 drivers/misc/fsl_law.c      |    2 ++
 include/asm-ppc/config.h    |    6 ++++--
 include/asm-ppc/processor.h |    4 ++++
 5 files changed, 15 insertions(+), 2 deletions(-)

diff --git a/cpu/mpc85xx/Makefile b/cpu/mpc85xx/Makefile
index 3ef00e8..56de7eb 100644
--- a/cpu/mpc85xx/Makefile
+++ b/cpu/mpc85xx/Makefile
@@ -53,6 +53,7 @@ COBJS-$(CONFIG_P1011)	+= ddr-gen3.o
 COBJS-$(CONFIG_P1020)	+= ddr-gen3.o
 COBJS-$(CONFIG_P2010)	+= ddr-gen3.o
 COBJS-$(CONFIG_P2020)	+= ddr-gen3.o
+COBJS-$(CONFIG_PPC_P4080)	+= ddr-gen3.o
 
 COBJS-$(CONFIG_CPM2)	+= ether_fcc.o
 COBJS-$(CONFIG_OF_LIBFDT) += fdt.o
diff --git a/cpu/mpc8xxx/cpu.c b/cpu/mpc8xxx/cpu.c
index 00791e1..d191263 100644
--- a/cpu/mpc8xxx/cpu.c
+++ b/cpu/mpc8xxx/cpu.c
@@ -72,6 +72,10 @@ struct cpu_type cpu_type_list [] = {
 	CPU_TYPE_ENTRY(P2010, P2010_E, 1),
 	CPU_TYPE_ENTRY(P2020, P2020, 2),
 	CPU_TYPE_ENTRY(P2020, P2020_E, 2),
+	CPU_TYPE_ENTRY(P4040, P4040, 4),
+	CPU_TYPE_ENTRY(P4040, P4040_E, 4),
+	CPU_TYPE_ENTRY(P4080, P4080, 8),
+	CPU_TYPE_ENTRY(P4080, P4080_E, 8),
 #elif defined(CONFIG_MPC86xx)
 	CPU_TYPE_ENTRY(8610, 8610, 1),
 	CPU_TYPE_ENTRY(8641, 8641, 2),
diff --git a/drivers/misc/fsl_law.c b/drivers/misc/fsl_law.c
index cbca440..512e81f 100644
--- a/drivers/misc/fsl_law.c
+++ b/drivers/misc/fsl_law.c
@@ -41,6 +41,8 @@ DECLARE_GLOBAL_DATA_PTR;
       defined(CONFIG_P1011) || defined(CONFIG_P1020) || \
       defined(CONFIG_P2010) || defined(CONFIG_P2020)
 #define FSL_HW_NUM_LAWS 12
+#elif defined(CONFIG_PPC_P4080)
+#define FSL_HW_NUM_LAWS 32
 #else
 #error FSL_HW_NUM_LAWS not defined for this platform
 #endif
diff --git a/include/asm-ppc/config.h b/include/asm-ppc/config.h
index 5670d06..e35b0b7 100644
--- a/include/asm-ppc/config.h
+++ b/include/asm-ppc/config.h
@@ -40,9 +40,11 @@
 
 #if defined(CONFIG_MPC8572) || defined(CONFIG_P1020) || \
 	defined(CONFIG_P2020) || defined(CONFIG_MPC8641)
-#define CONFIG_MAX_CPUS        2
+#define CONFIG_MAX_CPUS		2
+#elif defined(CONFIG_PPC_P4080)
+#define CONFIG_MAX_CPUS		8
 #else
-#define CONFIG_MAX_CPUS        1
+#define CONFIG_MAX_CPUS		1
 #endif
 
 #endif /* _ASM_CONFIG_H_ */
diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h
index 3764a5a..d009957 100644
--- a/include/asm-ppc/processor.h
+++ b/include/asm-ppc/processor.h
@@ -1031,6 +1031,10 @@
 #define SVR_P2010_E	0x80EB00
 #define SVR_P2020	0x80E200
 #define SVR_P2020_E	0x80EA00
+#define SVR_P4040	0x820100
+#define SVR_P4040_E	0x820900
+#define SVR_P4080	0x820000
+#define SVR_P4080_E	0x820800
 
 #define SVR_8610	0x80A000
 #define SVR_8641	0x809000
-- 
1.6.0.6

[U-Boot] [PATCH v3 6/7] ppc/p4080: Handle timebase enabling and frequency reporting

[Kumar Gala]

On CoreNet style platforms the timebase frequency is the bus frequency
defined by 16 (on PQ3 it is divide by 8).  Also on the CoreNet platforms
the core not longer controls the enabling of the timebase.  We now need
to enable the boot core's timebase via CCSR register writes.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
* Used get_tbclk() in fdt code to remove #ifdef

 cpu/mpc85xx/cpu.c      |    4 ++++
 cpu/mpc85xx/cpu_init.c |   12 ++++++++++++
 cpu/mpc85xx/fdt.c      |    4 ++--
 3 files changed, 18 insertions(+), 2 deletions(-)

diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c
index bdd9ee4..25c0416 100644
--- a/cpu/mpc85xx/cpu.c
+++ b/cpu/mpc85xx/cpu.c
@@ -184,7 +184,11 @@ int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
  */
 unsigned long get_tbclk (void)
 {
+#ifdef CONFIG_FSL_CORENET
+	return (gd->bus_clk + 8) / 16;
+#else
 	return (gd->bus_clk + 4UL)/8UL;
+#endif
 }
 
 
diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c
index a6d1e99..428b461 100644
--- a/cpu/mpc85xx/cpu_init.c
+++ b/cpu/mpc85xx/cpu_init.c
@@ -229,6 +229,18 @@ void cpu_init_f (void)
 #if defined(CONFIG_FSL_DMA)
 	dma_init();
 #endif
+#ifdef CONFIG_FSL_CORENET
+	{
+		volatile ccsr_rcpm_t *rcpm =
+			(void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
+		volatile ccsr_pic_t *pic =
+			(void *)(CONFIG_SYS_MPC85xx_PIC_ADDR);
+		u32 whoami = in_be32(&pic->whoami);
+
+		/* Enable the timebase register for this core */
+		out_be32(&rcpm->ctbenrl, (1 << whoami));
+	}
+#endif
 }
 
 
diff --git a/cpu/mpc85xx/fdt.c b/cpu/mpc85xx/fdt.c
index 723f473..64a1710 100644
--- a/cpu/mpc85xx/fdt.c
+++ b/cpu/mpc85xx/fdt.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2007 Freescale Semiconductor, Inc.
+ * Copyright 2007-2009 Freescale Semiconductor, Inc.
  *
  * (C) Copyright 2000
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
@@ -287,7 +287,7 @@ void ft_cpu_setup(void *blob, bd_t *bd)
 	fdt_add_enet_stashing(blob);
 
 	do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
-		"timebase-frequency", bd->bi_busfreq / 8, 1);
+		"timebase-frequency", get_tbclk(), 1);
 	do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
 		"bus-frequency", bd->bi_busfreq, 1);
 	get_sys_info(&sysinfo);
-- 
1.6.0.6

[U-Boot] [PATCH v3 7/7] ppc/p4080: Determine various chip frequencies on CoreNet platforms

[Kumar Gala]

The means to determine the core, bus, and DDR frequencies are completely
new on CoreNet style platforms.  Additionally on p4080 we can have
different frequencies for FMAN and PME IP blocks.  We need to keep track
of the FMAN & PME frequencies since they are used for time stamping
capabilities inside each block.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
 cpu/mpc85xx/cpu.c   |   29 +++++++++++++++++
 cpu/mpc85xx/speed.c |   85 +++++++++++++++++++++++++++++++++++++++++++++++++++
 include/e500.h      |    6 +++
 3 files changed, 120 insertions(+), 0 deletions(-)

diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c
index 25c0416..1c0f2b2 100644
--- a/cpu/mpc85xx/cpu.c
+++ b/cpu/mpc85xx/cpu.c
@@ -46,11 +46,20 @@ int checkcpu (void)
 	char buf1[32], buf2[32];
 #ifdef CONFIG_DDR_CLK_FREQ
 	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+#ifdef CONFIG_FSL_CORENET
+	u32 ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC)
+		>> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT;
+#else
 	u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
 		>> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
+#endif
+#else
+#ifdef CONFIG_FSL_CORENET
+	u32 ddr_sync = 0;
 #else
 	u32 ddr_ratio = 0;
 #endif
+#endif
 	int i;
 
 	svr = get_svr();
@@ -111,6 +120,16 @@ int checkcpu (void)
 	}
 	printf("\n       CCB:%-4s MHz,\n", strmhz(buf1, sysinfo.freqSystemBus));
 
+#ifdef CONFIG_FSL_CORENET
+	if (ddr_sync == 1)
+		printf("       DDR:%-4s MHz (%s MT/s data rate) (Synchronous), ",
+			strmhz(buf1, sysinfo.freqDDRBus/2),
+			strmhz(buf2, sysinfo.freqDDRBus));
+	else
+		printf("       DDR:%-4s MHz (%s MT/s data rate) (Asynchronous), ",
+			strmhz(buf1, sysinfo.freqDDRBus/2),
+			strmhz(buf2, sysinfo.freqDDRBus));
+#else
 	switch (ddr_ratio) {
 	case 0x0:
 		printf("       DDR:%-4s MHz (%s MT/s data rate), ",
@@ -128,6 +147,7 @@ int checkcpu (void)
 			strmhz(buf2, sysinfo.freqDDRBus));
 		break;
 	}
+#endif
 
 	if (sysinfo.freqLocalBus > LCRR_CLKDIV)
 		printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus));
@@ -143,6 +163,15 @@ int checkcpu (void)
 	printf("       QE:%-4s MHz\n", strmhz(buf1, sysinfo.freqQE));
 #endif
 
+#ifdef CONFIG_SYS_DPAA_FMAN
+	for (i = 0; i < CONFIG_SYS_NUM_FMAN; i++)
+		printf("       FMAN%d: %s MHz\n", i, strmhz(buf1, sysinfo.freqFMan[i]));
+#endif
+
+#ifdef CONFIG_SYS_DPAA_PME
+	printf("       PME:   %s MHz\n", strmhz(buf1, sysinfo.freqPME));
+#endif
+
 	puts("L1:    D-cache 32 kB enabled\n       I-cache 32 kB enabled\n");
 
 	return 0;
diff --git a/cpu/mpc85xx/speed.c b/cpu/mpc85xx/speed.c
index 2fdcefb..dc18798 100644
--- a/cpu/mpc85xx/speed.c
+++ b/cpu/mpc85xx/speed.c
@@ -1,5 +1,6 @@
 /*
  * Copyright 2004, 2007-2009 Freescale Semiconductor, Inc.
+ *
  * (C) Copyright 2003 Motorola Inc.
  * Xianghua Xiao, (X.Xiao@motorola.com)
  *
@@ -37,6 +38,89 @@ DECLARE_GLOBAL_DATA_PTR;
 void get_sys_info (sys_info_t * sysInfo)
 {
 	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+#ifdef CONFIG_FSL_CORENET
+	volatile ccsr_clk_t *clk = (void *)(CONFIG_SYS_FSL_CORENET_CLK_ADDR);
+
+	const u8 core_cplx_PLL[16] = {
+		[ 0] = 0,	/* CC1 PPL / 1 */
+		[ 1] = 0,	/* CC1 PPL / 2 */
+		[ 2] = 0,	/* CC1 PPL / 4 */
+		[ 4] = 1,	/* CC2 PPL / 1 */
+		[ 5] = 1,	/* CC2 PPL / 2 */
+		[ 6] = 1,	/* CC2 PPL / 4 */
+		[ 8] = 2,	/* CC3 PPL / 1 */
+		[ 9] = 2,	/* CC3 PPL / 2 */
+		[10] = 2,	/* CC3 PPL / 4 */
+		[12] = 3,	/* CC4 PPL / 1 */
+		[13] = 3,	/* CC4 PPL / 2 */
+		[14] = 3,	/* CC4 PPL / 4 */
+	};
+
+	const u8 core_cplx_PLL_div[16] = {
+		[ 0] = 1,	/* CC1 PPL / 1 */
+		[ 1] = 2,	/* CC1 PPL / 2 */
+		[ 2] = 4,	/* CC1 PPL / 4 */
+		[ 4] = 1,	/* CC2 PPL / 1 */
+		[ 5] = 2,	/* CC2 PPL / 2 */
+		[ 6] = 4,	/* CC2 PPL / 4 */
+		[ 8] = 1,	/* CC3 PPL / 1 */
+		[ 9] = 2,	/* CC3 PPL / 2 */
+		[10] = 4,	/* CC3 PPL / 4 */
+		[12] = 1,	/* CC4 PPL / 1 */
+		[13] = 2,	/* CC4 PPL / 2 */
+		[14] = 4,	/* CC4 PPL / 4 */
+	};
+	uint lcrr_div, i, freqCC_PLL[4], rcw_tmp;
+	unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
+
+	sysInfo->freqSystemBus = sysclk;
+	sysInfo->freqDDRBus = sysclk;
+	freqCC_PLL[0] = sysclk;
+	freqCC_PLL[1] = sysclk;
+	freqCC_PLL[2] = sysclk;
+	freqCC_PLL[3] = sysclk;
+
+	sysInfo->freqSystemBus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0xf;
+	sysInfo->freqDDRBus *= ((in_be32(&gur->rcwsr[0]) >> 17) & 0xf);
+	freqCC_PLL[0] *= (in_be32(&clk->pllc1gsr) >> 1) & 0x3f;
+	freqCC_PLL[1] *= (in_be32(&clk->pllc2gsr) >> 1) & 0x3f;
+	freqCC_PLL[2] *= (in_be32(&clk->pllc3gsr) >> 1) & 0x3f;
+	freqCC_PLL[3] *= (in_be32(&clk->pllc4gsr) >> 1) & 0x3f;
+
+	rcw_tmp = in_be32(&gur->rcwsr[3]);
+	for (i = 0; i < cpu_numcores(); i++) {
+		u32 c_pll_sel = (in_be32(&clk->clkc0csr + i*8) >> 27) & 0xf;
+		u32 cplx_pll = core_cplx_PLL[c_pll_sel];
+
+		sysInfo->freqProcessor[i] = freqCC_PLL[cplx_pll] / core_cplx_PLL_div[c_pll_sel];
+	}
+
+#define PME_CLK_SEL	0x80000000
+#define FM1_CLK_SEL	0x40000000
+#define FM2_CLK_SEL	0x20000000
+	rcw_tmp = in_be32(&gur->rcwsr[7]);
+
+#ifdef CONFIG_SYS_DPAA_PME
+	if (rcw_tmp & PME_CLK_SEL)
+		sysInfo->freqPME = freqCC_PLL[2] / 2;
+	else
+		sysInfo->freqPME = sysInfo->freqSystemBus / 2;
+#endif
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+	if (rcw_tmp & FM1_CLK_SEL)
+		sysInfo->freqFMan[0] = freqCC_PLL[2] / 2;
+	else
+		sysInfo->freqFMan[0] = sysInfo->freqSystemBus / 2;
+#if (CONFIG_SYS_NUM_FMAN) == 2
+	if (rcw_tmp & FM2_CLK_SEL)
+		sysInfo->freqFMan[1] = freqCC_PLL[2] / 2;
+	else
+		sysInfo->freqFMan[1] = sysInfo->freqSystemBus / 2;
+#endif
+#endif
+
+#else
 	uint plat_ratio,e500_ratio,half_freqSystemBus;
 	uint lcrr_div;
 	int i;
@@ -67,6 +151,7 @@ void get_sys_info (sys_info_t * sysInfo)
 			sysInfo->freqDDRBus = ddr_ratio * CONFIG_DDR_CLK_FREQ;
 	}
 #endif
+#endif
 
 #ifdef CONFIG_QE
 	qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO)
diff --git a/include/e500.h b/include/e500.h
index f8c8266..e1708b9 100644
--- a/include/e500.h
+++ b/include/e500.h
@@ -15,6 +15,12 @@ typedef struct
   unsigned long freqDDRBus;
   unsigned long freqLocalBus;
   unsigned long freqQE;
+#ifdef CONFIG_SYS_DPAA_FMAN
+  unsigned long freqFMan[CONFIG_SYS_NUM_FMAN];
+#endif
+#ifdef CONFIG_SYS_DPAA_PME
+  unsigned long freqPME;
+#endif
 } MPC85xx_SYS_INFO;
 
 #endif  /* _ASMLANGUAGE */
-- 
1.6.0.6

[U-Boot] [PATCH v3 1/7] ppc/p4080: Add p4080 platform immap definitions

[Wolfgang Denk]

Dear Kumar Gala,

In message <1253376008-13225-1-git-send-email-galak@kernel.crashing.org> you wrote:
> The p4080 SoC has a significant amount of commonality with the 85xx/PQ3
> platform.  We reuse the 85xx immap and just add new definitions for
> local access and global utils.  The global utils is now broken into
> global utils, clocking and run control/power management.
> 
> The offsets from CCSR for a number of blocks have also changed.  We
> introduce the CONFIG_FSL_CORENET define to distinquish the PQ3 style of
> platform from the new p4080 platform.  We don't use QoirQ as there are
> products (like p2020) that are PQ3 based platforms but have the QoirQ
> name.
> 
> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
...
> +typedef struct ccsr_local {
> +	u32	ccsrbarh;	/* 0x0 - Control Configuration Status Registers Base Address Register High */
> +	u32	ccsrbarl;	/* 0x4 - Control Configuration Status Registers Base Address Register Low */
> +	u32	ccsrar;		/* 0x8 - Configuration, Control, and Status Attribute Register */

Lines too long. Please check globally.


Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Microsoft Compatibility:
     your old Windows 3.11 application crash exactly as the new ones.

[U-Boot] [PATCH v3 2/7] ppc/p4080: Add support for CoreNet style platform LAWs

[Wolfgang Denk]

Dear Kumar Gala,

In message <1253376008-13225-2-git-send-email-galak@kernel.crashing.org> you wrote:
> On CoreNet based platforms the LAW address is split between an high &
> low register and we no longer shift the address.  Also, the target IDs
> on CoreNet platforms have been completely re-assigned.
> 
> Additionally, added a new find_law() API to which LAW an address hits in.
> This is need for the CoreNet style boot release code since it will need
> to determine what the target ID should be set to for boot window
> translation.
> 
> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
...
>  void set_law(u8 idx, phys_addr_t addr, enum law_size sz, enum law_trgt_if id)
>  {
> +#ifdef CONFIG_FSL_CORENET
> +	volatile ccsr_local_t *ccm = 
> +		(void *)(CONFIG_SYS_FSL_CORENET_CCM_ADDR);
> +
> +	gd->used_laws |= (1 << idx);
> +
> +	out_be32(&ccm->law[idx].lawar, 0);
> +	out_be32(&ccm->law[idx].lawbarh, ((u64)addr >> 32));
> +	out_be32(&ccm->law[idx].lawbarl, addr & 0xffffffff);
> +	out_be32(&ccm->law[idx].lawar, LAWAR_EN | ((u32)id << 20) | (u32)sz);
> +
> +	/* Read back so that we sync the writes */
> +	in_be32(&ccm->law[idx].lawar);
> +#else
>  	volatile u32 *base = (volatile u32 *)(CONFIG_SYS_IMMR + 0xc08);
>  	volatile u32 *lawbar = base + 8 * idx;
>  	volatile u32 *lawar = base + 8 * idx + 2;

Now we have variable declarations after code (ok, #ifdef'ed code, but
anyway). Please don't do that.  Please check everywhere.

>  
...
> +struct law_entry find_law(phys_addr_t addr)
> +{
> +	struct law_entry entry;
> +	int i;
> +
> +	entry.index = -1;
> +	entry.addr = 0;
> +	entry.size = 0;
> +	entry.trgt_id = 0;
> +
> +	for(i = 0; i < FSL_HW_NUM_LAWS; i++) {
> +

Please add a space after the "for", and drop the empty line.


Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Conceptual integrity in turn dictates that the  design  must  proceed
from  one  mind,  or  from  a  very small number of agreeing resonant
minds.               - Frederick Brooks Jr., "The Mythical Man Month"