[U-Boot] [PATCH-V2 5/9] fec_mxc: cleanup and factor out MX27 dependencies

[John Rigby <jcrigby@gmail.com>]

general cleanup
move clock init to cpu_eth_init in cpu/arm926ejs/mx27/generic.c
make MX27 specific phy init conditional on CONFIG_MX27
replace call to imx_get_ahbclk with one to imx_get_fecclk
and define imx_get_fecclk in include/asm-arm/arch-mx27/clock.h

Signed-off-by: John Rigby <jcrigby@gmail.com>
CC: Ben Warren <biggerbadderben@gmail.com>
CC: Fred Fan <fanyefeng@gmail.com>
CC: Tom <Tom.Rix@windriver.com>

---
 cpu/arm926ejs/mx27/generic.c      |    5 +++++
 drivers/net/fec_mxc.c             |   28 +++++++++++++---------------
 include/asm-arm/arch-mx27/clock.h |    1 +
 3 files changed, 19 insertions(+), 15 deletions(-)

diff --git a/cpu/arm926ejs/mx27/generic.c b/cpu/arm926ejs/mx27/generic.c
index da05c55..30cf544 100644
--- a/cpu/arm926ejs/mx27/generic.c
+++ b/cpu/arm926ejs/mx27/generic.c
@@ -166,6 +166,11 @@ int print_cpuinfo (void)
 int cpu_eth_init(bd_t *bis)
 {
 #if defined(CONFIG_FEC_MXC)
+	struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
+
+	/* enable FEC clock */
+	writel(readl(&pll->pccr1) | PCCR1_HCLK_FEC, &pll->pccr1);
+	writel(readl(&pll->pccr0) | PCCR0_FEC_EN, &pll->pccr0);
 	return fecmxc_initialize(bis);
 #else
 	return 0;
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index 19116f2..b5619eb 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -151,7 +151,9 @@ static int miiphy_restart_aneg(struct eth_device *dev)
 	 * Wake up from sleep if necessary
 	 * Reset PHY, then delay 300ns
 	 */
+#ifdef CONFIG_MX27
 	miiphy_write(dev->name, CONFIG_FEC_MXC_PHYADDR, PHY_MIPGSR, 0x00FF);
+#endif
 	miiphy_write(dev->name, CONFIG_FEC_MXC_PHYADDR, PHY_BMCR,
 			PHY_BMCR_RESET);
 	udelay(1000);
@@ -343,7 +345,8 @@ static int fec_open(struct eth_device *edev)
 	/*
 	 * Enable FEC-Lite controller
 	 */
-	writel(FEC_ECNTRL_ETHER_EN, &fec->eth->ecntrl);
+	writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_ETHER_EN,
+		&fec->eth->ecntrl);
 
 	miiphy_wait_aneg(edev);
 	miiphy_speed(edev->name, CONFIG_FEC_MXC_PHYADDR);
@@ -415,10 +418,10 @@ static int fec_init(struct eth_device *dev, bd_t* bd)
 		 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
 		 * and do not drop the Preamble.
 		 */
-		writel((((imx_get_ahbclk() / 1000000) + 2) / 5) << 1,
+		writel((((imx_get_fecclk() / 1000000) + 2) / 5) << 1,
 				&fec->eth->mii_speed);
 		debug("fec_init: mii_speed %#lx\n",
-				(((imx_get_ahbclk() / 1000000) + 2) / 5) << 1);
+				(((imx_get_fecclk() / 1000000) + 2) / 5) << 1);
 	}
 	/*
 	 * Set Opcode/Pause Duration Register
@@ -475,7 +478,7 @@ static void fec_halt(struct eth_device *dev)
 	/*
 	 * issue graceful stop command to the FEC transmitter if necessary
 	 */
-	writel(FEC_ECNTRL_RESET | readl(&fec->eth->x_cntrl),
+	writel(FEC_TCNTRL_GTS | readl(&fec->eth->x_cntrl),
 			&fec->eth->x_cntrl);
 
 	debug("eth_halt: wait for stop regs\n");
@@ -483,7 +486,7 @@ static void fec_halt(struct eth_device *dev)
 	 * wait for graceful stop to register
 	 */
 	while ((counter--) && (!(readl(&fec->eth->ievent) & FEC_IEVENT_GRA)))
-		;	/* FIXME ensure time */
+		udelay(1);
 
 	/*
 	 * Disable SmartDMA tasks
@@ -495,7 +498,7 @@ static void fec_halt(struct eth_device *dev)
 	 * Disable the Ethernet Controller
 	 * Note: this will also reset the BD index counter!
 	 */
-	writel(0, &fec->eth->ecntrl);
+	writel(readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_ETHER_EN, &fec->eth->ecntrl);
 	fec->rbd_index = 0;
 	fec->tbd_index = 0;
 	debug("eth_halt: done\n");
@@ -554,7 +557,7 @@ static int fec_send(struct eth_device *dev, volatile void* packet, int length)
 	 * wait until frame is sent .
 	 */
 	while (readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_READY) {
-		/* FIXME: Timeout */
+		udelay(1);
 	}
 	debug("fec_send: status 0x%x index %d\n",
 			readw(&fec->tbd_base[fec->tbd_index].status),
@@ -651,7 +654,6 @@ static int fec_recv(struct eth_device *dev)
 
 static int fec_probe(bd_t *bd)
 {
-	struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
 	struct eth_device *edev;
 	struct fec_priv *fec = &gfec;
 	unsigned char ethaddr_str[20];
@@ -659,10 +661,6 @@ static int fec_probe(bd_t *bd)
 	char *tmp = getenv("ethaddr");
 	char *end;
 
-	/* enable FEC clock */
-	writel(readl(&pll->pccr1) | PCCR1_HCLK_FEC, &pll->pccr1);
-	writel(readl(&pll->pccr0) | PCCR0_FEC_EN, &pll->pccr0);
-
 	/* create and fill edev struct */
 	edev = (struct eth_device *)malloc(sizeof(struct eth_device));
 	if (!edev) {
@@ -681,7 +679,7 @@ static int fec_probe(bd_t *bd)
 	fec->xcv_type = MII100;
 
 	/* Reset chip. */
-	writel(FEC_ECNTRL_RESET, &fec->eth->ecntrl);
+	writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_RESET, &fec->eth->ecntrl);
 	while (readl(&fec->eth->ecntrl) & 1)
 		udelay(10);
 
@@ -706,10 +704,10 @@ static int fec_probe(bd_t *bd)
 	 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
 	 * and do not drop the Preamble.
 	 */
-	writel((((imx_get_ahbclk() / 1000000) + 2) / 5) << 1,
+	writel((((imx_get_fecclk() / 1000000) + 2) / 5) << 1,
 			&fec->eth->mii_speed);
 	debug("fec_init: mii_speed %#lx\n",
-			(((imx_get_ahbclk() / 1000000) + 2) / 5) << 1);
+			(((imx_get_fecclk() / 1000000) + 2) / 5) << 1);
 
 	sprintf(edev->name, "FEC_MXC");
 
diff --git a/include/asm-arm/arch-mx27/clock.h b/include/asm-arm/arch-mx27/clock.h
index 472e8f2..7e9c7aa 100644
--- a/include/asm-arm/arch-mx27/clock.h
+++ b/include/asm-arm/arch-mx27/clock.h
@@ -37,5 +37,6 @@ ulong imx_get_perclk3(void);
 ulong imx_get_ahbclk(void);
 
 #define imx_get_uartclk imx_get_perclk1
+#define imx_get_fecclk imx_get_ahbclk
 
 #endif /* __ASM_ARCH_CLOCK_H */
-- 
1.6.4.2.236.gf324c