[U-Boot] [PATCH v3 6/6] arm: mvf600: Add basic support for Vybrid MVF600TWR board

[U-Boot] [PATCH v3 6/6] arm: mvf600: Add basic support for Vybrid MVF600TWR board

[Alison Wang]

MVF600TWR is a board based on Vybrid MVF600 SoC.

This patch adds basic support for Vybrid MVF600TWR board.

Signed-off-by: Alison Wang <b18965@freescale.com>
Signed-off-by: Jason Jin <Jason.jin@freescale.com>
Signed-off-by: TsiChung Liew <tsicliew@gmail.com>
---
Changes in v3:
- Replace BOOT_FROM by BOOT_OFFSET
- Enable CONFIG_OF_LIBFDT option
- Add useful define instead of raw number
- Use clrsetbits_le32 to set the single bits
- Move setup_iomux_enet() to board_early_init_f and remove board_eth_init()
- Remove redundant define
- Move CONFIG_IOMUX_SHARE_CONF_REG to imx-regs.h

Changes in v2:
- Add an entry to MAINTAINERS file
- Rename directory name 'vybird' to 'mvf600twr'
- Use standard method to set gd->ram_size
- Rewrite board_mmc_getcd() function
- Remove useless undef
- Remove hardcoded IP addresses and MAC addresses
- Remove useless CONFIG_SYS_ defines
- Define C structures and access C structures to set/read registers
- Move CONFIG_MACH_TYPE to board configuration file
- Use common iomux-v3 code

 MAINTAINERS                            |   4 +
 board/freescale/mvf600twr/Makefile     |  39 ++++
 board/freescale/mvf600twr/imximage.cfg |  33 +++
 board/freescale/mvf600twr/mvf600twr.c  | 413 +++++++++++++++++++++++++++++++++
 boards.cfg                             |   1 +
 include/configs/mvf600twr.h            | 140 +++++++++++
 6 files changed, 630 insertions(+)
 create mode 100644 board/freescale/mvf600twr/Makefile
 create mode 100644 board/freescale/mvf600twr/imximage.cfg
 create mode 100644 board/freescale/mvf600twr/mvf600twr.c
 create mode 100644 include/configs/mvf600twr.h

diff --git a/MAINTAINERS b/MAINTAINERS
index c05433a..d32ac66 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1057,6 +1057,10 @@ Eric Nelson <eric.nelson@boundarydevices.com>
 	nitrogen6s		i.MX6S		512MB
 	nitrogen6s1g		i.MX6S		1GB
 
+Alison Wang <b18965@freescale.com>
+
+	mvf600twr	MVF600
+
 -------------------------------------------------------------------------
 
 Unknown / orphaned boards:
diff --git a/board/freescale/mvf600twr/Makefile b/board/freescale/mvf600twr/Makefile
new file mode 100644
index 0000000..7416228
--- /dev/null
+++ b/board/freescale/mvf600twr/Makefile
@@ -0,0 +1,39 @@
+#
+# Copyright 2013 Freescale Semiconductor, Inc.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= $(BOARD).o
+
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/freescale/mvf600twr/imximage.cfg b/board/freescale/mvf600twr/imximage.cfg
new file mode 100644
index 0000000..b00d4c1
--- /dev/null
+++ b/board/freescale/mvf600twr/imximage.cfg
@@ -0,0 +1,33 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not write to the Free Software
+ * Foundation Inc. 51 Franklin Street Fifth Floor Boston,
+ * MA 02110-1301 USA
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+#include <asm/imx-common/imximage.cfg>
+
+/* image version */
+IMAGE_VERSION	2
+
+/* Boot Offset 0x400, valid for both SD and NAND boot */
+BOOT_OFFSET	FLASH_OFFSET_STANDARD
diff --git a/board/freescale/mvf600twr/mvf600twr.c b/board/freescale/mvf600twr/mvf600twr.c
new file mode 100644
index 0000000..71ee12b
--- /dev/null
+++ b/board/freescale/mvf600twr/mvf600twr.c
@@ -0,0 +1,413 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/mvf_pins.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/clock.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <miiphy.h>
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL	(PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+			PAD_CTL_DSE_25ohm | PAD_CTL_OBE_IBE_ENABLE)
+
+#define ESDHC_PAD_CTRL	(PAD_CTL_PUE | PAD_CTL_PUS_100K_UP | \
+			PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_20ohm | \
+			PAD_CTL_OBE_IBE_ENABLE)
+
+#define ENET_PAD_CTRL	(PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH | \
+			PAD_CTL_DSE_50ohm | PAD_CTL_OBE_IBE_ENABLE)
+
+#define DDR_PAD_CTRL	PAD_CTL_DSE_25ohm
+
+iomux_v3_cfg_t const ddr_pads[] = {
+	MVF600_PAD_DDR_A15__DDR_A_15 | MUX_PAD_CTRL(DDR_PAD_CTRL),
+	MVF600_PAD_DDR_A14__DDR_A_14 | MUX_PAD_CTRL(DDR_PAD_CTRL),
+	MVF600_PAD_DDR_A13__DDR_A_13 | MUX_PAD_CTRL(DDR_PAD_CTRL),
+	MVF600_PAD_DDR_A12__DDR_A_12 | MUX_PAD_CTRL(DDR_PAD_CTRL),
+	MVF600_PAD_DDR_A11__DDR_A_11 | MUX_PAD_CTRL(DDR_PAD_CTRL),
+	MVF600_PAD_DDR_A10__DDR_A_10 | MUX_PAD_CTRL(DDR_PAD_CTRL),
+	MVF600_PAD_DDR_A9__DDR_A_9 | MUX_PAD_CTRL(DDR_PAD_CTRL),
+	MVF600_PAD_DDR_A8__DDR_A_8 | MUX_PAD_CTRL(DDR_PAD_CTRL),
+	MVF600_PAD_DDR_A7__DDR_A_7 | MUX_PAD_CTRL(DDR_PAD_CTRL),
+	MVF600_PAD_DDR_A6__DDR_A_6 | MUX_PAD_CTRL(DDR_PAD_CTRL),
+	MVF600_PAD_DDR_A5__DDR_A_5 | MUX_PAD_CTRL(DDR_PAD_CTRL),
+	MVF600_PAD_DDR_A4__DDR_A_4 | MUX_PAD_CTRL(DDR_PAD_CTRL),
+	MVF600_PAD_DDR_A3__DDR_A_3 | MUX_PAD_CTRL(DDR_PAD_CTRL),
+	MVF600_PAD_DDR_A2__DDR_A_2 | MUX_PAD_CTRL(DDR_PAD_CTRL),
+	MVF600_PAD_DDR_A1__DDR_A_1 | MUX_PAD_CTRL(DDR_PAD_CTRL),
+	MVF600_PAD_DDR_BA2__DDR_BA_2 | MUX_PAD_CTRL(DDR_PAD_CTRL),
+	MVF600_PAD_DDR_BA1__DDR_BA_1 | MUX_PAD_CTRL(DDR_PAD_CTRL),
+	MVF600_PAD_DDR_BA0__DDR_BA_0 | MUX_PAD_CTRL(DDR_PAD_CTRL),
+	MVF600_PAD_DDR_CAS__DDR_CAS_B | MUX_PAD_CTRL(DDR_PAD_CTRL),
+	MVF600_PAD_DDR_CKE__DDR_CKE_0 | MUX_PAD_CTRL(DDR_PAD_CTRL),
+	MVF600_PAD_DDR_CLK__DDR_CLK_0 | MUX_PAD_CTRL(DDR_PAD_CTRL),
+	MVF600_PAD_DDR_CS__DDR_CS_B_0 | MUX_PAD_CTRL(DDR_PAD_CTRL),
+	MVF600_PAD_DDR_D15__DDR_D_15 | MUX_PAD_CTRL(DDR_PAD_CTRL),
+	MVF600_PAD_DDR_D14__DDR_D_14 | MUX_PAD_CTRL(DDR_PAD_CTRL),
+	MVF600_PAD_DDR_D13__DDR_D_13 | MUX_PAD_CTRL(DDR_PAD_CTRL),
+	MVF600_PAD_DDR_D12__DDR_D_12 | MUX_PAD_CTRL(DDR_PAD_CTRL),
+	MVF600_PAD_DDR_D11__DDR_D_11 | MUX_PAD_CTRL(DDR_PAD_CTRL),
+	MVF600_PAD_DDR_D10__DDR_D_10 | MUX_PAD_CTRL(DDR_PAD_CTRL),
+	MVF600_PAD_DDR_D9__DDR_D_9 | MUX_PAD_CTRL(DDR_PAD_CTRL),
+	MVF600_PAD_DDR_D8__DDR_D_8 | MUX_PAD_CTRL(DDR_PAD_CTRL),
+	MVF600_PAD_DDR_D7__DDR_D_7 | MUX_PAD_CTRL(DDR_PAD_CTRL),
+	MVF600_PAD_DDR_D6__DDR_D_6 | MUX_PAD_CTRL(DDR_PAD_CTRL),
+	MVF600_PAD_DDR_D5__DDR_D_5 | MUX_PAD_CTRL(DDR_PAD_CTRL),
+	MVF600_PAD_DDR_D4__DDR_D_4 | MUX_PAD_CTRL(DDR_PAD_CTRL),
+	MVF600_PAD_DDR_D3__DDR_D_3 | MUX_PAD_CTRL(DDR_PAD_CTRL),
+	MVF600_PAD_DDR_D2__DDR_D_2 | MUX_PAD_CTRL(DDR_PAD_CTRL),
+	MVF600_PAD_DDR_D1__DDR_D_1 | MUX_PAD_CTRL(DDR_PAD_CTRL),
+	MVF600_PAD_DDR_D0__DDR_D_0 | MUX_PAD_CTRL(DDR_PAD_CTRL),
+	MVF600_PAD_DDR_DQM1__DDR_DQM_1 | MUX_PAD_CTRL(DDR_PAD_CTRL),
+	MVF600_PAD_DDR_DQM0__DDR_DQM_0 | MUX_PAD_CTRL(DDR_PAD_CTRL),
+	MVF600_PAD_DDR_DQS1__DDR_DQS_1 | MUX_PAD_CTRL(DDR_PAD_CTRL),
+	MVF600_PAD_DDR_DQS0__DDR_DQS_0 | MUX_PAD_CTRL(DDR_PAD_CTRL),
+	MVF600_PAD_DDR_RAS__DDR_RAS_B | MUX_PAD_CTRL(DDR_PAD_CTRL),
+	MVF600_PAD_DDR_WE__DDR_WE_B | MUX_PAD_CTRL(DDR_PAD_CTRL),
+	MVF600_PAD_DDR_ODT1__DDR_ODT_0 | MUX_PAD_CTRL(DDR_PAD_CTRL),
+	MVF600_PAD_DDR_ODT0__DDR_ODT_1 | MUX_PAD_CTRL(DDR_PAD_CTRL),
+};
+
+iomux_v3_cfg_t const uart1_pads[] = {
+	MVF600_PAD_PTB4__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MVF600_PAD_PTB5__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+iomux_v3_cfg_t const enet0_pads[] = {
+	MVF600_PAD_PTA6__RMII0_CLKIN | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MVF600_PAD_PTC1__RMII0_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MVF600_PAD_PTC0__RMII0_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MVF600_PAD_PTC2__RMII0_CRS_DV | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MVF600_PAD_PTC3__RMII0_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MVF600_PAD_PTC4__RMII0_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MVF600_PAD_PTC5__RMII0_RXER | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MVF600_PAD_PTC6__RMII0_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MVF600_PAD_PTC7__RMII0_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MVF600_PAD_PTC8__RMII0_TXEN | MUX_PAD_CTRL(ENET_PAD_CTRL),
+};
+
+iomux_v3_cfg_t const esdhc1_pads[] = {
+	MVF600_PAD_PTA24__ESDHC1_CLK | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	MVF600_PAD_PTA25__ESDHC1_CMD | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	MVF600_PAD_PTA26__ESDHC1_DAT0 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	MVF600_PAD_PTA27__ESDHC1_DAT1 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	MVF600_PAD_PTA28__ESDHC1_DAT2 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	MVF600_PAD_PTA29__ESDHC1_DAT3 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+};
+
+void setup_iomux_ddr(void)
+{
+	imx_iomux_v3_setup_multiple_pads(ddr_pads, ARRAY_SIZE(ddr_pads));
+}
+
+void ddr_phy_init(void)
+{
+	struct ddrmr_regs *ddrmr = (struct ddrmr_regs *)DDR_BASE_ADDR;
+
+	writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[0]);
+	writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[16]);
+	writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[32]);
+	writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[48]);
+
+	writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[1]);
+	writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[17]);
+	writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[33]);
+	writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[49]);
+
+	writel(DDRMC_PHY_CTRL, &ddrmr->phy[2]);
+	writel(DDRMC_PHY_CTRL, &ddrmr->phy[18]);
+	writel(DDRMC_PHY_CTRL, &ddrmr->phy[34]);
+	writel(DDRMC_PHY_CTRL, &ddrmr->phy[50]);
+
+	writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[3]);
+	writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[19]);
+	writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[35]);
+	writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[51]);
+
+	writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[4]);
+	writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[20]);
+	writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[36]);
+	writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[52]);
+
+	writel(DDRMC_PHY50_DDR3_MODE | DDRMC_PHY50_EN_SW_HALF_CYCLE,
+		&ddrmr->phy[50]);
+}
+
+void ddr_ctrl_init(void)
+{
+	struct ddrmr_regs *ddrmr = (struct ddrmr_regs *)DDR_BASE_ADDR;
+
+	writel(DDRMC_CR00_DRAM_CLASS_DDR3, &ddrmr->cr[0]);
+	writel(DDRMC_CR02_DRAM_TINIT(32), &ddrmr->cr[2]);
+	writel(DDRMC_CR10_TRST_PWRON(124), &ddrmr->cr[10]);
+
+	writel(DDRMC_CR11_CKE_INACTIVE(80000), &ddrmr->cr[11]);
+	writel(DDRMC_CR12_WRLAT(5) | DDRMC_CR12_CASLAT_LIN(12), &ddrmr->cr[12]);
+	writel(DDRMC_CR13_TRC(21) | DDRMC_CR13_TRRD(4) | DDRMC_CR13_TCCD(4) |
+		DDRMC_CR13_TBST_INT_INTERVAL(4), &ddrmr->cr[13]);
+	writel(DDRMC_CR14_TFAW(20) | DDRMC_CR14_TRP(6) | DDRMC_CR14_TWTR(4) |
+		DDRMC_CR14_TRAS_MIN(15), &ddrmr->cr[14]);
+	writel(DDRMC_CR16_TMRD(4) | DDRMC_CR16_TRTP(4), &ddrmr->cr[16]);
+	writel(DDRMC_CR17_TRAS_MAX(28080) | DDRMC_CR17_TMOD(12),
+		&ddrmr->cr[17]);
+	writel(DDRMC_CR18_TCKESR(4) | DDRMC_CR18_TCKE(3), &ddrmr->cr[18]);
+
+	writel(DDRMC_CR20_AP_EN, &ddrmr->cr[20]);
+	writel(DDRMC_CR21_TRCD_INT(6) | DDRMC_CR21_TRAS_LOCKOUT |
+		DDRMC_CR21_CCMAP_EN, &ddrmr->cr[21]);
+
+	writel(DDRMC_CR22_TDAL(11), &ddrmr->cr[22]);
+	writel(DDRMC_CR23_BSTLEN(3) | DDRMC_CR23_TDLL(512), &ddrmr->cr[23]);
+	writel(DDRMC_CR24_TRP_AB(6), &ddrmr->cr[24]);
+
+	writel(DDRMC_CR25_TREF_EN, &ddrmr->cr[25]);
+	writel(DDRMC_CR26_TREF(3112) | DDRMC_CR26_TRFC(44), &ddrmr->cr[26]);
+	writel(DDRMC_CR28_TREF_INT(5), &ddrmr->cr[28]);
+	writel(DDRMC_CR29_TPDEX(3), &ddrmr->cr[29]);
+
+	writel(DDRMC_CR30_TXPDLL(10), &ddrmr->cr[30]);
+	writel(DDRMC_CR31_TXSNR(68) | DDRMC_CR31_TXSR(512), &ddrmr->cr[31]);
+	writel(DDRMC_CR33_EN_QK_SREF, &ddrmr->cr[33]);
+	writel(DDRMC_CR34_CKSRX(5) | DDRMC_CR34_CKSRE(5), &ddrmr->cr[34]);
+
+	writel(DDRMC_CR38_FREQ_CHG_EN, &ddrmr->cr[38]);
+	writel(DDRMC_CR39_PHY_INI_COM(1024) | DDRMC_CR39_PHY_INI_STA(16) |
+		DDRMC_CR39_FRQ_CH_DLLOFF(2), &ddrmr->cr[39]);
+
+	writel(DDRMC_CR41_PHY_INI_STRT_INI_DIS, &ddrmr->cr[41]);
+	writel(DDRMC_CR48_MR1_DA_0(70) | DDRMC_CR48_MR0_DA_0(1056),
+		&ddrmr->cr[48]);
+
+	writel(DDRMC_CR66_ZQCL(256) | DDRMC_CR66_ZQINIT(512), &ddrmr->cr[66]);
+	writel(DDRMC_CR67_ZQCS(64), &ddrmr->cr[67]);
+	writel(DDRMC_CR69_ZQ_ON_SREF_EX(2), &ddrmr->cr[69]);
+
+	writel(DDRMC_CR70_REF_PER_ZQ(64), &ddrmr->cr[70]);
+	writel(DDRMC_CR72_ZQCS_ROTATE, &ddrmr->cr[72]);
+
+	writel(DDRMC_CR73_APREBIT(10) | DDRMC_CR73_COL_DIFF(1) |
+		DDRMC_CR73_ROW_DIFF(3), &ddrmr->cr[73]);
+	writel(DDRMC_CR74_BANKSPLT_EN | DDRMC_CR74_ADDR_CMP_EN |
+		DDRMC_CR74_CMD_AGE_CNT(255) | DDRMC_CR74_AGE_CNT(255),
+		&ddrmr->cr[74]);
+	writel(DDRMC_CR75_RW_PG_EN | DDRMC_CR75_RW_EN | DDRMC_CR75_PRI_EN |
+		DDRMC_CR75_PLEN, &ddrmr->cr[75]);
+	writel(DDRMC_CR76_NQENT_ACTDIS(3) | DDRMC_CR76_D_RW_G_BKCN(3) |
+		DDRMC_CR76_W2R_SPLT_EN | DDRMC_CR76_CS_EN, &ddrmr->cr[76]);
+	writel(DDRMC_CR77_CS_MAP | DDRMC_CR77_DI_RD_INTLEAVE |
+		DDRMC_CR77_SWAP_EN, &ddrmr->cr[77]);
+	writel(DDRMC_CR78_BUR_ON_FLY_BIT(12), &ddrmr->cr[78]);
+	writel(DDRMC_CR79_CTLUPD_AREF, &ddrmr->cr[79]);
+
+	writel(DDRMC_CR82_INT_MASK, &ddrmr->cr[82]);
+
+	writel(DDRMC_CR87_ODT_WR_MAPCS0 | DDRMC_CR87_ODT_RD_MAPCS0,
+		&ddrmr->cr[87]);
+	writel(DDRMC_CR88_TODTL_CMD(4), &ddrmr->cr[88]);
+	writel(DDRMC_CR89_AODT_RWSMCS(2), &ddrmr->cr[89]);
+
+	writel(DDRMC_CR91_R2W_SMCSDL(2), &ddrmr->cr[91]);
+	writel(DDRMC_CR96_WLMRD(40) | DDRMC_CR96_WLDQSEN(25), &ddrmr->cr[96]);
+
+	writel(DDRMC_CR105_RDLVL_DL_0(32), &ddrmr->cr[105]);
+	writel(DDRMC_CR110_RDLVL_DL_1(32), &ddrmr->cr[110]);
+	writel(DDRMC_CR114_RDLVL_GTDL_2(8224), &ddrmr->cr[114]);
+
+	writel(DDRMC_CR117_AXI0_W_PRI(1) | DDRMC_CR117_AXI0_R_PRI(1),
+		&ddrmr->cr[117]);
+	writel(DDRMC_CR118_AXI1_W_PRI(1) | DDRMC_CR118_AXI1_R_PRI(1),
+		&ddrmr->cr[118]);
+
+	writel(DDRMC_CR120_AXI0_PRI1_RPRI(2) | DDRMC_CR120_AXI0_PRI0_RPRI(2),
+		&ddrmr->cr[120]);
+	writel(DDRMC_CR121_AXI0_PRI3_RPRI(2) | DDRMC_CR121_AXI0_PRI2_RPRI(2),
+		&ddrmr->cr[121]);
+	writel(DDRMC_CR122_AXI1_PRI1_RPRI(1) | DDRMC_CR122_AXI1_PRI0_RPRI(1) |
+		DDRMC_CR122_AXI0_PRIRLX(100), &ddrmr->cr[122]);
+	writel(DDRMC_CR123_AXI1_PRI3_RPRI(1) | DDRMC_CR123_AXI1_PRI2_RPRI(1),
+		&ddrmr->cr[123]);
+	writel(DDRMC_CR124_AXI1_PRIRLX(100), &ddrmr->cr[124]);
+
+	writel(DDRMC_CR126_PHY_RDLAT(11), &ddrmr->cr[126]);
+	writel(DDRMC_CR132_WRLAT_ADJ(5) | DDRMC_CR132_RDLAT_ADJ(6),
+		&ddrmr->cr[132]);
+	writel(DDRMC_CR139_PHY_WRLV_RESPLAT(4) | DDRMC_CR139_PHY_WRLV_LOAD(7) |
+		DDRMC_CR139_PHY_WRLV_DLL(3) | DDRMC_CR139_PHY_WRLV_EN(3),
+		&ddrmr->cr[139]);
+
+	writel(DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(13) |
+		DDRMC_CR154_PAD_ZQ_MODE(1), &ddrmr->cr[154]);
+	writel(DDRMC_CR155_AXI0_AWCACHE | DDRMC_CR155_PAD_ODT_BYTE1(2),
+		&ddrmr->cr[155]);
+	writel(DDRMC_CR158_TWR(6), &ddrmr->cr[158]);
+
+	ddr_phy_init();
+
+	writel(DDRMC_CR00_DRAM_CLASS_DDR3 | DDRMC_CR00_START, &ddrmr->cr[0]);
+
+	udelay(200);
+}
+
+int dram_init(void)
+{
+	setup_iomux_ddr();
+
+	ddr_ctrl_init();
+	gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
+
+	return 0;
+}
+
+static void setup_iomux_uart(void)
+{
+	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+}
+
+static void setup_iomux_enet(void)
+{
+	imx_iomux_v3_setup_multiple_pads(enet0_pads, ARRAY_SIZE(enet0_pads));
+}
+
+#ifdef CONFIG_FSL_ESDHC
+struct fsl_esdhc_cfg esdhc_cfg[1] = {
+	{ESDHC1_BASE_ADDR},
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	/* eSDHC1 is always present */
+	return 1;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+	s32 status = 0;
+
+	esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+
+	imx_iomux_v3_setup_multiple_pads(
+		esdhc1_pads, ARRAY_SIZE(esdhc1_pads));
+
+	status |= fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
+
+	return status;
+}
+#endif
+
+static void clock_init(void)
+{
+	struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
+	struct anadig_reg *anadig = (struct anadig_reg *)ANADIG_BASE_ADDR;
+
+	clrsetbits_le32(&ccm->ccgr0, CCM_REG_CTRL_MASK,
+		CCM_CCGR0_UART1_CTRL_MASK);
+	clrsetbits_le32(&ccm->ccgr1, CCM_REG_CTRL_MASK,
+		CCM_CCGR1_PIT_CTRL_MASK | CCM_CCGR1_WDOGA5_CTRL_MASK);
+	clrsetbits_le32(&ccm->ccgr2, CCM_REG_CTRL_MASK,
+		CCM_CCGR2_IOMUXC_CTRL_MASK | CCM_CCGR2_PORTA_CTRL_MASK |
+		CCM_CCGR2_PORTB_CTRL_MASK | CCM_CCGR2_PORTC_CTRL_MASK |
+		CCM_CCGR2_PORTD_CTRL_MASK | CCM_CCGR2_PORTE_CTRL_MASK);
+	clrsetbits_le32(&ccm->ccgr3, CCM_REG_CTRL_MASK,
+		CCM_CCGR3_ANADIG_CTRL_MASK);
+	clrsetbits_le32(&ccm->ccgr4, CCM_REG_CTRL_MASK,
+		CCM_CCGR4_WKUP_CTRL_MASK | CCM_CCGR4_CCM_CTRL_MASK |
+		CCM_CCGR4_GPC_CTRL_MASK);
+	clrsetbits_le32(&ccm->ccgr6, CCM_REG_CTRL_MASK,
+		CCM_CCGR6_OCOTP_CTRL_MASK | CCM_CCGR6_DDRMC_CTRL_MASK);
+	clrsetbits_le32(&ccm->ccgr7, CCM_REG_CTRL_MASK,
+		CCM_CCGR7_SDHC1_CTRL_MASK);
+	clrsetbits_le32(&ccm->ccgr9, CCM_REG_CTRL_MASK,
+		CCM_CCGR9_FEC0_CTRL_MASK | CCM_CCGR9_FEC1_CTRL_MASK);
+
+	clrsetbits_le32(&anadig->pll2_ctrl, ANADIG_PLL2_CTRL_POWERDOWN,
+		ANADIG_PLL2_CTRL_ENABLE | ANADIG_PLL2_CTRL_DIV_SELECT);
+	clrsetbits_le32(&anadig->pll1_ctrl, ANADIG_PLL1_CTRL_POWERDOWN,
+		ANADIG_PLL1_CTRL_ENABLE | ANADIG_PLL1_CTRL_DIV_SELECT);
+
+	clrsetbits_le32(&ccm->ccr, CCM_CCR_OSCNT_MASK,
+		CCM_CCR_FIRC_EN | CCM_CCR_OSCNT(5));
+	clrsetbits_le32(&ccm->ccsr, CCM_REG_CTRL_MASK,
+		CCM_CCSR_PLL1_PFD_CLK_SEL(3) | CCM_CCSR_PLL2_PFD4_EN |
+		CCM_CCSR_PLL2_PFD3_EN | CCM_CCSR_PLL2_PFD2_EN |
+		CCM_CCSR_PLL2_PFD1_EN | CCM_CCSR_PLL1_PFD4_EN |
+		CCM_CCSR_PLL1_PFD3_EN | CCM_CCSR_PLL1_PFD2_EN |
+		CCM_CCSR_PLL1_PFD1_EN | CCM_CCSR_DDRC_CLK_SEL(1) |
+		CCM_CCSR_FAST_CLK_SEL(1) | CCM_CCSR_SYS_CLK_SEL(4));
+	clrsetbits_le32(&ccm->cacrr, CCM_REG_CTRL_MASK,
+		CCM_CACRR_IPG_CLK_DIV(1) | CCM_CACRR_BUS_CLK_DIV(2) |
+		CCM_CACRR_ARM_CLK_DIV(0));
+	clrsetbits_le32(&ccm->cscmr1, CCM_REG_CTRL_MASK,
+		CCM_CSCMR1_ESDHC1_CLK_SEL(3));
+	clrsetbits_le32(&ccm->cscdr1, CCM_REG_CTRL_MASK,
+		CCM_CSCDR1_RMII_CLK_EN);
+	clrsetbits_le32(&ccm->cscdr2, CCM_REG_CTRL_MASK,
+		CCM_CSCDR2_ESDHC1_EN | CCM_CSCDR2_ESDHC1_CLK_DIV(0));
+	clrsetbits_le32(&ccm->cscmr2, CCM_REG_CTRL_MASK,
+		CCM_CSCMR2_RMII_CLK_SEL(0));
+}
+
+static void mscm_init(void)
+{
+	struct mscm_ir *mscmir = (struct mscm_ir *)MSCM_IR_BASE_ADDR;
+	int i;
+
+	for (i = 0; i < MSCM_IRSPRC_NUM; i++)
+		writew(MSCM_IRSPRC_CP0_EN, &mscmir->irsprc[i]);
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+
+	return 0;
+}
+
+int board_early_init_f(void)
+{
+	clock_init();
+	mscm_init();
+
+	setup_iomux_uart();
+	setup_iomux_enet();
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	puts("Board: mvf600twr\n");
+
+	return 0;
+}
diff --git a/boards.cfg b/boards.cfg
index 2f39f26..60c1920 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -262,6 +262,7 @@ mx6qsabrelite                arm         armv7       mx6qsabrelite       freesca
 mx6qsabresd                  arm         armv7       mx6qsabresd         freescale      mx6		mx6qsabresd:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
 mx6slevk                     arm         armv7       mx6slevk            freescale      mx6		mx6slevk:IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg,MX6SL
 titanium                     arm         armv7       titanium            freescale      mx6		titanium:IMX_CONFIG=board/freescale/titanium/imximage.cfg
+mvf600twr                    arm         armv7       mvf600twr           freescale      mvf600          mvf600twr:IMX_CONFIG=board/freescale/mvf600twr/imximage.cfg
 eco5pk                       arm         armv7       eco5pk              8dtech         omap3
 nitrogen6dl                  arm         armv7       nitrogen6x          boundary       mx6		nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL,DDR_MB=1024
 nitrogen6dl2g                arm         armv7       nitrogen6x          boundary       mx6		nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl2g.cfg,MX6DL,DDR_MB=2048
diff --git a/include/configs/mvf600twr.h b/include/configs/mvf600twr.h
new file mode 100644
index 0000000..1cfb9f6
--- /dev/null
+++ b/include/configs/mvf600twr.h
@@ -0,0 +1,140 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the Freescale Vybrid mvf600twr board.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/imx-regs.h>
+#include <config_cmd_default.h>
+
+#define CONFIG_MVF600
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define CONFIG_MACH_TYPE		4146
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+/* Enable passing of ATAGs */
+#define CONFIG_CMDLINE_TAG
+
+#define CONFIG_CMD_FUSE
+#ifdef CONFIG_CMD_FUSE
+#define CONFIG_MXC_OCOTP
+#endif
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 2 * 1024 * 1024)
+
+#define CONFIG_BOARD_EARLY_INIT_F
+
+#define CONFIG_FSL_LPUART
+#define LPUART_BASE			UART1_BASE
+
+/* Allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_SYS_UART_PORT		(1)
+#define CONFIG_BAUDRATE			115200
+
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR	0
+#define CONFIG_SYS_FSL_ESDHC_NUM	1
+
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_FEC_MXC
+#define CONFIG_MII
+#define IMX_FEC_BASE			ENET_BASE_ADDR
+#define CONFIG_FEC_XCV_TYPE		RMII
+#define CONFIG_ETHPRIME			"FEC"
+#define CONFIG_FEC_MXC_PHYADDR          0
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_MICREL
+
+#define CONFIG_BOOTDELAY		3
+
+#define CONFIG_SYS_TEXT_BASE		0x3f008000
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_PROMPT		"Vybrid U-Boot > "
+#undef CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE		\
+			(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+
+#define CONFIG_SYS_MEMTEST_START	0x80010000
+#define CONFIG_SYS_MEMTEST_END		0x87C00000
+
+#define CONFIG_SYS_LOAD_ADDR		0x80010000
+
+#define CONFIG_SYS_HZ			1000
+
+/*
+ * Stack sizes
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE		(128 * 1024)	/* regular stack */
+
+/* Physical memory map */
+#define CONFIG_NR_DRAM_BANKS		1
+#define PHYS_SDRAM			(0x80000000)
+#define PHYS_SDRAM_SIZE			(128 * 1024 * 1024)
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* FLASH and environment organization */
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_ENV_SIZE			(8 * 1024)
+#define CONFIG_ENV_IS_IN_MMC
+
+#define CONFIG_ENV_OFFSET		(12 * 64 * 1024)
+#define CONFIG_SYS_MMC_ENV_DEV		0
+
+#define CONFIG_OF_LIBFDT
+#define CONFIG_CMD_BOOTZ
+
+#endif
-- 
1.8.0

[U-Boot] [PATCH v3 6/6] arm: mvf600: Add basic support for Vybrid MVF600TWR board

[Benoît Thébaudeau]

Hi Alison,

On Tuesday, May 21, 2013 11:03:01 AM, Alison Wang wrote:
> MVF600TWR is a board based on Vybrid MVF600 SoC.
> 
> This patch adds basic support for Vybrid MVF600TWR board.
> 
> Signed-off-by: Alison Wang <b18965@freescale.com>
> Signed-off-by: Jason Jin <Jason.jin@freescale.com>
> Signed-off-by: TsiChung Liew <tsicliew@gmail.com>

[...]

> diff --git a/include/configs/mvf600twr.h b/include/configs/mvf600twr.h
> new file mode 100644
> index 0000000..1cfb9f6
> --- /dev/null
> +++ b/include/configs/mvf600twr.h
> @@ -0,0 +1,140 @@
> +/*
> + * Copyright 2013 Freescale Semiconductor, Inc.
> + *
> + * Configuration settings for the Freescale Vybrid mvf600twr board.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#ifndef __CONFIG_H
> +#define __CONFIG_H
> +
> +#include <asm/arch/imx-regs.h>
> +#include <config_cmd_default.h>
> +
> +#define CONFIG_MVF600
> +

[...]

> +#define CONFIG_CMD_PING
> +#define CONFIG_CMD_DHCP
> +#define CONFIG_CMD_MII
> +#define CONFIG_CMD_NET
> +#define CONFIG_FEC_MXC
> +#define CONFIG_MII
> +#define IMX_FEC_BASE			ENET_BASE_ADDR
> +#define CONFIG_FEC_XCV_TYPE		RMII
> +#define CONFIG_ETHPRIME			"FEC"

You don't need to define this one with only 1 Ethernet interface defined. But
isn't the MVF600 a dual-Ethernet SoC?

> +#define CONFIG_FEC_MXC_PHYADDR          0
> +#define CONFIG_PHYLIB
> +#define CONFIG_PHY_MICREL
> +
> +#define CONFIG_BOOTDELAY		3
> +
> +#define CONFIG_SYS_TEXT_BASE		0x3f008000
> +
> +/* Miscellaneous configurable options */
> +#define CONFIG_SYS_LONGHELP		/* undef to save memory */
> +#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
> +#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
> +#define CONFIG_SYS_PROMPT		"Vybrid U-Boot > "
> +#undef CONFIG_AUTO_COMPLETE
> +#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
> +#define CONFIG_SYS_PBSIZE		\
> +			(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
> +#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
> +#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
> +
> +#define CONFIG_SYS_MEMTEST_START	0x80010000
> +#define CONFIG_SYS_MEMTEST_END		0x87C00000

You now have to #define CONFIG_CMD_MEMTEST for those to be useful.

> +
> +#define CONFIG_SYS_LOAD_ADDR		0x80010000
> +
> +#define CONFIG_SYS_HZ			1000
> +
> +/*
> + * Stack sizes
> + * The stack sizes are set up in start.S using the settings below
> + */
> +#define CONFIG_STACKSIZE		(128 * 1024)	/* regular stack */
> +
> +/* Physical memory map */
> +#define CONFIG_NR_DRAM_BANKS		1
> +#define PHYS_SDRAM			(0x80000000)
> +#define PHYS_SDRAM_SIZE			(128 * 1024 * 1024)
> +
> +#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
> +#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
> +#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
> +
> +#define CONFIG_SYS_INIT_SP_OFFSET \
> +	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
> +#define CONFIG_SYS_INIT_SP_ADDR \
> +	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
> +
> +/* FLASH and environment organization */
> +#define CONFIG_SYS_NO_FLASH
> +
> +#define CONFIG_ENV_SIZE			(8 * 1024)
> +#define CONFIG_ENV_IS_IN_MMC
> +
> +#define CONFIG_ENV_OFFSET		(12 * 64 * 1024)
> +#define CONFIG_SYS_MMC_ENV_DEV		0
> +
> +#define CONFIG_OF_LIBFDT
> +#define CONFIG_CMD_BOOTZ
> +
> +#endif
> --
> 1.8.0

Best regards,
Beno?t

[U-Boot] [PATCH v3 6/6] arm: mvf600: Add basic support for Vybrid MVF600TWR board

[Benoît Thébaudeau]

Hi Alison,

On Tuesday, May 21, 2013 11:03:01 AM, Alison Wang wrote:
> MVF600TWR is a board based on Vybrid MVF600 SoC.
> 
> This patch adds basic support for Vybrid MVF600TWR board.
> 
> Signed-off-by: Alison Wang <b18965@freescale.com>
> Signed-off-by: Jason Jin <Jason.jin@freescale.com>
> Signed-off-by: TsiChung Liew <tsicliew@gmail.com>

[...]

> diff --git a/board/freescale/mvf600twr/mvf600twr.c
> b/board/freescale/mvf600twr/mvf600twr.c
> new file mode 100644
> index 0000000..71ee12b
> --- /dev/null
> +++ b/board/freescale/mvf600twr/mvf600twr.c
> @@ -0,0 +1,413 @@
> +/*
> + * Copyright 2013 Freescale Semiconductor, Inc.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#include <common.h>
> +#include <asm/io.h>
> +#include <asm/arch/imx-regs.h>
> +#include <asm/arch/mvf_pins.h>
> +#include <asm/arch/crm_regs.h>
> +#include <asm/arch/clock.h>
> +#include <mmc.h>
> +#include <fsl_esdhc.h>
> +#include <miiphy.h>
> +#include <netdev.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +#define UART_PAD_CTRL	(PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
> +			PAD_CTL_DSE_25ohm | PAD_CTL_OBE_IBE_ENABLE)
> +
> +#define ESDHC_PAD_CTRL	(PAD_CTL_PUE | PAD_CTL_PUS_100K_UP | \
> +			PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_20ohm | \
> +			PAD_CTL_OBE_IBE_ENABLE)

With the changes that I have suggested in my review of your IOMUX patch,
ESDHC_PAD_CTRL could be simplified by removing PAD_CTL_PUE.

And without those changes, UART_PAD_CTRL and ENET_PAD_CTRL in your current code
set pull values that are actually unused (unless the corresponding PKE/PUE bits
do not exist and default to pull in the pad control registers used with these
definitions).

> +
> +#define ENET_PAD_CTRL	(PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH | \
> +			PAD_CTL_DSE_50ohm | PAD_CTL_OBE_IBE_ENABLE)
> +
> +#define DDR_PAD_CTRL	PAD_CTL_DSE_25ohm

MUX_PAD_CTRL() could be added to the 4 pad control definitions above in order to
avoid repeating it everywhere below. But using MUX_PAD_CTRL() relies on the fact
that the pad control values in mvf_pins.h are all 0 (which is the case, but this
is dangerous if this is changed later), so a better approach could be to use
NEW_PAD_CTRL(), e.g.:
        NEW_PAD_CTRL(MVF600_PAD_DDR_A15__DDR_A_15, DDR_PAD_CTRL),
instead of:
        MVF600_PAD_DDR_A15__DDR_A_15 | MUX_PAD_CTRL(DDR_PAD_CTRL),

> +
> +iomux_v3_cfg_t const ddr_pads[] = {
> +	MVF600_PAD_DDR_A15__DDR_A_15 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> +	MVF600_PAD_DDR_A14__DDR_A_14 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> +	MVF600_PAD_DDR_A13__DDR_A_13 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> +	MVF600_PAD_DDR_A12__DDR_A_12 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> +	MVF600_PAD_DDR_A11__DDR_A_11 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> +	MVF600_PAD_DDR_A10__DDR_A_10 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> +	MVF600_PAD_DDR_A9__DDR_A_9 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> +	MVF600_PAD_DDR_A8__DDR_A_8 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> +	MVF600_PAD_DDR_A7__DDR_A_7 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> +	MVF600_PAD_DDR_A6__DDR_A_6 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> +	MVF600_PAD_DDR_A5__DDR_A_5 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> +	MVF600_PAD_DDR_A4__DDR_A_4 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> +	MVF600_PAD_DDR_A3__DDR_A_3 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> +	MVF600_PAD_DDR_A2__DDR_A_2 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> +	MVF600_PAD_DDR_A1__DDR_A_1 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> +	MVF600_PAD_DDR_BA2__DDR_BA_2 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> +	MVF600_PAD_DDR_BA1__DDR_BA_1 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> +	MVF600_PAD_DDR_BA0__DDR_BA_0 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> +	MVF600_PAD_DDR_CAS__DDR_CAS_B | MUX_PAD_CTRL(DDR_PAD_CTRL),
> +	MVF600_PAD_DDR_CKE__DDR_CKE_0 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> +	MVF600_PAD_DDR_CLK__DDR_CLK_0 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> +	MVF600_PAD_DDR_CS__DDR_CS_B_0 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> +	MVF600_PAD_DDR_D15__DDR_D_15 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> +	MVF600_PAD_DDR_D14__DDR_D_14 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> +	MVF600_PAD_DDR_D13__DDR_D_13 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> +	MVF600_PAD_DDR_D12__DDR_D_12 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> +	MVF600_PAD_DDR_D11__DDR_D_11 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> +	MVF600_PAD_DDR_D10__DDR_D_10 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> +	MVF600_PAD_DDR_D9__DDR_D_9 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> +	MVF600_PAD_DDR_D8__DDR_D_8 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> +	MVF600_PAD_DDR_D7__DDR_D_7 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> +	MVF600_PAD_DDR_D6__DDR_D_6 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> +	MVF600_PAD_DDR_D5__DDR_D_5 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> +	MVF600_PAD_DDR_D4__DDR_D_4 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> +	MVF600_PAD_DDR_D3__DDR_D_3 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> +	MVF600_PAD_DDR_D2__DDR_D_2 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> +	MVF600_PAD_DDR_D1__DDR_D_1 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> +	MVF600_PAD_DDR_D0__DDR_D_0 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> +	MVF600_PAD_DDR_DQM1__DDR_DQM_1 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> +	MVF600_PAD_DDR_DQM0__DDR_DQM_0 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> +	MVF600_PAD_DDR_DQS1__DDR_DQS_1 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> +	MVF600_PAD_DDR_DQS0__DDR_DQS_0 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> +	MVF600_PAD_DDR_RAS__DDR_RAS_B | MUX_PAD_CTRL(DDR_PAD_CTRL),
> +	MVF600_PAD_DDR_WE__DDR_WE_B | MUX_PAD_CTRL(DDR_PAD_CTRL),
> +	MVF600_PAD_DDR_ODT1__DDR_ODT_0 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> +	MVF600_PAD_DDR_ODT0__DDR_ODT_1 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> +};
> +
> +iomux_v3_cfg_t const uart1_pads[] = {
> +	MVF600_PAD_PTB4__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
> +	MVF600_PAD_PTB5__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
> +};
> +
> +iomux_v3_cfg_t const enet0_pads[] = {
> +	MVF600_PAD_PTA6__RMII0_CLKIN | MUX_PAD_CTRL(ENET_PAD_CTRL),
> +	MVF600_PAD_PTC1__RMII0_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
> +	MVF600_PAD_PTC0__RMII0_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
> +	MVF600_PAD_PTC2__RMII0_CRS_DV | MUX_PAD_CTRL(ENET_PAD_CTRL),
> +	MVF600_PAD_PTC3__RMII0_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
> +	MVF600_PAD_PTC4__RMII0_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
> +	MVF600_PAD_PTC5__RMII0_RXER | MUX_PAD_CTRL(ENET_PAD_CTRL),
> +	MVF600_PAD_PTC6__RMII0_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
> +	MVF600_PAD_PTC7__RMII0_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
> +	MVF600_PAD_PTC8__RMII0_TXEN | MUX_PAD_CTRL(ENET_PAD_CTRL),
> +};
> +
> +iomux_v3_cfg_t const esdhc1_pads[] = {
> +	MVF600_PAD_PTA24__ESDHC1_CLK | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
> +	MVF600_PAD_PTA25__ESDHC1_CMD | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
> +	MVF600_PAD_PTA26__ESDHC1_DAT0 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
> +	MVF600_PAD_PTA27__ESDHC1_DAT1 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
> +	MVF600_PAD_PTA28__ESDHC1_DAT2 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
> +	MVF600_PAD_PTA29__ESDHC1_DAT3 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
> +};

[...]

Best regards,
Beno?t

[U-Boot] [PATCH v3 6/6] arm: mvf600: Add basic support for Vybrid MVF600TWR board

[Wang Huan-B18965]

Hi, Benoit,

On Tuesday, May 21, 2013 11:03:01 AM, Alison Wang wrote:
> MVF600TWR is a board based on Vybrid MVF600 SoC.
>
> This patch adds basic support for Vybrid MVF600TWR board.
>
> Signed-off-by: Alison Wang <b18965@freescale.com>
> Signed-off-by: Jason Jin <Jason.jin@freescale.com>
> Signed-off-by: TsiChung Liew <tsicliew@gmail.com>

[...]

> diff --git a/include/configs/mvf600twr.h b/include/configs/mvf600twr.h
> new file mode 100644
> index 0000000..1cfb9f6
> --- /dev/null
> +++ b/include/configs/mvf600twr.h
> @@ -0,0 +1,140 @@
> +/*
> + * Copyright 2013 Freescale Semiconductor, Inc.
> + *
> + * Configuration settings for the Freescale Vybrid mvf600twr board.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.      See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#ifndef __CONFIG_H
> +#define __CONFIG_H
> +
> +#include <asm/arch/imx-regs.h>
> +#include <config_cmd_default.h>
> +
> +#define CONFIG_MVF600
> +

[...]

> +#define CONFIG_CMD_PING
> +#define CONFIG_CMD_DHCP
> +#define CONFIG_CMD_MII
> +#define CONFIG_CMD_NET
> +#define CONFIG_FEC_MXC
> +#define CONFIG_MII
> +#define IMX_FEC_BASE                 ENET_BASE_ADDR
> +#define CONFIG_FEC_XCV_TYPE          RMII
> +#define CONFIG_ETHPRIME                      "FEC"

You don't need to define this one with only 1 Ethernet interface defined. But
isn't the MVF600 a dual-Ethernet SoC?
[Alison Wang] Yes, MVF600 is a dual-Ethernet SoC. I will change it to "FEC0".

> +#define CONFIG_FEC_MXC_PHYADDR          0
> +#define CONFIG_PHYLIB
> +#define CONFIG_PHY_MICREL
> +
> +#define CONFIG_BOOTDELAY             3
> +
> +#define CONFIG_SYS_TEXT_BASE         0x3f008000
> +
> +/* Miscellaneous configurable options */
> +#define CONFIG_SYS_LONGHELP          /* undef to save memory */
> +#define CONFIG_SYS_HUSH_PARSER               /* use "hush" command parser */
> +#define CONFIG_SYS_PROMPT_HUSH_PS2   "> "
> +#define CONFIG_SYS_PROMPT            "Vybrid U-Boot > "
> +#undef CONFIG_AUTO_COMPLETE
> +#define CONFIG_SYS_CBSIZE            256     /* Console I/O Buffer Size */
> +#define CONFIG_SYS_PBSIZE            \
> +                     (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
> +#define CONFIG_SYS_MAXARGS           16      /* max number of command args */
> +#define CONFIG_SYS_BARGSIZE          CONFIG_SYS_CBSIZE
> +
> +#define CONFIG_SYS_MEMTEST_START     0x80010000
> +#define CONFIG_SYS_MEMTEST_END               0x87C00000

You now have to #define CONFIG_CMD_MEMTEST for those to be useful.
[Alison Wang] OK. Thanks.

> +
> +#define CONFIG_SYS_LOAD_ADDR         0x80010000
> +
> +#define CONFIG_SYS_HZ                        1000
> +
> +/*
> + * Stack sizes
> + * The stack sizes are set up in start.S using the settings below
> + */
> +#define CONFIG_STACKSIZE             (128 * 1024)    /* regular stack */
> +
> +/* Physical memory map */
> +#define CONFIG_NR_DRAM_BANKS         1
> +#define PHYS_SDRAM                   (0x80000000)
> +#define PHYS_SDRAM_SIZE                      (128 * 1024 * 1024)
> +
> +#define CONFIG_SYS_SDRAM_BASE                PHYS_SDRAM
> +#define CONFIG_SYS_INIT_RAM_ADDR     IRAM_BASE_ADDR
> +#define CONFIG_SYS_INIT_RAM_SIZE     IRAM_SIZE
> +
> +#define CONFIG_SYS_INIT_SP_OFFSET \
> +     (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
> +#define CONFIG_SYS_INIT_SP_ADDR \
> +     (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
> +
> +/* FLASH and environment organization */
> +#define CONFIG_SYS_NO_FLASH
> +
> +#define CONFIG_ENV_SIZE                      (8 * 1024)
> +#define CONFIG_ENV_IS_IN_MMC
> +
> +#define CONFIG_ENV_OFFSET            (12 * 64 * 1024)
> +#define CONFIG_SYS_MMC_ENV_DEV               0
> +
> +#define CONFIG_OF_LIBFDT
> +#define CONFIG_CMD_BOOTZ
> +
> +#endif
> --
> 1.8.0

Best regards,
Alison Wang

[U-Boot] [PATCH v3 6/6] arm: mvf600: Add basic support for Vybrid MVF600TWR board

[Wang Huan-B18965]

Hi, Benoit,

> 
> On Tuesday, May 21, 2013 11:03:01 AM, Alison Wang wrote:
> > MVF600TWR is a board based on Vybrid MVF600 SoC.
> >
> > This patch adds basic support for Vybrid MVF600TWR board.
> >
> > Signed-off-by: Alison Wang <b18965@freescale.com>
> > Signed-off-by: Jason Jin <Jason.jin@freescale.com>
> > Signed-off-by: TsiChung Liew <tsicliew@gmail.com>
> 
> [...]
> 
> > diff --git a/board/freescale/mvf600twr/mvf600twr.c
> > b/board/freescale/mvf600twr/mvf600twr.c
> > new file mode 100644
> > index 0000000..71ee12b
> > --- /dev/null
> > +++ b/board/freescale/mvf600twr/mvf600twr.c
> > @@ -0,0 +1,413 @@
> > +/*
> > + * Copyright 2013 Freescale Semiconductor, Inc.
> > + *
> > + * This program is free software; you can redistribute it and/or
> > + * modify it under the terms of the GNU General Public License as
> > + * published by the Free Software Foundation; either version 2 of
> > + * the License, or (at your option) any later version.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> > + * GNU General Public License for more details.
> > + *
> > + * You should have received a copy of the GNU General Public License
> > + * along with this program; if not, write to the Free Software
> > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> > + * MA 02111-1307 USA
> > + */
> > +
> > +#include <common.h>
> > +#include <asm/io.h>
> > +#include <asm/arch/imx-regs.h>
> > +#include <asm/arch/mvf_pins.h>
> > +#include <asm/arch/crm_regs.h>
> > +#include <asm/arch/clock.h>
> > +#include <mmc.h>
> > +#include <fsl_esdhc.h>
> > +#include <miiphy.h>
> > +#include <netdev.h>
> > +
> > +DECLARE_GLOBAL_DATA_PTR;
> > +
> > +#define UART_PAD_CTRL	(PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED
> | \
> > +			PAD_CTL_DSE_25ohm | PAD_CTL_OBE_IBE_ENABLE)
> > +
> > +#define ESDHC_PAD_CTRL	(PAD_CTL_PUE | PAD_CTL_PUS_100K_UP | \
> > +			PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_20ohm | \
> > +			PAD_CTL_OBE_IBE_ENABLE)
> 
> With the changes that I have suggested in my review of your IOMUX patch,
> ESDHC_PAD_CTRL could be simplified by removing PAD_CTL_PUE.
> 
> And without those changes, UART_PAD_CTRL and ENET_PAD_CTRL in your
> current code set pull values that are actually unused (unless the
> corresponding PKE/PUE bits do not exist and default to pull in the pad
> control registers used with these definitions).
[Alison Wang] Agree.
> 
> > +
> > +#define ENET_PAD_CTRL	(PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH
> | \
> > +			PAD_CTL_DSE_50ohm | PAD_CTL_OBE_IBE_ENABLE)
> > +
> > +#define DDR_PAD_CTRL	PAD_CTL_DSE_25ohm
> 
> MUX_PAD_CTRL() could be added to the 4 pad control definitions above in
> order to avoid repeating it everywhere below. But using MUX_PAD_CTRL()
> relies on the fact that the pad control values in mvf_pins.h are all 0
> (which is the case, but this is dangerous if this is changed later), so
> a better approach could be to use NEW_PAD_CTRL(), e.g.:
>         NEW_PAD_CTRL(MVF600_PAD_DDR_A15__DDR_A_15, DDR_PAD_CTRL),
> instead of:
>         MVF600_PAD_DDR_A15__DDR_A_15 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> 
> > +
[Alison Wang] I have a question about using NEW_PAD_CTRL(). If NEW_PAD_CTRL()
is used, should the pad control values for MVF600_PAD_DDR_A15__DDR_A_15 in mvf_pins.h
be the same as DDR_PAD_CTRL? I saw you didn't use the same value on other platforms,
how do you define it?

Best Regards,
Alison Wang

[U-Boot] [PATCH v3 6/6] arm: mvf600: Add basic support for Vybrid MVF600TWR board

[Benoît Thébaudeau]

Hi Alison,

On Wednesday, May 22, 2013 5:17:41 AM, Wang Huan-B18965 wrote:
> Hi, Benoit,
> 
> > -----Original Message-----
> > From: Beno?t Th?baudeau [mailto:benoit.thebaudeau at advansee.com]
> > Sent: Wednesday, May 22, 2013 1:29 AM
> > To: Wang Huan-B18965
> > Cc: sbabic at denx.de; u-boot at lists.denx.de; TsiChung Liew; Jin Zhengxiong-
> > R64188; Estevam Fabio-R49496
> > Subject: Re: [U-Boot] [PATCH v3 6/6] arm: mvf600: Add basic support for
> > Vybrid MVF600TWR board
> > 
> > Hi Alison,
> > 
> > On Tuesday, May 21, 2013 11:03:01 AM, Alison Wang wrote:
> > > MVF600TWR is a board based on Vybrid MVF600 SoC.
> > >
> > > This patch adds basic support for Vybrid MVF600TWR board.
> > >
> > > Signed-off-by: Alison Wang <b18965@freescale.com>
> > > Signed-off-by: Jason Jin <Jason.jin@freescale.com>
> > > Signed-off-by: TsiChung Liew <tsicliew@gmail.com>
> > 
> > [...]
> > 
> > > diff --git a/include/configs/mvf600twr.h b/include/configs/mvf600twr.h
> > > new file mode 100644 index 0000000..1cfb9f6
> > > --- /dev/null
> > > +++ b/include/configs/mvf600twr.h
> > > @@ -0,0 +1,140 @@
> > > +/*
> > > + * Copyright 2013 Freescale Semiconductor, Inc.
> > > + *
> > > + * Configuration settings for the Freescale Vybrid mvf600twr board.
> > > + *
> > > + * This program is free software; you can redistribute it and/or
> > > + * modify it under the terms of the GNU General Public License as
> > > + * published by the Free Software Foundation; either version 2 of
> > > + * the License, or (at your option) any later version.
> > > + *
> > > + * This program is distributed in the hope that it will be useful,
> > > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	See the
> > > + * GNU General Public License for more details.
> > > + *
> > > + * You should have received a copy of the GNU General Public License
> > > + * along with this program; if not, write to the Free Software
> > > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> > > + * MA 02111-1307 USA
> > > + */
> > > +
> > > +#ifndef __CONFIG_H
> > > +#define __CONFIG_H
> > > +
> > > +#include <asm/arch/imx-regs.h>
> > > +#include <config_cmd_default.h>
> > > +
> > > +#define CONFIG_MVF600
> > > +
> > 
> > [...]
> > 
> > > +#define CONFIG_CMD_PING
> > > +#define CONFIG_CMD_DHCP
> > > +#define CONFIG_CMD_MII
> > > +#define CONFIG_CMD_NET
> > > +#define CONFIG_FEC_MXC
> > > +#define CONFIG_MII
> > > +#define IMX_FEC_BASE			ENET_BASE_ADDR
> > > +#define CONFIG_FEC_XCV_TYPE		RMII
> > > +#define CONFIG_ETHPRIME			"FEC"
> > 
> > You don't need to define this one with only 1 Ethernet interface defined.
> > But isn't the MVF600 a dual-Ethernet SoC?
> [Alison Wang] Yes, MVF600 is a dual-Ethernet SoC. I will change it to "FEC0".
> Thanks.

CONFIG_ETHPRIME should just be removed if you are not going to enable the 2nd
FEC in U-Boot. But if you plan to enable the 2nd FEC, which will have to be done
now or later for a dual-Ethernet SoC, then you have to:
 - remove CONFIG_FEC_MXC_PHYADDR and IMX_FEC_BASE,
 - define CONFIG_ETHPRIME to "FEC0",
 - call fecmxc_initialize_multi() once for each FEC instead of calling
   fecmxc_initialize() from cpu_eth_init() in generic.c (you can define
   ENET1_BASE_ADDR and ENET2_BASE_ADDR instead of ENET_BASE_ADDR in imx-regs.h,
   and CONFIG_FEC1_MXC_PHYADDR and CONFIG_FEC2_MXC_PHYADDR instead of
   CONFIG_FEC_MXC_PHYADDR in mvf600twr.h, then pass them to
   fecmxc_initialize_multi() from cpu_eth_init(), with 0 and 1 as the IDs),
 - add support for the 2nd FEC in imx_get_mac_from_fuse(),
 - update doc/README.mvf600 to say which fuses are used for the MAC address of
   the 2nd FEC.

[...]

Best regards,
Beno?t

[U-Boot] [PATCH v3 6/6] arm: mvf600: Add basic support for Vybrid MVF600TWR board

[Benoît Thébaudeau]

Hi Alison,

On Wednesday, May 22, 2013 10:23:12 AM, Wang Huan-B18965 wrote:

[...]

> > > +
> > > +#define ENET_PAD_CTRL	(PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH
> > | \
> > > +			PAD_CTL_DSE_50ohm | PAD_CTL_OBE_IBE_ENABLE)
> > > +
> > > +#define DDR_PAD_CTRL	PAD_CTL_DSE_25ohm
> > 
> > MUX_PAD_CTRL() could be added to the 4 pad control definitions above in
> > order to avoid repeating it everywhere below. But using MUX_PAD_CTRL()
> > relies on the fact that the pad control values in mvf_pins.h are all 0
> > (which is the case, but this is dangerous if this is changed later), so
> > a better approach could be to use NEW_PAD_CTRL(), e.g.:
> >         NEW_PAD_CTRL(MVF600_PAD_DDR_A15__DDR_A_15, DDR_PAD_CTRL),
> > instead of:
> >         MVF600_PAD_DDR_A15__DDR_A_15 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> > 
> > > +
> [Alison Wang] I have a question about using NEW_PAD_CTRL(). If NEW_PAD_CTRL()
> is used, should the pad control values for MVF600_PAD_DDR_A15__DDR_A_15 in
> mvf_pins.h
> be the same as DDR_PAD_CTRL? I saw you didn't use the same value on other
> platforms,
> how do you define it?

No, you don't have to change mvf_pins.h. That's what NEW_PAD_CTRL() is useful
for: You can have any pad control value defined in mvf_pins.h, and a board can
override the pad control values when using definitions from mvf_pins.h, without
having to modify mvf_pins.h.

E.g.:
---
mvf_pins.h:
MVF600_PAD_PTA6__RMII0_CLKIN = IOMUX_PAD(0x0, 0x0, 2, 0x0, 0, PAD_CTRL1),

mvf600twr.c:
NEW_PAD_CTRL(MVF600_PAD_PTA6__RMII0_CLKIN, PAD_CTRL2),
---
would have the same effect as a theoretical:
---
mvf_pins.h:
MVF600_PAD_PTA6__RMII0_CLKIN = IOMUX_PAD(0x0, 0x0, 2, 0x0, 0, PAD_CTRL2),

mvf600twr.c:
MVF600_PAD_PTA6__RMII0_CLKIN,
---

But if you think that the pad control values that you have defined in
mvf600twr.c are not specific to this board and should be used as the default pad
control values for all boards based on the MVF600, then you should move those
definitions to mvf_pins.h, and use them there, which means that you will no
longer need MUX_PAD_CTRL() or NEW_PAD_CTRL() in mvf600twr.c:
---
mvf_pins.h:
#define MVF600_DDR_PAD_CTRL	PAD_CTL_DSE_25ohm
...
MVF600_PAD_DDR_A15__DDR_A_15 = IOMUX_PAD(0x0220, 0x0220, 0, 0x0000, 0,
                                         MVF600_DDR_PAD_CTRL),

mvf600twr.c:
MVF600_PAD_DDR_A15__DDR_A_15,
---

Best regards,
Beno?t

[U-Boot] [PATCH v3 6/6] arm: mvf600: Add basic support for Vybrid MVF600TWR board

[Wang Huan-B18965]

Hi, Benoit,

> On Wednesday, May 22, 2013 5:17:41 AM, Wang Huan-B18965 wrote:
> > Hi, Benoit,
> >
> > > -----Original Message-----
> > > From: Beno?t Th?baudeau [mailto:benoit.thebaudeau at advansee.com]
> > > Sent: Wednesday, May 22, 2013 1:29 AM
> > > To: Wang Huan-B18965
> > > Cc: sbabic at denx.de; u-boot at lists.denx.de; TsiChung Liew; Jin
> > > Zhengxiong- R64188; Estevam Fabio-R49496
> > > Subject: Re: [U-Boot] [PATCH v3 6/6] arm: mvf600: Add basic support
> > > for Vybrid MVF600TWR board
> > >
> > > Hi Alison,
> > >
> > > On Tuesday, May 21, 2013 11:03:01 AM, Alison Wang wrote:
> > > > MVF600TWR is a board based on Vybrid MVF600 SoC.
> > > >
> > > > This patch adds basic support for Vybrid MVF600TWR board.
> > > >
> > > > Signed-off-by: Alison Wang <b18965@freescale.com>
> > > > Signed-off-by: Jason Jin <Jason.jin@freescale.com>
> > > > Signed-off-by: TsiChung Liew <tsicliew@gmail.com>
> > >
> > > [...]
> > >
> > > > diff --git a/include/configs/mvf600twr.h
> > > > b/include/configs/mvf600twr.h new file mode 100644 index
> > > > 0000000..1cfb9f6
> > > > --- /dev/null
> > > > +++ b/include/configs/mvf600twr.h
> > > > @@ -0,0 +1,140 @@
> > > > +/*
> > > > + * Copyright 2013 Freescale Semiconductor, Inc.
> > > > + *
> > > > + * Configuration settings for the Freescale Vybrid mvf600twr
> board.
> > > > + *
> > > > + * This program is free software; you can redistribute it and/or
> > > > + * modify it under the terms of the GNU General Public License
> as
> > > > + * published by the Free Software Foundation; either version 2
> of
> > > > + * the License, or (at your option) any later version.
> > > > + *
> > > > + * This program is distributed in the hope that it will be
> > > > +useful,
> > > > + * but WITHOUT ANY WARRANTY; without even the implied warranty
> of
> > > > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	See
> the
> > > > + * GNU General Public License for more details.
> > > > + *
> > > > + * You should have received a copy of the GNU General Public
> > > > +License
> > > > + * along with this program; if not, write to the Free Software
> > > > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> > > > + * MA 02111-1307 USA
> > > > + */
> > > > +
> > > > +#ifndef __CONFIG_H
> > > > +#define __CONFIG_H
> > > > +
> > > > +#include <asm/arch/imx-regs.h>
> > > > +#include <config_cmd_default.h>
> > > > +
> > > > +#define CONFIG_MVF600
> > > > +
> > >
> > > [...]
> > >
> > > > +#define CONFIG_CMD_PING
> > > > +#define CONFIG_CMD_DHCP
> > > > +#define CONFIG_CMD_MII
> > > > +#define CONFIG_CMD_NET
> > > > +#define CONFIG_FEC_MXC
> > > > +#define CONFIG_MII
> > > > +#define IMX_FEC_BASE			ENET_BASE_ADDR
> > > > +#define CONFIG_FEC_XCV_TYPE		RMII
> > > > +#define CONFIG_ETHPRIME			"FEC"
> > >
> > > You don't need to define this one with only 1 Ethernet interface
> defined.
> > > But isn't the MVF600 a dual-Ethernet SoC?
> > [Alison Wang] Yes, MVF600 is a dual-Ethernet SoC. I will change it to
> "FEC0".
> > Thanks.
> 
> CONFIG_ETHPRIME should just be removed if you are not going to enable
> the 2nd FEC in U-Boot. But if you plan to enable the 2nd FEC, which
> will have to be done now or later for a dual-Ethernet SoC, then you
> have to:
>  - remove CONFIG_FEC_MXC_PHYADDR and IMX_FEC_BASE,
>  - define CONFIG_ETHPRIME to "FEC0",
>  - call fecmxc_initialize_multi() once for each FEC instead of calling
>    fecmxc_initialize() from cpu_eth_init() in generic.c (you can define
>    ENET1_BASE_ADDR and ENET2_BASE_ADDR instead of ENET_BASE_ADDR in
> imx-regs.h,
>    and CONFIG_FEC1_MXC_PHYADDR and CONFIG_FEC2_MXC_PHYADDR instead of
>    CONFIG_FEC_MXC_PHYADDR in mvf600twr.h, then pass them to
>    fecmxc_initialize_multi() from cpu_eth_init(), with 0 and 1 as the
> IDs),
>  - add support for the 2nd FEC in imx_get_mac_from_fuse(),
>  - update doc/README.mvf600 to say which fuses are used for the MAC
> address of
>    the 2nd FEC.
[Alison Wang] Agree. Thanks.

Best Regards,
Alison Wang

[U-Boot] [PATCH v3 6/6] arm: mvf600: Add basic support for Vybrid MVF600TWR board

[Wang Huan-B18965]

Hi, Benoit,

> On Wednesday, May 22, 2013 10:23:12 AM, Wang Huan-B18965 wrote:
> 
> [...]
> 
> > > > +
> > > > +#define ENET_PAD_CTRL	(PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH
> > > | \
> > > > +			PAD_CTL_DSE_50ohm | PAD_CTL_OBE_IBE_ENABLE)
> > > > +
> > > > +#define DDR_PAD_CTRL	PAD_CTL_DSE_25ohm
> > >
> > > MUX_PAD_CTRL() could be added to the 4 pad control definitions
> above
> > > in order to avoid repeating it everywhere below. But using
> > > MUX_PAD_CTRL() relies on the fact that the pad control values in
> > > mvf_pins.h are all 0 (which is the case, but this is dangerous if
> > > this is changed later), so a better approach could be to use
> NEW_PAD_CTRL(), e.g.:
> > >         NEW_PAD_CTRL(MVF600_PAD_DDR_A15__DDR_A_15, DDR_PAD_CTRL),
> > > instead of:
> > >         MVF600_PAD_DDR_A15__DDR_A_15 | MUX_PAD_CTRL(DDR_PAD_CTRL),
> > >
> > > > +
> > [Alison Wang] I have a question about using NEW_PAD_CTRL(). If
> > NEW_PAD_CTRL() is used, should the pad control values for
> > MVF600_PAD_DDR_A15__DDR_A_15 in mvf_pins.h be the same as
> > DDR_PAD_CTRL? I saw you didn't use the same value on other platforms,
> > how do you define it?
> 
> No, you don't have to change mvf_pins.h. That's what NEW_PAD_CTRL() is
> useful
> for: You can have any pad control value defined in mvf_pins.h, and a
> board can override the pad control values when using definitions from
> mvf_pins.h, without having to modify mvf_pins.h.
> 
> E.g.:
> ---
> mvf_pins.h:
> MVF600_PAD_PTA6__RMII0_CLKIN = IOMUX_PAD(0x0, 0x0, 2, 0x0, 0,
> PAD_CTRL1),
> 
> mvf600twr.c:
> NEW_PAD_CTRL(MVF600_PAD_PTA6__RMII0_CLKIN, PAD_CTRL2),
> ---
> would have the same effect as a theoretical:
> ---
> mvf_pins.h:
> MVF600_PAD_PTA6__RMII0_CLKIN = IOMUX_PAD(0x0, 0x0, 2, 0x0, 0,
> PAD_CTRL2),
> 
> mvf600twr.c:
> MVF600_PAD_PTA6__RMII0_CLKIN,
> ---
> 
> But if you think that the pad control values that you have defined in
> mvf600twr.c are not specific to this board and should be used as the
> default pad control values for all boards based on the MVF600, then you
> should move those definitions to mvf_pins.h, and use them there, which
> means that you will no longer need MUX_PAD_CTRL() or NEW_PAD_CTRL() in
> mvf600twr.c:
> ---
> mvf_pins.h:
> #define MVF600_DDR_PAD_CTRL	PAD_CTL_DSE_25ohm
> ...
> MVF600_PAD_DDR_A15__DDR_A_15 = IOMUX_PAD(0x0220, 0x0220, 0, 0x0000, 0,
>                                          MVF600_DDR_PAD_CTRL),
> 
> mvf600twr.c:
> MVF600_PAD_DDR_A15__DDR_A_15,
[Alison Wang] I see. Thanks.

Best Regards,
Alison Wang