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From: Stefan Roese <sr@denx.de>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH] ppc4xx: Add DDR1/2 macros in ppc4xx-sdram.h for non-405EX as well
Date: Thu, 10 Jun 2010 11:27:55 +0200	[thread overview]
Message-ID: <1276162075-13901-1-git-send-email-sr@denx.de> (raw)

This patch adds some DDR(2) macros to all PPC4xx's equipped with
this IBM DDR1/2 controller.

Signed-off-by: Stefan Roese <sr@denx.de>
---
 arch/powerpc/include/asm/ppc4xx-sdram.h |    4 +++-
 1 files changed, 3 insertions(+), 1 deletions(-)

diff --git a/arch/powerpc/include/asm/ppc4xx-sdram.h b/arch/powerpc/include/asm/ppc4xx-sdram.h
index 66cf509..d9506e2 100644
--- a/arch/powerpc/include/asm/ppc4xx-sdram.h
+++ b/arch/powerpc/include/asm/ppc4xx-sdram.h
@@ -344,6 +344,9 @@
 #define SDRAM_RXBAS_SDSZ_2048		SDRAM_RXBAS_SDSZ_2048MB
 #define SDRAM_RXBAS_SDSZ_4096		SDRAM_RXBAS_SDSZ_4096MB
 #define SDRAM_RXBAS_SDSZ_8192		SDRAM_RXBAS_SDSZ_8192MB
+#endif /* CONFIG_405EX */
+
+/* The mode definitions are the same for all PPC4xx variants */
 #define SDRAM_RXBAS_SDAM_MODE0		PPC_REG_VAL(23, 0x0)
 #define SDRAM_RXBAS_SDAM_MODE1		PPC_REG_VAL(23, 0x1)
 #define SDRAM_RXBAS_SDAM_MODE2		PPC_REG_VAL(23, 0x2)
@@ -356,7 +359,6 @@
 #define SDRAM_RXBAS_SDAM_MODE9		PPC_REG_VAL(23, 0x9)
 #define SDRAM_RXBAS_SDBE_DISABLE	PPC_REG_VAL(31, 0x0)
 #define SDRAM_RXBAS_SDBE_ENABLE		PPC_REG_VAL(31, 0x1)
-#endif /* CONFIG_405EX */
 
 /*
  * Memory controller registers
-- 
1.7.1

             reply	other threads:[~2010-06-10  9:27 UTC|newest]

Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2010-06-10  9:27 Stefan Roese [this message]
2010-07-01  8:29 ` [U-Boot] [PATCH] ppc4xx: Add DDR1/2 macros in ppc4xx-sdram.h for non-405EX as well Stefan Roese

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