From mboxrd@z Thu Jan 1 00:00:00 1970 From: Kumar Gala Date: Thu, 30 Sep 2010 09:11:45 -0500 Subject: [U-Boot] [PATCH] powerpc/p4080: Add new CPC register - HDBCR0 In-Reply-To: <1285855905-7186-3-git-send-email-galak@kernel.crashing.org> References: <1285855905-7186-1-git-send-email-galak@kernel.crashing.org> <1285855905-7186-2-git-send-email-galak@kernel.crashing.org> <1285855905-7186-3-git-send-email-galak@kernel.crashing.org> Message-ID: <1285855905-7186-4-git-send-email-galak@kernel.crashing.org> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Manual was updated to add a new register for disabling CDQ speculation. Signed-off-by: Kumar Gala --- arch/powerpc/include/asm/immap_85xx.h | 5 ++++- 1 files changed, 4 insertions(+), 1 deletions(-) diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 3dd2b7f..30c64eb 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -1589,7 +1589,9 @@ typedef struct cpc_corenet { u32 cpcerreaddr; /* error extended address */ u32 cpcerraddr; /* error address */ u32 cpcerrctl; /* error control */ - u32 res9[105]; /* pad out to 4k */ + u32 res9[41]; /* pad out to 4k */ + u32 cpchdbcr0; /* hardware debug control register 0 */ + u32 res10[63]; /* pad out to 4k */ } cpc_corenet_t; #define CPC_CSR0_CE 0x80000000 /* Cache Enable */ @@ -1616,6 +1618,7 @@ typedef struct cpc_corenet { #define CPC_SRCR0_SRAMSZ_32_WAY 0x0000000a #define CPC_SRCR0_SRAMEN 0x00000001 #define CPC_ERRDIS_TMHITDIS 0x00000080 /* multi-way hit disable */ +#define CPC_HDBCR0_CDQ_SPEC_DIS 0x08000000 #endif /* CONFIG_SYS_FSL_CPC */ /* Global Utilities Block */ -- 1.7.2.3