* [U-Boot] [PATCH 0/3] Add support for the IGEP v2 board.
@ 2010-10-09 23:13 Enric Balletbo i Serra
2010-10-09 23:13 ` [U-Boot] [PATCH 1/3] mtd: OneNAND: add support for OneNAND manufactured by Numonyx Enric Balletbo i Serra
` (2 more replies)
0 siblings, 3 replies; 9+ messages in thread
From: Enric Balletbo i Serra @ 2010-10-09 23:13 UTC (permalink / raw)
To: u-boot
Hello,
This is the first version of patch series to add initial support for
OMAP3 IGEP v2 board. Please consider to include in next merge window.
Cheers,
Enric
^ permalink raw reply [flat|nested] 9+ messages in thread
* [U-Boot] [PATCH 1/3] mtd: OneNAND: add support for OneNAND manufactured by Numonyx
2010-10-09 23:13 [U-Boot] [PATCH 0/3] Add support for the IGEP v2 board Enric Balletbo i Serra
@ 2010-10-09 23:13 ` Enric Balletbo i Serra
2010-10-10 4:41 ` Steve Sakoman
2010-10-09 23:13 ` [U-Boot] [PATCH 2/3] OMAP3: SDRC: Introduce Numonyx DDR type Enric Balletbo i Serra
2010-10-09 23:13 ` [U-Boot] [PATCH 3/3] OMAP3: Add support for the IGEP v2 board Enric Balletbo i Serra
2 siblings, 1 reply; 9+ messages in thread
From: Enric Balletbo i Serra @ 2010-10-09 23:13 UTC (permalink / raw)
To: u-boot
This patch adds the Numonyx manufacturer code (0x20) to
onenand manufacturers.
Signed-off-by: Enric Balletbo i Serra <eballetbo@gmail.com>
---
drivers/mtd/onenand/onenand_base.c | 1 +
include/linux/mtd/onenand.h | 1 +
2 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/drivers/mtd/onenand/onenand_base.c b/drivers/mtd/onenand/onenand_base.c
index f9273ab..c978420 100644
--- a/drivers/mtd/onenand/onenand_base.c
+++ b/drivers/mtd/onenand/onenand_base.c
@@ -2214,6 +2214,7 @@ char *onenand_print_device_info(int device, int version)
static const struct onenand_manufacturers onenand_manuf_ids[] = {
{ONENAND_MFR_SAMSUNG, "Samsung"},
+ {ONENAND_MFR_NUMONYX, "Numonyx"},
};
/**
diff --git a/include/linux/mtd/onenand.h b/include/linux/mtd/onenand.h
index 68e174e..0025fd0 100644
--- a/include/linux/mtd/onenand.h
+++ b/include/linux/mtd/onenand.h
@@ -155,6 +155,7 @@ struct onenand_chip {
* OneNAND Flash Manufacturer ID Codes
*/
#define ONENAND_MFR_SAMSUNG 0xec
+#define ONENAND_MFR_NUMONYX 0x20
/**
* struct nand_manufacturers - NAND Flash Manufacturer ID Structure
--
1.7.0.4
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [U-Boot] [PATCH 2/3] OMAP3: SDRC: Introduce Numonyx DDR type
2010-10-09 23:13 [U-Boot] [PATCH 0/3] Add support for the IGEP v2 board Enric Balletbo i Serra
2010-10-09 23:13 ` [U-Boot] [PATCH 1/3] mtd: OneNAND: add support for OneNAND manufactured by Numonyx Enric Balletbo i Serra
@ 2010-10-09 23:13 ` Enric Balletbo i Serra
2010-10-10 4:46 ` Steve Sakoman
2010-10-09 23:13 ` [U-Boot] [PATCH 3/3] OMAP3: Add support for the IGEP v2 board Enric Balletbo i Serra
2 siblings, 1 reply; 9+ messages in thread
From: Enric Balletbo i Serra @ 2010-10-09 23:13 UTC (permalink / raw)
To: u-boot
Introduce Numonyx DDR timings and provide CONFIG_OMAP3_NUMONYX_DDR
config options to allow for platform files to setup their timings.
Signed-off-by: Enric Balletbo i Serra <eballetbo@gmail.com>
---
arch/arm/include/asm/arch-omap3/mem.h | 42 +++++++++++++++++++++++++++++++++
1 files changed, 42 insertions(+), 0 deletions(-)
diff --git a/arch/arm/include/asm/arch-omap3/mem.h b/arch/arm/include/asm/arch-omap3/mem.h
index a78cf9f..cb59588 100644
--- a/arch/arm/include/asm/arch-omap3/mem.h
+++ b/arch/arm/include/asm/arch-omap3/mem.h
@@ -128,6 +128,44 @@ enum {
(MICRON_XSR_165 << 0) | (MICRON_TXP_165 << 8) | \
(MICRON_TWTR_165 << 16))
+/* NUMONYX part of IGEP v2 (165MHz optimized) 6.06ns
+ * ACTIMA
+ * TDAL = Twr/Tck + Trp/tck = 15/6 + 18/6 = 2.5 + 3 = 5.5 -> 6
+ * TDPL (Twr) = 15/6 = 2.5 -> 3
+ * TRRD = 12/6 = 2
+ * TRCD = 22.5/6 = 3.75 -> 4
+ * TRP = 18/6 = 3
+ * TRAS = 42/6 = 7
+ * TRC = 60/6 = 10
+ * TRFC = 140/6 = 23.3 -> 24
+ * ACTIMB
+ * TWTR = 2
+ * TCKE = 2
+ * TXSR = 200/6 = 33.3 -> 34
+ * TXP = 1.0 + 1.1 = 2.1 -> 3
+ */
+#define NUMONYX_TDAL_165 6
+#define NUMONYX_TDPL_165 3
+#define NUMONYX_TRRD_165 2
+#define NUMONYX_TRCD_165 4
+#define NUMONYX_TRP_165 3
+#define NUMONYX_TRAS_165 7
+#define NUMONYX_TRC_165 10
+#define NUMONYX_TRFC_165 24
+#define NUMONYX_V_ACTIMA_165 ((NUMONYX_TRFC_165 << 27) | \
+ (NUMONYX_TRC_165 << 22) | (NUMONYX_TRAS_165 << 18) | \
+ (NUMONYX_TRP_165 << 15) | (NUMONYX_TRCD_165 << 12) | \
+ (NUMONYX_TRRD_165 << 9) | (NUMONYX_TDPL_165 << 6) | \
+ (NUMONYX_TDAL_165))
+
+#define NUMONYX_TWTR_165 2
+#define NUMONYX_TCKE_165 2
+#define NUMONYX_TXP_165 3
+#define NUMONYX_XSR_165 34
+#define NUMONYX_V_ACTIMB_165 ((NUMONYX_TCKE_165 << 12) | \
+ (NUMONYX_XSR_165 << 0)) | (NUMONYX_TXP_165 << 8) | \
+ (NUMONYX_TWTR_165 << 16)
+
#ifdef CONFIG_OMAP3_INFINEON_DDR
#define V_ACTIMA_165 INFINEON_V_ACTIMA_165
#define V_ACTIMB_165 INFINEON_V_ACTIMB_165
@@ -136,6 +174,10 @@ enum {
#define V_ACTIMA_165 MICRON_V_ACTIMA_165
#define V_ACTIMB_165 MICRON_V_ACTIMB_165
#endif
+#ifdef CONFIG_OMAP3_NUMONYX_DDR
+#define V_ACTIMA_165 NUMONYX_V_ACTIMA_165
+#define V_ACTIMB_165 NUMONYX_V_ACTIMB_165
+#endif
#if !defined(V_ACTIMA_165) || !defined(V_ACTIMB_165)
#error "Please choose the right DDR type in config header"
--
1.7.0.4
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [U-Boot] [PATCH 3/3] OMAP3: Add support for the IGEP v2 board.
2010-10-09 23:13 [U-Boot] [PATCH 0/3] Add support for the IGEP v2 board Enric Balletbo i Serra
2010-10-09 23:13 ` [U-Boot] [PATCH 1/3] mtd: OneNAND: add support for OneNAND manufactured by Numonyx Enric Balletbo i Serra
2010-10-09 23:13 ` [U-Boot] [PATCH 2/3] OMAP3: SDRC: Introduce Numonyx DDR type Enric Balletbo i Serra
@ 2010-10-09 23:13 ` Enric Balletbo i Serra
2010-10-10 4:51 ` Steve Sakoman
2 siblings, 1 reply; 9+ messages in thread
From: Enric Balletbo i Serra @ 2010-10-09 23:13 UTC (permalink / raw)
To: u-boot
The IGEP v2 board is a low-cost, fan-less and industrial temperature
range single board computer that unleashes laptop-like performance and
expandability without the bulk, expense, or noise of typical desktop
machines. Its architecture shares much in common with other OMAP3 boards.
Signed-off-by: Enric Balletbo i Serra <eballetbo@gmail.com>
---
MAKEALL | 1 +
board/isee/igep0020/Makefile | 49 +++++++++
board/isee/igep0020/config.mk | 34 ++++++
board/isee/igep0020/igep0020.c | 129 ++++++++++++++++++++++
board/isee/igep0020/igep0020.h | 156 +++++++++++++++++++++++++++
boards.cfg | 1 +
include/configs/igep0020.h | 230 ++++++++++++++++++++++++++++++++++++++++
7 files changed, 600 insertions(+), 0 deletions(-)
create mode 100644 board/isee/igep0020/Makefile
create mode 100644 board/isee/igep0020/config.mk
create mode 100644 board/isee/igep0020/igep0020.c
create mode 100644 board/isee/igep0020/igep0020.h
create mode 100644 include/configs/igep0020.h
diff --git a/MAKEALL b/MAKEALL
index 1b506d6..78dce8b 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -490,6 +490,7 @@ LIST_ARM11=" \
LIST_ARMV7=" \
am3517_evm \
devkit8000 \
+ igep0020 \
mx51evk \
omap3_beagle \
omap3_overo \
diff --git a/board/isee/igep0020/Makefile b/board/isee/igep0020/Makefile
new file mode 100644
index 0000000..2f11879
--- /dev/null
+++ b/board/isee/igep0020/Makefile
@@ -0,0 +1,49 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS := igep0020.o
+
+SRCS := $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+ rm -f $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/isee/igep0020/config.mk b/board/isee/igep0020/config.mk
new file mode 100644
index 0000000..3ae6a40
--- /dev/null
+++ b/board/isee/igep0020/config.mk
@@ -0,0 +1,34 @@
+#
+# (C) Copyright 2009
+# ISEE 2007 SL, <www.iseebcn.com>
+#
+# IGEP0020 uses OMAP3 (ARM-CortexA8) cpu
+# see http://www.ti.com/ for more information on Texas Instruments
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+# Physical Address:
+# 8000'0000 (bank0)
+# A000/0000 (bank1)
+# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
+# (mem base + reserved)
+
+# For use with external or internal boots.
+TEXT_BASE = 0x80008000
+
diff --git a/board/isee/igep0020/igep0020.c b/board/isee/igep0020/igep0020.c
new file mode 100644
index 0000000..f5b51e9
--- /dev/null
+++ b/board/isee/igep0020/igep0020.c
@@ -0,0 +1,129 @@
+/*
+ * (C) Copyright 2010
+ * ISEE 2007 SL, <www.iseebcn.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <twl4030.h>
+#include <asm/io.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-types.h>
+#include "igep0020.h"
+
+/* GPMC definitions for LAN9221 chips */
+static const u32 gpmc_lan_config[] = {
+ NET_LAN9221_GPMC_CONFIG1,
+ NET_LAN9221_GPMC_CONFIG2,
+ NET_LAN9221_GPMC_CONFIG3,
+ NET_LAN9221_GPMC_CONFIG4,
+ NET_LAN9221_GPMC_CONFIG5,
+ NET_LAN9221_GPMC_CONFIG6,
+};
+
+/*
+ * Routine: board_init
+ * Description: Early hardware init.
+ */
+int board_init(void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
+ /* board id for Linux */
+ gd->bd->bi_arch_number = MACH_TYPE_IGEP0020;
+ /* boot param addr */
+ gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
+
+ return 0;
+}
+
+/*
+ * Routine: setup_net_chip
+ * Description: Setting up the configuration GPMC registers specific to the
+ * Ethernet hardware.
+ */
+#if defined(CONFIG_CMD_NET)
+static void setup_net_chip(void)
+{
+ struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
+
+ enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[5], 0x2C000000,
+ GPMC_SIZE_16M);
+
+ /* Enable off mode for NWE in PADCONF_GPMC_NWE register */
+ writew(readw(&ctrl_base ->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
+ /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
+ writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
+ /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
+ writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
+ &ctrl_base->gpmc_nadv_ale);
+
+ /* Make GPIO 64 as output pin and send a magic pulse through it */
+ if (!omap_request_gpio(64)) {
+ omap_set_gpio_direction(64, 0);
+ omap_set_gpio_dataout(64, 1);
+ udelay(1);
+ omap_set_gpio_dataout(64, 0);
+ udelay(1);
+ omap_set_gpio_dataout(64, 1);
+ }
+}
+#endif
+
+/*
+ * Routine: misc_init_r
+ * Description: Configure board specific parts
+ */
+int misc_init_r(void)
+{
+ twl4030_power_init();
+
+#if defined(CONFIG_CMD_NET)
+ setup_net_chip();
+#endif
+
+ dieid_num_r();
+
+ return 0;
+}
+
+/*
+ * Routine: set_muxconf_regs
+ * Description: Setting up the configuration Mux registers specific to the
+ * hardware. Many pins need to be moved from protect to primary
+ * mode.
+ */
+void set_muxconf_regs(void)
+{
+ MUX_DEFAULT();
+}
+
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_SMC911X
+ rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+#endif
+ return rc;
+}
+
diff --git a/board/isee/igep0020/igep0020.h b/board/isee/igep0020/igep0020.h
new file mode 100644
index 0000000..c08d758
--- /dev/null
+++ b/board/isee/igep0020/igep0020.h
@@ -0,0 +1,156 @@
+/*
+ * (C) Copyright 2010
+ * ISEE 2007 SL, <www.iseebcn.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _IGEP0020_H_
+#define _IGEP0020_H_
+
+const omap3_sysinfo sysinfo = {
+ DDR_STACKED,
+ "IGEP v2 board",
+ "ONENAND",
+};
+
+/* GPMC CS 5 connected to an SMSC LAN9221 ethernet controller */
+#define NET_LAN9221_GPMC_CONFIG1 0x00001000
+#define NET_LAN9221_GPMC_CONFIG2 0x00080701
+#define NET_LAN9221_GPMC_CONFIG3 0x00020201
+#define NET_LAN9221_GPMC_CONFIG4 0x08030703
+#define NET_LAN9221_GPMC_CONFIG5 0x00060908
+#define NET_LAN9221_GPMC_CONFIG6 0x87030000
+#define NET_LAN9221_GPMC_CONFIG7 0x00000f6c
+
+static void setup_net_chip(void);
+
+/*
+ * IEN - Input Enable
+ * IDIS - Input Disable
+ * PTD - Pull type Down
+ * PTU - Pull type Up
+ * DIS - Pull type selection is inactive
+ * EN - Pull type selection is active
+ * M0 - Mode 0
+ * The commented string gives the final mux configuration for that pin
+ */
+#define MUX_DEFAULT()\
+ MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /* SDRC_D0 */\
+ MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /* SDRC_D1 */\
+ MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /* SDRC_D2 */\
+ MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /* SDRC_D3 */\
+ MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /* SDRC_D4 */\
+ MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /* SDRC_D5 */\
+ MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /* SDRC_D6 */\
+ MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /* SDRC_D7 */\
+ MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /* SDRC_D8 */\
+ MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /* SDRC_D9 */\
+ MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /* SDRC_D10 */\
+ MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /* SDRC_D11 */\
+ MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /* SDRC_D12 */\
+ MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /* SDRC_D13 */\
+ MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /* SDRC_D14 */\
+ MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /* SDRC_D15 */\
+ MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /* SDRC_D16 */\
+ MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /* SDRC_D17 */\
+ MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /* SDRC_D18 */\
+ MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /* SDRC_D19 */\
+ MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /* SDRC_D20 */\
+ MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /* SDRC_D21 */\
+ MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /* SDRC_D22 */\
+ MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /* SDRC_D23 */\
+ MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /* SDRC_D24 */\
+ MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /* SDRC_D25 */\
+ MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /* SDRC_D26 */\
+ MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /* SDRC_D27 */\
+ MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /* SDRC_D28 */\
+ MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /* SDRC_D29 */\
+ MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /* SDRC_D30 */\
+ MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /* SDRC_D31 */\
+ MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /* SDRC_CLK */\
+ MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /* SDRC_DQS0 */\
+ MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /* SDRC_DQS1 */\
+ MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /* SDRC_DQS2 */\
+ MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /* SDRC_DQS3 */\
+ MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /* GPMC_A1 */\
+ MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /* GPMC_A2 */\
+ MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /* GPMC_A3 */\
+ MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /* GPMC_A4 */\
+ MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /* GPMC_A5 */\
+ MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /* GPMC_A6 */\
+ MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /* GPMC_A7 */\
+ MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /* GPMC_A8 */\
+ MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /* GPMC_A9 */\
+ MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /* GPMC_A10 */\
+ MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /* GPMC_D0 */\
+ MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /* GPMC_D1 */\
+ MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /* GPMC_D2 */\
+ MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /* GPMC_D3 */\
+ MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /* GPMC_D4 */\
+ MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /* GPMC_D5 */\
+ MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /* GPMC_D6 */\
+ MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /* GPMC_D7 */\
+ MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /* GPMC_D8 */\
+ MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /* GPMC_D9 */\
+ MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /* GPMC_D10 */\
+ MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /* GPMC_D11 */\
+ MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /* GPMC_D12 */\
+ MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /* GPMC_D13 */\
+ MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /* GPMC_D14 */\
+ MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /* GPMC_D15 */\
+ MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /* GPMC_nCS0 */\
+ MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /* GPMC_nCS1 */\
+ MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) /* GPIO_nCS2 */\
+ MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)) /* GPIO_nCS3 */\
+ MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | EN | M0)) /* GPMC_nCS4 */\
+ MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0)) /* GPMC_nCS5 */\
+ MUX_VAL(CP(GPMC_NCS6), (IDIS | PTU | EN | M0)) /* GPMC_nCS6 */\
+ MUX_VAL(CP(GPMC_NCS7), (IDIS | PTU | EN | M0)) /* GPMC_nCS7 */\
+ MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /* GPMC_CLK */\
+ MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) /* GPMC_nADV_ALE */\
+ MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) /* GPMC_nOE */\
+ MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) /* GPMC_nWE */\
+ MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0)) /* GPMC_nBE0_CLE */\
+ MUX_VAL(CP(GPMC_NBE1), (IEN | PTD | DIS | M0)) /* GPMC_nBE1 */\
+ MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) /* GPMC_nWP */\
+ MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /* GPMC_WAIT0 */\
+ MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | DIS | M4)) /* GPIO_64-ETH_NRST */\
+ MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) /* MMC1_CLK */\
+ MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /* MMC1_CMD */\
+ MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /* MMC1_DAT0 */\
+ MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /* MMC1_DAT1 */\
+ MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /* MMC1_DAT2 */\
+ MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /* MMC1_DAT3 */\
+ MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /* UART3_TX */\
+ MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) /* UART3_RX */\
+ MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /* I2C1_SCL */\
+ MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /* I2C1_SDA */\
+ MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /* I2C4_SCL */\
+ MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /* I2C4_SDA */\
+ MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /* SYS_32K */\
+ MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /* GPIO_2 */\
+ MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /* GPIO_3 */\
+ MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /* GPIO_4 */\
+ MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /* GPIO_5 */\
+ MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /* GPIO_6 */\
+ MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /* GPIO_7 */\
+ MUX_VAL(CP(SYS_BOOT6), (IEN | PTD | DIS | M4)) /* GPIO_8 */\
+ MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) /* SDRC_CKE0 */\
+ MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | EN | M0)) /* SDRC_CKE1 */
+#endif
diff --git a/boards.cfg b/boards.cfg
index 202de1a..6f8db44 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -262,6 +262,7 @@ omap4_panda arm armv7 panda ti omap4
omap4_sdp4430 arm armv7 sdp4430 ti omap4
am3517_evm arm armv7 am3517evm logicpd omap3
devkit8000 arm armv7 devkit8000 timll omap3
+igep0020 arm armv7 igep0020 isee omap3
s5p_goni arm armv7 goni samsung s5pc1xx
smdkc100 arm armv7 smdkc100 samsung s5pc1xx
ixdpg425 arm ixp
diff --git a/include/configs/igep0020.h b/include/configs/igep0020.h
new file mode 100644
index 0000000..a884c3e
--- /dev/null
+++ b/include/configs/igep0020.h
@@ -0,0 +1,230 @@
+/*
+ * (C) Copyright 2010
+ * ISEE 2007 SL, <www.iseebcn.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+#include <asm/sizes.h>
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */
+#define CONFIG_OMAP 1 /* in a TI OMAP core */
+#define CONFIG_OMAP34XX 1 /* which is a 34XX */
+#define CONFIG_OMAP3430 1 /* which is in a 3430 */
+#define CONFIG_OMAP3_IGEP0020 1 /* working with IGEP0020 */
+
+#define CONFIG_SDRC /* The chip has SDRC controller */
+
+#include <asm/arch/cpu.h>
+#include <asm/arch/omap3.h>
+
+/*
+ * Display CPU and Board information
+ */
+#define CONFIG_DISPLAY_CPUINFO 1
+#define CONFIG_DISPLAY_BOARDINFO 1
+
+/* Clock Defines */
+#define V_OSCK 26000000 /* Clock output from T2 */
+#define V_SCLK (V_OSCK >> 1)
+
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG 1
+#define CONFIG_REVISION_TAG 1
+
+/*
+ * NS16550 Configuration
+ */
+
+#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
+
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE (-4)
+#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
+
+/* select serial console configuration */
+#define CONFIG_CONS_INDEX 3
+#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
+#define CONFIG_SERIAL3 3
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,115200}
+#define CONFIG_MMC 1
+#define CONFIG_OMAP3_MMC 1
+#define CONFIG_DOS_PARTITION 1
+
+/* DDR */
+#define CONFIG_OMAP3_NUMONYX_DDR 1
+
+/* USB */
+#define CONFIG_MUSB_UDC 1
+#define CONFIG_USB_OMAP3 1
+#define CONFIG_TWL4030_USB 1
+
+/* USB device configuration */
+#define CONFIG_USB_DEVICE 1
+#define CONFIG_USB_TTY 1
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
+
+/* Change these to suit your needs */
+#define CONFIG_USBD_VENDORID 0x0451
+#define CONFIG_USBD_PRODUCTID 0x5678
+#define CONFIG_USBD_MANUFACTURER "Texas Instruments"
+#define CONFIG_USBD_PRODUCT_NAME "IGEP"
+
+/* commands to include */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_EXT2 /* EXT2 Support */
+#define CONFIG_CMD_FAT /* FAT support */
+#define CONFIG_CMD_I2C /* I2C serial bus support */
+#define CONFIG_CMD_MMC /* MMC support */
+#define CONFIG_CMD_ONENAND /* ONENAND support */
+#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_NFS /* NFS support */
+#define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */
+#define CONFIG_MTD_DEVICE
+
+#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
+#undef CONFIG_CMD_IMLS /* List all found images */
+
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_HARD_I2C 1
+#define CONFIG_SYS_I2C_SPEED 100000
+#define CONFIG_SYS_I2C_SLAVE 1
+#define CONFIG_SYS_I2C_BUS 0
+#define CONFIG_SYS_I2C_BUS_SELECT 1
+#define CONFIG_DRIVER_OMAP34XX_I2C 1
+
+/*
+ * TWL4030
+ */
+#define CONFIG_TWL4030_POWER 1
+
+/* Environment information */
+#define CONFIG_BOOTCOMMAND \
+ "mmc init 0 ; fatload mmc 0 0x80000000 setup.ini ; source \0"
+
+#define CONFIG_BOOTDELAY 3
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "usbtty=cdc_acm\0"
+
+#define CONFIG_AUTO_COMPLETE 1
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_PROMPT "U-Boot # "
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
+
+#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */
+ /* works on */
+#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
+ 0x01F00000) /* 31MB */
+
+#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */
+ /* load address */
+
+#define CONFIG_SYS_MONITOR_LEN (256 << 10)
+
+/*
+ * OMAP3 has 12 GP timers, they can be driven by the system clock
+ * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
+ * This rate is divided by a local divisor.
+ */
+#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
+#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
+#define CONFIG_SYS_HZ 1000
+
+/*
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */
+
+/*
+ * Physical Memory Map
+ *
+ */
+#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
+#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
+#define PHYS_SDRAM_1_SIZE (32 << 20) /*@least 32 meg */
+#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
+
+/* SDRAM Bank Allocation method */
+#define SDRC_R_B_C 1
+
+/*
+ * FLASH and environment organization
+ */
+
+#define PISMO1_ONEN_SIZE GPMC_SIZE_128M /* Configure the PISMO */
+
+#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
+
+#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
+
+#define CONFIG_ENV_IS_IN_ONENAND 1
+#define CONFIG_ENV_SIZE (512 << 10) /* Total Size Environment */
+#define CONFIG_ENV_ADDR ONENAND_ENV_OFFSET
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
+#define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes for initial data */
+
+/*
+ * SMSC911x Ethernet
+ */
+#if defined(CONFIG_CMD_NET)
+#define CONFIG_NET_MULTI
+#define CONFIG_SMC911X
+#define CONFIG_SMC911X_32_BIT
+#define CONFIG_SMC911X_BASE 0x2C000000
+#endif /* (CONFIG_CMD_NET) */
+
+/* additions for new relocation code, must added to all boards */
+#undef CONFIG_SYS_ARM_WITHOUT_RELOC /* This board is tested with relocation support */
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_SP_ADDR (LOW_LEVEL_SRAM_STACK - CONFIG_SYS_GBL_DATA_SIZE)
+
+#endif /* __CONFIG_H */
--
1.7.0.4
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [U-Boot] [PATCH 1/3] mtd: OneNAND: add support for OneNAND manufactured by Numonyx
2010-10-09 23:13 ` [U-Boot] [PATCH 1/3] mtd: OneNAND: add support for OneNAND manufactured by Numonyx Enric Balletbo i Serra
@ 2010-10-10 4:41 ` Steve Sakoman
0 siblings, 0 replies; 9+ messages in thread
From: Steve Sakoman @ 2010-10-10 4:41 UTC (permalink / raw)
To: u-boot
On Sat, Oct 9, 2010 at 4:13 PM, Enric Balletbo i Serra
<eballetbo@gmail.com> wrote:
> This patch adds the Numonyx manufacturer code (0x20) to
> onenand manufacturers.
>
> Signed-off-by: Enric Balletbo i Serra <eballetbo@gmail.com>
> ---
> ?drivers/mtd/onenand/onenand_base.c | ? ?1 +
> ?include/linux/mtd/onenand.h ? ? ? ?| ? ?1 +
> ?2 files changed, 2 insertions(+), 0 deletions(-)
>
> diff --git a/drivers/mtd/onenand/onenand_base.c b/drivers/mtd/onenand/onenand_base.c
> index f9273ab..c978420 100644
> --- a/drivers/mtd/onenand/onenand_base.c
> +++ b/drivers/mtd/onenand/onenand_base.c
> @@ -2214,6 +2214,7 @@ char *onenand_print_device_info(int device, int version)
>
> ?static const struct onenand_manufacturers onenand_manuf_ids[] = {
> ? ? ? ?{ONENAND_MFR_SAMSUNG, "Samsung"},
> + ? ? ? {ONENAND_MFR_NUMONYX, "Numonyx"},
> ?};
>
> ?/**
> diff --git a/include/linux/mtd/onenand.h b/include/linux/mtd/onenand.h
> index 68e174e..0025fd0 100644
> --- a/include/linux/mtd/onenand.h
> +++ b/include/linux/mtd/onenand.h
> @@ -155,6 +155,7 @@ struct onenand_chip {
> ?* OneNAND Flash Manufacturer ID Codes
> ?*/
> ?#define ONENAND_MFR_SAMSUNG ? ?0xec
> +#define ONENAND_MFR_NUMONYX ? ?0x20
>
> ?/**
> ?* struct nand_manufacturers - NAND Flash Manufacturer ID Structure
> --
> 1.7.0.4
Acked-by: Steve Sakoman <steve.sakoman@linaro.org>
^ permalink raw reply [flat|nested] 9+ messages in thread
* [U-Boot] [PATCH 2/3] OMAP3: SDRC: Introduce Numonyx DDR type
2010-10-09 23:13 ` [U-Boot] [PATCH 2/3] OMAP3: SDRC: Introduce Numonyx DDR type Enric Balletbo i Serra
@ 2010-10-10 4:46 ` Steve Sakoman
0 siblings, 0 replies; 9+ messages in thread
From: Steve Sakoman @ 2010-10-10 4:46 UTC (permalink / raw)
To: u-boot
On Sun, 2010-10-10 at 01:13 +0200, Enric Balletbo i Serra wrote:
> Introduce Numonyx DDR timings and provide CONFIG_OMAP3_NUMONYX_DDR
> config options to allow for platform files to setup their timings.
>
> Signed-off-by: Enric Balletbo i Serra <eballetbo@gmail.com>
> ---
> arch/arm/include/asm/arch-omap3/mem.h | 42 +++++++++++++++++++++++++++++++++
> 1 files changed, 42 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/include/asm/arch-omap3/mem.h b/arch/arm/include/asm/arch-omap3/mem.h
> index a78cf9f..cb59588 100644
> --- a/arch/arm/include/asm/arch-omap3/mem.h
> +++ b/arch/arm/include/asm/arch-omap3/mem.h
> @@ -128,6 +128,44 @@ enum {
> (MICRON_XSR_165 << 0) | (MICRON_TXP_165 << 8) | \
> (MICRON_TWTR_165 << 16))
>
> +/* NUMONYX part of IGEP v2 (165MHz optimized) 6.06ns
> + * ACTIMA
> + * TDAL = Twr/Tck + Trp/tck = 15/6 + 18/6 = 2.5 + 3 = 5.5 -> 6
> + * TDPL (Twr) = 15/6 = 2.5 -> 3
> + * TRRD = 12/6 = 2
> + * TRCD = 22.5/6 = 3.75 -> 4
> + * TRP = 18/6 = 3
> + * TRAS = 42/6 = 7
> + * TRC = 60/6 = 10
> + * TRFC = 140/6 = 23.3 -> 24
> + * ACTIMB
> + * TWTR = 2
> + * TCKE = 2
> + * TXSR = 200/6 = 33.3 -> 34
> + * TXP = 1.0 + 1.1 = 2.1 -> 3
> + */
> +#define NUMONYX_TDAL_165 6
> +#define NUMONYX_TDPL_165 3
> +#define NUMONYX_TRRD_165 2
> +#define NUMONYX_TRCD_165 4
> +#define NUMONYX_TRP_165 3
> +#define NUMONYX_TRAS_165 7
> +#define NUMONYX_TRC_165 10
> +#define NUMONYX_TRFC_165 24
> +#define NUMONYX_V_ACTIMA_165 ((NUMONYX_TRFC_165 << 27) | \
> + (NUMONYX_TRC_165 << 22) | (NUMONYX_TRAS_165 << 18) | \
> + (NUMONYX_TRP_165 << 15) | (NUMONYX_TRCD_165 << 12) | \
> + (NUMONYX_TRRD_165 << 9) | (NUMONYX_TDPL_165 << 6) | \
> + (NUMONYX_TDAL_165))
> +
> +#define NUMONYX_TWTR_165 2
> +#define NUMONYX_TCKE_165 2
> +#define NUMONYX_TXP_165 3
> +#define NUMONYX_XSR_165 34
> +#define NUMONYX_V_ACTIMB_165 ((NUMONYX_TCKE_165 << 12) | \
> + (NUMONYX_XSR_165 << 0)) | (NUMONYX_TXP_165 << 8) | \
> + (NUMONYX_TWTR_165 << 16)
I think the parens in the above define aren't quite what you intended
(perhaps an extra close paren in the XSR term and a missing close paren
on the end of the define)
> #ifdef CONFIG_OMAP3_INFINEON_DDR
> #define V_ACTIMA_165 INFINEON_V_ACTIMA_165
> #define V_ACTIMB_165 INFINEON_V_ACTIMB_165
> @@ -136,6 +174,10 @@ enum {
> #define V_ACTIMA_165 MICRON_V_ACTIMA_165
> #define V_ACTIMB_165 MICRON_V_ACTIMB_165
> #endif
> +#ifdef CONFIG_OMAP3_NUMONYX_DDR
> +#define V_ACTIMA_165 NUMONYX_V_ACTIMA_165
> +#define V_ACTIMB_165 NUMONYX_V_ACTIMB_165
> +#endif
>
> #if !defined(V_ACTIMA_165) || !defined(V_ACTIMB_165)
> #error "Please choose the right DDR type in config header"
If the above change is made, then:
Acked-by: Steve Sakoman <steve.sakoman@linaro.org>
Steve
^ permalink raw reply [flat|nested] 9+ messages in thread
* [U-Boot] [PATCH 3/3] OMAP3: Add support for the IGEP v2 board.
2010-10-09 23:13 ` [U-Boot] [PATCH 3/3] OMAP3: Add support for the IGEP v2 board Enric Balletbo i Serra
@ 2010-10-10 4:51 ` Steve Sakoman
0 siblings, 0 replies; 9+ messages in thread
From: Steve Sakoman @ 2010-10-10 4:51 UTC (permalink / raw)
To: u-boot
On Sun, 2010-10-10 at 01:13 +0200, Enric Balletbo i Serra wrote:
> The IGEP v2 board is a low-cost, fan-less and industrial temperature
> range single board computer that unleashes laptop-like performance and
> expandability without the bulk, expense, or noise of typical desktop
> machines. Its architecture shares much in common with other OMAP3 boards.
>
> Signed-off-by: Enric Balletbo i Serra <eballetbo@gmail.com>
> ---
> MAKEALL | 1 +
> board/isee/igep0020/Makefile | 49 +++++++++
> board/isee/igep0020/config.mk | 34 ++++++
> board/isee/igep0020/igep0020.c | 129 ++++++++++++++++++++++
> board/isee/igep0020/igep0020.h | 156 +++++++++++++++++++++++++++
> boards.cfg | 1 +
> include/configs/igep0020.h | 230 ++++++++++++++++++++++++++++++++++++++++
> 7 files changed, 600 insertions(+), 0 deletions(-)
> create mode 100644 board/isee/igep0020/Makefile
> create mode 100644 board/isee/igep0020/config.mk
> create mode 100644 board/isee/igep0020/igep0020.c
> create mode 100644 board/isee/igep0020/igep0020.h
> create mode 100644 include/configs/igep0020.h
>
> diff --git a/MAKEALL b/MAKEALL
> index 1b506d6..78dce8b 100755
> --- a/MAKEALL
> +++ b/MAKEALL
> @@ -490,6 +490,7 @@ LIST_ARM11=" \
> LIST_ARMV7=" \
> am3517_evm \
> devkit8000 \
> + igep0020 \
> mx51evk \
> omap3_beagle \
> omap3_overo \
> diff --git a/board/isee/igep0020/Makefile b/board/isee/igep0020/Makefile
> new file mode 100644
> index 0000000..2f11879
> --- /dev/null
> +++ b/board/isee/igep0020/Makefile
> @@ -0,0 +1,49 @@
> +#
> +# (C) Copyright 2000, 2001, 2002
> +# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
> +#
> +# See file CREDITS for list of people who contributed to this
> +# project.
> +#
> +# This program is free software; you can redistribute it and/or
> +# modify it under the terms of the GNU General Public License as
> +# published by the Free Software Foundation; either version 2 of
> +# the License, or (at your option) any later version.
> +#
> +# This program is distributed in the hope that it will be useful,
> +# but WITHOUT ANY WARRANTY; without even the implied warranty of
> +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> +# GNU General Public License for more details.
> +#
> +# You should have received a copy of the GNU General Public License
> +# along with this program; if not, write to the Free Software
> +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> +# MA 02111-1307 USA
> +#
> +
> +include $(TOPDIR)/config.mk
> +
> +LIB = $(obj)lib$(BOARD).a
> +
> +COBJS := igep0020.o
> +
> +SRCS := $(COBJS:.o=.c)
> +OBJS := $(addprefix $(obj),$(COBJS))
> +
> +$(LIB): $(obj).depend $(OBJS)
> + $(AR) $(ARFLAGS) $@ $(OBJS)
> +
> +clean:
> + rm -f $(OBJS)
> +
> +distclean: clean
> + rm -f $(LIB) core *.bak $(obj).depend
> +
> +#########################################################################
> +
> +# defines $(obj).depend target
> +include $(SRCTREE)/rules.mk
> +
> +sinclude $(obj).depend
> +
> +#########################################################################
> diff --git a/board/isee/igep0020/config.mk b/board/isee/igep0020/config.mk
> new file mode 100644
> index 0000000..3ae6a40
> --- /dev/null
> +++ b/board/isee/igep0020/config.mk
> @@ -0,0 +1,34 @@
> +#
> +# (C) Copyright 2009
> +# ISEE 2007 SL, <www.iseebcn.com>
> +#
> +# IGEP0020 uses OMAP3 (ARM-CortexA8) cpu
> +# see http://www.ti.com/ for more information on Texas Instruments
> +#
> +# See file CREDITS for list of people who contributed to this
> +# project.
> +#
> +# This program is free software; you can redistribute it and/or
> +# modify it under the terms of the GNU General Public License as
> +# published by the Free Software Foundation; either version 2 of
> +# the License, or (at your option) any later version.
> +#
> +# This program is distributed in the hope that it will be useful,
> +# but WITHOUT ANY WARRANTY; without even the implied warranty of
> +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> +# GNU General Public License for more details.
> +#
> +# You should have received a copy of the GNU General Public License
> +# along with this program; if not, write to the Free Software
> +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> +# MA 02111-1307 USA
> +#
> +# Physical Address:
> +# 8000'0000 (bank0)
> +# A000/0000 (bank1)
> +# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
> +# (mem base + reserved)
> +
> +# For use with external or internal boots.
> +TEXT_BASE = 0x80008000
> +
> diff --git a/board/isee/igep0020/igep0020.c b/board/isee/igep0020/igep0020.c
> new file mode 100644
> index 0000000..f5b51e9
> --- /dev/null
> +++ b/board/isee/igep0020/igep0020.c
> @@ -0,0 +1,129 @@
> +/*
> + * (C) Copyright 2010
> + * ISEE 2007 SL, <www.iseebcn.com>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +#include <common.h>
> +#include <twl4030.h>
> +#include <asm/io.h>
> +#include <asm/arch/gpio.h>
> +#include <asm/arch/mem.h>
> +#include <asm/arch/mux.h>
> +#include <asm/arch/sys_proto.h>
> +#include <asm/mach-types.h>
> +#include "igep0020.h"
> +
> +/* GPMC definitions for LAN9221 chips */
> +static const u32 gpmc_lan_config[] = {
> + NET_LAN9221_GPMC_CONFIG1,
> + NET_LAN9221_GPMC_CONFIG2,
> + NET_LAN9221_GPMC_CONFIG3,
> + NET_LAN9221_GPMC_CONFIG4,
> + NET_LAN9221_GPMC_CONFIG5,
> + NET_LAN9221_GPMC_CONFIG6,
> +};
> +
> +/*
> + * Routine: board_init
> + * Description: Early hardware init.
> + */
> +int board_init(void)
> +{
> + DECLARE_GLOBAL_DATA_PTR;
> +
> + gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
> + /* board id for Linux */
> + gd->bd->bi_arch_number = MACH_TYPE_IGEP0020;
> + /* boot param addr */
> + gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
> +
> + return 0;
> +}
> +
> +/*
> + * Routine: setup_net_chip
> + * Description: Setting up the configuration GPMC registers specific to the
> + * Ethernet hardware.
> + */
> +#if defined(CONFIG_CMD_NET)
> +static void setup_net_chip(void)
> +{
> + struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
> +
> + enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[5], 0x2C000000,
> + GPMC_SIZE_16M);
> +
> + /* Enable off mode for NWE in PADCONF_GPMC_NWE register */
> + writew(readw(&ctrl_base ->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
Extra space after first &ctrl_base in line above.
> + /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
> + writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
> + /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
> + writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
> + &ctrl_base->gpmc_nadv_ale);
> +
> + /* Make GPIO 64 as output pin and send a magic pulse through it */
> + if (!omap_request_gpio(64)) {
> + omap_set_gpio_direction(64, 0);
> + omap_set_gpio_dataout(64, 1);
> + udelay(1);
> + omap_set_gpio_dataout(64, 0);
> + udelay(1);
> + omap_set_gpio_dataout(64, 1);
> + }
> +}
> +#endif
> +
> +/*
> + * Routine: misc_init_r
> + * Description: Configure board specific parts
> + */
> +int misc_init_r(void)
> +{
> + twl4030_power_init();
> +
> +#if defined(CONFIG_CMD_NET)
> + setup_net_chip();
> +#endif
> +
> + dieid_num_r();
> +
> + return 0;
> +}
> +
> +/*
> + * Routine: set_muxconf_regs
> + * Description: Setting up the configuration Mux registers specific to the
> + * hardware. Many pins need to be moved from protect to primary
> + * mode.
> + */
> +void set_muxconf_regs(void)
> +{
> + MUX_DEFAULT();
> +}
> +
> +int board_eth_init(bd_t *bis)
> +{
> + int rc = 0;
> +#ifdef CONFIG_SMC911X
> + rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
> +#endif
> + return rc;
> +}
> +
> diff --git a/board/isee/igep0020/igep0020.h b/board/isee/igep0020/igep0020.h
> new file mode 100644
> index 0000000..c08d758
> --- /dev/null
> +++ b/board/isee/igep0020/igep0020.h
> @@ -0,0 +1,156 @@
> +/*
> + * (C) Copyright 2010
> + * ISEE 2007 SL, <www.iseebcn.com>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +#ifndef _IGEP0020_H_
> +#define _IGEP0020_H_
> +
> +const omap3_sysinfo sysinfo = {
> + DDR_STACKED,
> + "IGEP v2 board",
> + "ONENAND",
> +};
> +
> +/* GPMC CS 5 connected to an SMSC LAN9221 ethernet controller */
> +#define NET_LAN9221_GPMC_CONFIG1 0x00001000
> +#define NET_LAN9221_GPMC_CONFIG2 0x00080701
> +#define NET_LAN9221_GPMC_CONFIG3 0x00020201
> +#define NET_LAN9221_GPMC_CONFIG4 0x08030703
> +#define NET_LAN9221_GPMC_CONFIG5 0x00060908
> +#define NET_LAN9221_GPMC_CONFIG6 0x87030000
> +#define NET_LAN9221_GPMC_CONFIG7 0x00000f6c
> +
> +static void setup_net_chip(void);
> +
> +/*
> + * IEN - Input Enable
> + * IDIS - Input Disable
> + * PTD - Pull type Down
> + * PTU - Pull type Up
> + * DIS - Pull type selection is inactive
> + * EN - Pull type selection is active
> + * M0 - Mode 0
> + * The commented string gives the final mux configuration for that pin
> + */
> +#define MUX_DEFAULT()\
> + MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /* SDRC_D0 */\
> + MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /* SDRC_D1 */\
> + MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /* SDRC_D2 */\
> + MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /* SDRC_D3 */\
> + MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /* SDRC_D4 */\
> + MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /* SDRC_D5 */\
> + MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /* SDRC_D6 */\
> + MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /* SDRC_D7 */\
> + MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /* SDRC_D8 */\
> + MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /* SDRC_D9 */\
> + MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /* SDRC_D10 */\
> + MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /* SDRC_D11 */\
> + MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /* SDRC_D12 */\
> + MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /* SDRC_D13 */\
> + MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /* SDRC_D14 */\
> + MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /* SDRC_D15 */\
> + MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /* SDRC_D16 */\
> + MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /* SDRC_D17 */\
> + MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /* SDRC_D18 */\
> + MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /* SDRC_D19 */\
> + MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /* SDRC_D20 */\
> + MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /* SDRC_D21 */\
> + MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /* SDRC_D22 */\
> + MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /* SDRC_D23 */\
> + MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /* SDRC_D24 */\
> + MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /* SDRC_D25 */\
> + MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /* SDRC_D26 */\
> + MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /* SDRC_D27 */\
> + MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /* SDRC_D28 */\
> + MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /* SDRC_D29 */\
> + MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /* SDRC_D30 */\
> + MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /* SDRC_D31 */\
> + MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /* SDRC_CLK */\
> + MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /* SDRC_DQS0 */\
> + MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /* SDRC_DQS1 */\
> + MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /* SDRC_DQS2 */\
> + MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /* SDRC_DQS3 */\
> + MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /* GPMC_A1 */\
> + MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /* GPMC_A2 */\
> + MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /* GPMC_A3 */\
> + MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /* GPMC_A4 */\
> + MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /* GPMC_A5 */\
> + MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /* GPMC_A6 */\
> + MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /* GPMC_A7 */\
> + MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /* GPMC_A8 */\
> + MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /* GPMC_A9 */\
> + MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /* GPMC_A10 */\
> + MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /* GPMC_D0 */\
> + MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /* GPMC_D1 */\
> + MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /* GPMC_D2 */\
> + MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /* GPMC_D3 */\
> + MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /* GPMC_D4 */\
> + MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /* GPMC_D5 */\
> + MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /* GPMC_D6 */\
> + MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /* GPMC_D7 */\
> + MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /* GPMC_D8 */\
> + MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /* GPMC_D9 */\
> + MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /* GPMC_D10 */\
> + MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /* GPMC_D11 */\
> + MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /* GPMC_D12 */\
> + MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /* GPMC_D13 */\
> + MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /* GPMC_D14 */\
> + MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /* GPMC_D15 */\
> + MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /* GPMC_nCS0 */\
> + MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /* GPMC_nCS1 */\
> + MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) /* GPIO_nCS2 */\
> + MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)) /* GPIO_nCS3 */\
> + MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | EN | M0)) /* GPMC_nCS4 */\
> + MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0)) /* GPMC_nCS5 */\
> + MUX_VAL(CP(GPMC_NCS6), (IDIS | PTU | EN | M0)) /* GPMC_nCS6 */\
> + MUX_VAL(CP(GPMC_NCS7), (IDIS | PTU | EN | M0)) /* GPMC_nCS7 */\
> + MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /* GPMC_CLK */\
> + MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) /* GPMC_nADV_ALE */\
> + MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) /* GPMC_nOE */\
> + MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) /* GPMC_nWE */\
> + MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0)) /* GPMC_nBE0_CLE */\
> + MUX_VAL(CP(GPMC_NBE1), (IEN | PTD | DIS | M0)) /* GPMC_nBE1 */\
> + MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) /* GPMC_nWP */\
> + MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /* GPMC_WAIT0 */\
> + MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | DIS | M4)) /* GPIO_64-ETH_NRST */\
> + MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) /* MMC1_CLK */\
> + MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /* MMC1_CMD */\
> + MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /* MMC1_DAT0 */\
> + MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /* MMC1_DAT1 */\
> + MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /* MMC1_DAT2 */\
> + MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /* MMC1_DAT3 */\
> + MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /* UART3_TX */\
> + MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) /* UART3_RX */\
> + MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /* I2C1_SCL */\
> + MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /* I2C1_SDA */\
> + MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /* I2C4_SCL */\
> + MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /* I2C4_SDA */\
> + MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /* SYS_32K */\
> + MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /* GPIO_2 */\
> + MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /* GPIO_3 */\
> + MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /* GPIO_4 */\
> + MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /* GPIO_5 */\
> + MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /* GPIO_6 */\
> + MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /* GPIO_7 */\
> + MUX_VAL(CP(SYS_BOOT6), (IEN | PTD | DIS | M4)) /* GPIO_8 */\
> + MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) /* SDRC_CKE0 */\
> + MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | EN | M0)) /* SDRC_CKE1 */
> +#endif
> diff --git a/boards.cfg b/boards.cfg
> index 202de1a..6f8db44 100644
> --- a/boards.cfg
> +++ b/boards.cfg
> @@ -262,6 +262,7 @@ omap4_panda arm armv7 panda ti omap4
> omap4_sdp4430 arm armv7 sdp4430 ti omap4
> am3517_evm arm armv7 am3517evm logicpd omap3
> devkit8000 arm armv7 devkit8000 timll omap3
> +igep0020 arm armv7 igep0020 isee omap3
> s5p_goni arm armv7 goni samsung s5pc1xx
> smdkc100 arm armv7 smdkc100 samsung s5pc1xx
> ixdpg425 arm ixp
> diff --git a/include/configs/igep0020.h b/include/configs/igep0020.h
> new file mode 100644
> index 0000000..a884c3e
> --- /dev/null
> +++ b/include/configs/igep0020.h
> @@ -0,0 +1,230 @@
> +/*
> + * (C) Copyright 2010
> + * ISEE 2007 SL, <www.iseebcn.com>
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#ifndef __CONFIG_H
> +#define __CONFIG_H
> +#include <asm/sizes.h>
> +
> +/*
> + * High Level Configuration Options
> + */
> +#define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */
> +#define CONFIG_OMAP 1 /* in a TI OMAP core */
> +#define CONFIG_OMAP34XX 1 /* which is a 34XX */
> +#define CONFIG_OMAP3430 1 /* which is in a 3430 */
> +#define CONFIG_OMAP3_IGEP0020 1 /* working with IGEP0020 */
> +
> +#define CONFIG_SDRC /* The chip has SDRC controller */
> +
> +#include <asm/arch/cpu.h>
> +#include <asm/arch/omap3.h>
> +
> +/*
> + * Display CPU and Board information
> + */
> +#define CONFIG_DISPLAY_CPUINFO 1
> +#define CONFIG_DISPLAY_BOARDINFO 1
> +
> +/* Clock Defines */
> +#define V_OSCK 26000000 /* Clock output from T2 */
> +#define V_SCLK (V_OSCK >> 1)
> +
> +#define CONFIG_MISC_INIT_R
> +
> +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
> +#define CONFIG_SETUP_MEMORY_TAGS 1
> +#define CONFIG_INITRD_TAG 1
> +#define CONFIG_REVISION_TAG 1
> +
> +/*
> + * NS16550 Configuration
> + */
> +
> +#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
> +
> +#define CONFIG_SYS_NS16550
> +#define CONFIG_SYS_NS16550_SERIAL
> +#define CONFIG_SYS_NS16550_REG_SIZE (-4)
> +#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
> +
> +/* select serial console configuration */
> +#define CONFIG_CONS_INDEX 3
> +#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
> +#define CONFIG_SERIAL3 3
> +
> +/* allow to overwrite serial and ethaddr */
> +#define CONFIG_ENV_OVERWRITE
> +#define CONFIG_BAUDRATE 115200
> +#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,115200}
Need a space after the 57600 comma.
> +#define CONFIG_MMC 1
> +#define CONFIG_OMAP3_MMC 1
> +#define CONFIG_DOS_PARTITION 1
> +
> +/* DDR */
> +#define CONFIG_OMAP3_NUMONYX_DDR 1
> +
> +/* USB */
> +#define CONFIG_MUSB_UDC 1
> +#define CONFIG_USB_OMAP3 1
> +#define CONFIG_TWL4030_USB 1
> +
> +/* USB device configuration */
> +#define CONFIG_USB_DEVICE 1
> +#define CONFIG_USB_TTY 1
> +#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
> +
> +/* Change these to suit your needs */
> +#define CONFIG_USBD_VENDORID 0x0451
> +#define CONFIG_USBD_PRODUCTID 0x5678
> +#define CONFIG_USBD_MANUFACTURER "Texas Instruments"
> +#define CONFIG_USBD_PRODUCT_NAME "IGEP"
> +
> +/* commands to include */
> +#include <config_cmd_default.h>
> +
> +#define CONFIG_CMD_CACHE
> +#define CONFIG_CMD_EXT2 /* EXT2 Support */
> +#define CONFIG_CMD_FAT /* FAT support */
> +#define CONFIG_CMD_I2C /* I2C serial bus support */
> +#define CONFIG_CMD_MMC /* MMC support */
> +#define CONFIG_CMD_ONENAND /* ONENAND support */
> +#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
> +#define CONFIG_CMD_DHCP
> +#define CONFIG_CMD_PING
> +#define CONFIG_CMD_NFS /* NFS support */
> +#define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */
> +#define CONFIG_MTD_DEVICE
> +
> +#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
> +#undef CONFIG_CMD_IMLS /* List all found images */
> +
> +#define CONFIG_SYS_NO_FLASH
> +#define CONFIG_HARD_I2C 1
> +#define CONFIG_SYS_I2C_SPEED 100000
> +#define CONFIG_SYS_I2C_SLAVE 1
> +#define CONFIG_SYS_I2C_BUS 0
> +#define CONFIG_SYS_I2C_BUS_SELECT 1
> +#define CONFIG_DRIVER_OMAP34XX_I2C 1
> +
> +/*
> + * TWL4030
> + */
> +#define CONFIG_TWL4030_POWER 1
> +
> +/* Environment information */
> +#define CONFIG_BOOTCOMMAND \
> + "mmc init 0 ; fatload mmc 0 0x80000000 setup.ini ; source \0"
> +
> +#define CONFIG_BOOTDELAY 3
> +
> +#define CONFIG_EXTRA_ENV_SETTINGS \
> + "usbtty=cdc_acm\0"
> +
> +#define CONFIG_AUTO_COMPLETE 1
> +
> +/*
> + * Miscellaneous configurable options
> + */
> +#define CONFIG_SYS_LONGHELP /* undef to save memory */
> +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
> +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
> +#define CONFIG_SYS_PROMPT "U-Boot # "
> +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
> +/* Print Buffer Size */
> +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
> + sizeof(CONFIG_SYS_PROMPT) + 16)
> +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
> +/* Boot Argument Buffer Size */
> +#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
> +
> +#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */
> + /* works on */
> +#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
> + 0x01F00000) /* 31MB */
> +
> +#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */
> + /* load address */
> +
> +#define CONFIG_SYS_MONITOR_LEN (256 << 10)
> +
> +/*
> + * OMAP3 has 12 GP timers, they can be driven by the system clock
> + * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
> + * This rate is divided by a local divisor.
> + */
> +#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
> +#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
> +#define CONFIG_SYS_HZ 1000
> +
> +/*
> + * Stack sizes
> + *
> + * The stack sizes are set up in start.S using the settings below
> + */
> +#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */
> +
> +/*
> + * Physical Memory Map
> + *
> + */
> +#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
> +#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
> +#define PHYS_SDRAM_1_SIZE (32 << 20) /*@least 32 meg */
> +#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
> +
> +/* SDRAM Bank Allocation method */
> +#define SDRC_R_B_C 1
> +
> +/*
> + * FLASH and environment organization
> + */
> +
> +#define PISMO1_ONEN_SIZE GPMC_SIZE_128M /* Configure the PISMO */
> +
> +#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
> +
> +#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
> +
> +#define CONFIG_ENV_IS_IN_ONENAND 1
> +#define CONFIG_ENV_SIZE (512 << 10) /* Total Size Environment */
> +#define CONFIG_ENV_ADDR ONENAND_ENV_OFFSET
> +
> +/*
> + * Size of malloc() pool
> + */
> +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
> +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes for initial data */
> +
> +/*
> + * SMSC911x Ethernet
> + */
> +#if defined(CONFIG_CMD_NET)
> +#define CONFIG_NET_MULTI
> +#define CONFIG_SMC911X
> +#define CONFIG_SMC911X_32_BIT
> +#define CONFIG_SMC911X_BASE 0x2C000000
> +#endif /* (CONFIG_CMD_NET) */
> +
> +/* additions for new relocation code, must added to all boards */
> +#undef CONFIG_SYS_ARM_WITHOUT_RELOC /* This board is tested with relocation support */
You should omit the 2 previous lines.
> +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
> +#define CONFIG_SYS_INIT_SP_ADDR (LOW_LEVEL_SRAM_STACK - CONFIG_SYS_GBL_DATA_SIZE)
> +
> +#endif /* __CONFIG_H */
Otherwise looks reasonable. I'll build & run test when I get some time
tomorrow or Monday.
Steve
^ permalink raw reply [flat|nested] 9+ messages in thread
* [U-Boot] [PATCH 3/3] OMAP3: Add support for the IGEP v2 board.
2010-10-11 19:48 [U-Boot] [PATCHv4 0/3] " Enric Balletbo i Serra
@ 2010-10-11 19:48 ` Enric Balletbo i Serra
2010-10-11 19:49 ` Enric Balletbò i Serra
0 siblings, 1 reply; 9+ messages in thread
From: Enric Balletbo i Serra @ 2010-10-11 19:48 UTC (permalink / raw)
To: u-boot
The IGEP v2 board is a low-cost, fan-less and industrial temperature
range single board computer that unleashes laptop-like performance and
expandability without the bulk, expense, or noise of typical desktop
machines. Its architecture shares much in common with other OMAP3 boards.
Signed-off-by: Enric Balletbo i Serra <eballetbo@gmail.com>
Acked-by: Steve Sakoman <steve.sakoman@linaro.org>
Tested-by: Steve Sakoman <steve.sakoman@linaro.org>
---
MAINTAINERS | 4 +
MAKEALL | 1 +
board/isee/igep0020/Makefile | 49 +++++++++
board/isee/igep0020/config.mk | 33 ++++++
board/isee/igep0020/igep0020.c | 129 ++++++++++++++++++++++
board/isee/igep0020/igep0020.h | 156 +++++++++++++++++++++++++++
boards.cfg | 1 +
include/configs/igep0020.h | 228 ++++++++++++++++++++++++++++++++++++++++
8 files changed, 601 insertions(+), 0 deletions(-)
create mode 100644 board/isee/igep0020/Makefile
create mode 100644 board/isee/igep0020/config.mk
create mode 100644 board/isee/igep0020/igep0020.c
create mode 100644 board/isee/igep0020/igep0020.h
create mode 100644 include/configs/igep0020.h
diff --git a/MAINTAINERS b/MAINTAINERS
index e003226..99728ae 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -818,6 +818,10 @@ Alex Z
lart SA1100
dnp1110 SA1110
+Enric Balletbo i Serra <eballetbo@iseebcn.com>
+
+ igep0020 ARM ARMV7 (OMAP3xx SoC)
+
-------------------------------------------------------------------------
Unknown / orphaned boards:
diff --git a/MAKEALL b/MAKEALL
index 1b506d6..78dce8b 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -490,6 +490,7 @@ LIST_ARM11=" \
LIST_ARMV7=" \
am3517_evm \
devkit8000 \
+ igep0020 \
mx51evk \
omap3_beagle \
omap3_overo \
diff --git a/board/isee/igep0020/Makefile b/board/isee/igep0020/Makefile
new file mode 100644
index 0000000..2f11879
--- /dev/null
+++ b/board/isee/igep0020/Makefile
@@ -0,0 +1,49 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS := igep0020.o
+
+SRCS := $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+ rm -f $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/isee/igep0020/config.mk b/board/isee/igep0020/config.mk
new file mode 100644
index 0000000..b8812f9
--- /dev/null
+++ b/board/isee/igep0020/config.mk
@@ -0,0 +1,33 @@
+#
+# (C) Copyright 2009
+# ISEE 2007 SL, <www.iseebcn.com>
+#
+# IGEP0020 uses OMAP3 (ARM-CortexA8) cpu
+# see http://www.ti.com/ for more information on Texas Instruments
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+# Physical Address:
+# 8000'0000 (bank0)
+# A000/0000 (bank1)
+# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
+# (mem base + reserved)
+
+# For use with external or internal boots.
+TEXT_BASE = 0x80008000
diff --git a/board/isee/igep0020/igep0020.c b/board/isee/igep0020/igep0020.c
new file mode 100644
index 0000000..3f7eda1
--- /dev/null
+++ b/board/isee/igep0020/igep0020.c
@@ -0,0 +1,129 @@
+/*
+ * (C) Copyright 2010
+ * ISEE 2007 SL, <www.iseebcn.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <netdev.h>
+#include <twl4030.h>
+#include <asm/io.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-types.h>
+#include "igep0020.h"
+
+/* GPMC definitions for LAN9221 chips */
+static const u32 gpmc_lan_config[] = {
+ NET_LAN9221_GPMC_CONFIG1,
+ NET_LAN9221_GPMC_CONFIG2,
+ NET_LAN9221_GPMC_CONFIG3,
+ NET_LAN9221_GPMC_CONFIG4,
+ NET_LAN9221_GPMC_CONFIG5,
+ NET_LAN9221_GPMC_CONFIG6,
+};
+
+/*
+ * Routine: board_init
+ * Description: Early hardware init.
+ */
+int board_init(void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
+ /* board id for Linux */
+ gd->bd->bi_arch_number = MACH_TYPE_IGEP0020;
+ /* boot param addr */
+ gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
+
+ return 0;
+}
+
+/*
+ * Routine: setup_net_chip
+ * Description: Setting up the configuration GPMC registers specific to the
+ * Ethernet hardware.
+ */
+#if defined(CONFIG_CMD_NET)
+static void setup_net_chip(void)
+{
+ struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
+
+ enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[5], 0x2C000000,
+ GPMC_SIZE_16M);
+
+ /* Enable off mode for NWE in PADCONF_GPMC_NWE register */
+ writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
+ /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
+ writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
+ /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
+ writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
+ &ctrl_base->gpmc_nadv_ale);
+
+ /* Make GPIO 64 as output pin and send a magic pulse through it */
+ if (!omap_request_gpio(64)) {
+ omap_set_gpio_direction(64, 0);
+ omap_set_gpio_dataout(64, 1);
+ udelay(1);
+ omap_set_gpio_dataout(64, 0);
+ udelay(1);
+ omap_set_gpio_dataout(64, 1);
+ }
+}
+#endif
+
+/*
+ * Routine: misc_init_r
+ * Description: Configure board specific parts
+ */
+int misc_init_r(void)
+{
+ twl4030_power_init();
+
+#if defined(CONFIG_CMD_NET)
+ setup_net_chip();
+#endif
+
+ dieid_num_r();
+
+ return 0;
+}
+
+/*
+ * Routine: set_muxconf_regs
+ * Description: Setting up the configuration Mux registers specific to the
+ * hardware. Many pins need to be moved from protect to primary
+ * mode.
+ */
+void set_muxconf_regs(void)
+{
+ MUX_DEFAULT();
+}
+
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_SMC911X
+ rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+#endif
+ return rc;
+}
diff --git a/board/isee/igep0020/igep0020.h b/board/isee/igep0020/igep0020.h
new file mode 100644
index 0000000..c08d758
--- /dev/null
+++ b/board/isee/igep0020/igep0020.h
@@ -0,0 +1,156 @@
+/*
+ * (C) Copyright 2010
+ * ISEE 2007 SL, <www.iseebcn.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _IGEP0020_H_
+#define _IGEP0020_H_
+
+const omap3_sysinfo sysinfo = {
+ DDR_STACKED,
+ "IGEP v2 board",
+ "ONENAND",
+};
+
+/* GPMC CS 5 connected to an SMSC LAN9221 ethernet controller */
+#define NET_LAN9221_GPMC_CONFIG1 0x00001000
+#define NET_LAN9221_GPMC_CONFIG2 0x00080701
+#define NET_LAN9221_GPMC_CONFIG3 0x00020201
+#define NET_LAN9221_GPMC_CONFIG4 0x08030703
+#define NET_LAN9221_GPMC_CONFIG5 0x00060908
+#define NET_LAN9221_GPMC_CONFIG6 0x87030000
+#define NET_LAN9221_GPMC_CONFIG7 0x00000f6c
+
+static void setup_net_chip(void);
+
+/*
+ * IEN - Input Enable
+ * IDIS - Input Disable
+ * PTD - Pull type Down
+ * PTU - Pull type Up
+ * DIS - Pull type selection is inactive
+ * EN - Pull type selection is active
+ * M0 - Mode 0
+ * The commented string gives the final mux configuration for that pin
+ */
+#define MUX_DEFAULT()\
+ MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /* SDRC_D0 */\
+ MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /* SDRC_D1 */\
+ MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /* SDRC_D2 */\
+ MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /* SDRC_D3 */\
+ MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /* SDRC_D4 */\
+ MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /* SDRC_D5 */\
+ MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /* SDRC_D6 */\
+ MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /* SDRC_D7 */\
+ MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /* SDRC_D8 */\
+ MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /* SDRC_D9 */\
+ MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /* SDRC_D10 */\
+ MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /* SDRC_D11 */\
+ MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /* SDRC_D12 */\
+ MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /* SDRC_D13 */\
+ MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /* SDRC_D14 */\
+ MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /* SDRC_D15 */\
+ MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /* SDRC_D16 */\
+ MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /* SDRC_D17 */\
+ MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /* SDRC_D18 */\
+ MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /* SDRC_D19 */\
+ MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /* SDRC_D20 */\
+ MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /* SDRC_D21 */\
+ MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /* SDRC_D22 */\
+ MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /* SDRC_D23 */\
+ MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /* SDRC_D24 */\
+ MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /* SDRC_D25 */\
+ MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /* SDRC_D26 */\
+ MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /* SDRC_D27 */\
+ MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /* SDRC_D28 */\
+ MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /* SDRC_D29 */\
+ MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /* SDRC_D30 */\
+ MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /* SDRC_D31 */\
+ MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /* SDRC_CLK */\
+ MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /* SDRC_DQS0 */\
+ MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /* SDRC_DQS1 */\
+ MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /* SDRC_DQS2 */\
+ MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /* SDRC_DQS3 */\
+ MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /* GPMC_A1 */\
+ MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /* GPMC_A2 */\
+ MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /* GPMC_A3 */\
+ MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /* GPMC_A4 */\
+ MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /* GPMC_A5 */\
+ MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /* GPMC_A6 */\
+ MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /* GPMC_A7 */\
+ MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /* GPMC_A8 */\
+ MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /* GPMC_A9 */\
+ MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /* GPMC_A10 */\
+ MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /* GPMC_D0 */\
+ MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /* GPMC_D1 */\
+ MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /* GPMC_D2 */\
+ MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /* GPMC_D3 */\
+ MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /* GPMC_D4 */\
+ MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /* GPMC_D5 */\
+ MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /* GPMC_D6 */\
+ MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /* GPMC_D7 */\
+ MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /* GPMC_D8 */\
+ MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /* GPMC_D9 */\
+ MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /* GPMC_D10 */\
+ MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /* GPMC_D11 */\
+ MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /* GPMC_D12 */\
+ MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /* GPMC_D13 */\
+ MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /* GPMC_D14 */\
+ MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /* GPMC_D15 */\
+ MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /* GPMC_nCS0 */\
+ MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /* GPMC_nCS1 */\
+ MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) /* GPIO_nCS2 */\
+ MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)) /* GPIO_nCS3 */\
+ MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | EN | M0)) /* GPMC_nCS4 */\
+ MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0)) /* GPMC_nCS5 */\
+ MUX_VAL(CP(GPMC_NCS6), (IDIS | PTU | EN | M0)) /* GPMC_nCS6 */\
+ MUX_VAL(CP(GPMC_NCS7), (IDIS | PTU | EN | M0)) /* GPMC_nCS7 */\
+ MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /* GPMC_CLK */\
+ MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) /* GPMC_nADV_ALE */\
+ MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) /* GPMC_nOE */\
+ MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) /* GPMC_nWE */\
+ MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0)) /* GPMC_nBE0_CLE */\
+ MUX_VAL(CP(GPMC_NBE1), (IEN | PTD | DIS | M0)) /* GPMC_nBE1 */\
+ MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) /* GPMC_nWP */\
+ MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /* GPMC_WAIT0 */\
+ MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | DIS | M4)) /* GPIO_64-ETH_NRST */\
+ MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) /* MMC1_CLK */\
+ MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /* MMC1_CMD */\
+ MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /* MMC1_DAT0 */\
+ MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /* MMC1_DAT1 */\
+ MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /* MMC1_DAT2 */\
+ MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /* MMC1_DAT3 */\
+ MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /* UART3_TX */\
+ MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) /* UART3_RX */\
+ MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /* I2C1_SCL */\
+ MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /* I2C1_SDA */\
+ MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /* I2C4_SCL */\
+ MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /* I2C4_SDA */\
+ MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /* SYS_32K */\
+ MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /* GPIO_2 */\
+ MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /* GPIO_3 */\
+ MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /* GPIO_4 */\
+ MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /* GPIO_5 */\
+ MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /* GPIO_6 */\
+ MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /* GPIO_7 */\
+ MUX_VAL(CP(SYS_BOOT6), (IEN | PTD | DIS | M4)) /* GPIO_8 */\
+ MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) /* SDRC_CKE0 */\
+ MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | EN | M0)) /* SDRC_CKE1 */
+#endif
diff --git a/boards.cfg b/boards.cfg
index 202de1a..6f8db44 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -262,6 +262,7 @@ omap4_panda arm armv7 panda ti omap4
omap4_sdp4430 arm armv7 sdp4430 ti omap4
am3517_evm arm armv7 am3517evm logicpd omap3
devkit8000 arm armv7 devkit8000 timll omap3
+igep0020 arm armv7 igep0020 isee omap3
s5p_goni arm armv7 goni samsung s5pc1xx
smdkc100 arm armv7 smdkc100 samsung s5pc1xx
ixdpg425 arm ixp
diff --git a/include/configs/igep0020.h b/include/configs/igep0020.h
new file mode 100644
index 0000000..34e8a57
--- /dev/null
+++ b/include/configs/igep0020.h
@@ -0,0 +1,228 @@
+/*
+ * (C) Copyright 2010
+ * ISEE 2007 SL, <www.iseebcn.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+#include <asm/sizes.h>
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */
+#define CONFIG_OMAP 1 /* in a TI OMAP core */
+#define CONFIG_OMAP34XX 1 /* which is a 34XX */
+#define CONFIG_OMAP3430 1 /* which is in a 3430 */
+#define CONFIG_OMAP3_IGEP0020 1 /* working with IGEP0020 */
+
+#define CONFIG_SDRC /* The chip has SDRC controller */
+
+#include <asm/arch/cpu.h>
+#include <asm/arch/omap3.h>
+
+/*
+ * Display CPU and Board information
+ */
+#define CONFIG_DISPLAY_CPUINFO 1
+#define CONFIG_DISPLAY_BOARDINFO 1
+
+/* Clock Defines */
+#define V_OSCK 26000000 /* Clock output from T2 */
+#define V_SCLK (V_OSCK >> 1)
+
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG 1
+#define CONFIG_REVISION_TAG 1
+
+/*
+ * NS16550 Configuration
+ */
+
+#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
+
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE (-4)
+#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
+
+/* select serial console configuration */
+#define CONFIG_CONS_INDEX 3
+#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
+#define CONFIG_SERIAL3 3
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200}
+#define CONFIG_MMC 1
+#define CONFIG_OMAP3_MMC 1
+#define CONFIG_DOS_PARTITION 1
+
+/* DDR */
+#define CONFIG_OMAP3_NUMONYX_DDR 1
+
+/* USB */
+#define CONFIG_MUSB_UDC 1
+#define CONFIG_USB_OMAP3 1
+#define CONFIG_TWL4030_USB 1
+
+/* USB device configuration */
+#define CONFIG_USB_DEVICE 1
+#define CONFIG_USB_TTY 1
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
+
+/* Change these to suit your needs */
+#define CONFIG_USBD_VENDORID 0x0451
+#define CONFIG_USBD_PRODUCTID 0x5678
+#define CONFIG_USBD_MANUFACTURER "Texas Instruments"
+#define CONFIG_USBD_PRODUCT_NAME "IGEP"
+
+/* commands to include */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_EXT2 /* EXT2 Support */
+#define CONFIG_CMD_FAT /* FAT support */
+#define CONFIG_CMD_I2C /* I2C serial bus support */
+#define CONFIG_CMD_MMC /* MMC support */
+#define CONFIG_CMD_ONENAND /* ONENAND support */
+#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_NFS /* NFS support */
+#define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */
+#define CONFIG_MTD_DEVICE
+
+#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
+#undef CONFIG_CMD_IMLS /* List all found images */
+
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_HARD_I2C 1
+#define CONFIG_SYS_I2C_SPEED 100000
+#define CONFIG_SYS_I2C_SLAVE 1
+#define CONFIG_SYS_I2C_BUS 0
+#define CONFIG_SYS_I2C_BUS_SELECT 1
+#define CONFIG_DRIVER_OMAP34XX_I2C 1
+
+/*
+ * TWL4030
+ */
+#define CONFIG_TWL4030_POWER 1
+
+/* Environment information */
+#define CONFIG_BOOTCOMMAND \
+ "mmc init 0 ; fatload mmc 0 0x80000000 setup.ini ; source \0"
+
+#define CONFIG_BOOTDELAY 3
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "usbtty=cdc_acm\0"
+
+#define CONFIG_AUTO_COMPLETE 1
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_PROMPT "U-Boot # "
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
+
+#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */
+ /* works on */
+#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
+ 0x01F00000) /* 31MB */
+
+#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */
+ /* load address */
+
+#define CONFIG_SYS_MONITOR_LEN (256 << 10)
+
+/*
+ * OMAP3 has 12 GP timers, they can be driven by the system clock
+ * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
+ * This rate is divided by a local divisor.
+ */
+#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
+#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
+#define CONFIG_SYS_HZ 1000
+
+/*
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */
+
+/*
+ * Physical Memory Map
+ *
+ */
+#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
+#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
+#define PHYS_SDRAM_1_SIZE (32 << 20) /*@least 32 meg */
+#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
+
+/* SDRAM Bank Allocation method */
+#define SDRC_R_B_C 1
+
+/*
+ * FLASH and environment organization
+ */
+
+#define PISMO1_ONEN_SIZE GPMC_SIZE_128M /* Configure the PISMO */
+
+#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
+
+#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
+
+#define CONFIG_ENV_IS_IN_ONENAND 1
+#define CONFIG_ENV_SIZE (512 << 10) /* Total Size Environment */
+#define CONFIG_ENV_ADDR ONENAND_ENV_OFFSET
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
+#define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes for initial data */
+
+/*
+ * SMSC911x Ethernet
+ */
+#if defined(CONFIG_CMD_NET)
+#define CONFIG_NET_MULTI
+#define CONFIG_SMC911X
+#define CONFIG_SMC911X_32_BIT
+#define CONFIG_SMC911X_BASE 0x2C000000
+#endif /* (CONFIG_CMD_NET) */
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_SP_ADDR (LOW_LEVEL_SRAM_STACK - CONFIG_SYS_GBL_DATA_SIZE)
+
+#endif /* __CONFIG_H */
--
1.7.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [U-Boot] [PATCH 3/3] OMAP3: Add support for the IGEP v2 board.
2010-10-11 19:48 ` [U-Boot] [PATCH 3/3] OMAP3: " Enric Balletbo i Serra
@ 2010-10-11 19:49 ` Enric Balletbò i Serra
0 siblings, 0 replies; 9+ messages in thread
From: Enric Balletbò i Serra @ 2010-10-11 19:49 UTC (permalink / raw)
To: u-boot
Sorry, this is the version 4
2010/10/11 Enric Balletbo i Serra <eballetbo@gmail.com>:
> The IGEP v2 board is a low-cost, fan-less and industrial temperature
> range single board computer that unleashes laptop-like performance and
> expandability without the bulk, expense, or noise of typical desktop
> machines. Its architecture shares much in common with other OMAP3 boards.
>
> Signed-off-by: Enric Balletbo i Serra <eballetbo@gmail.com>
> Acked-by: Steve Sakoman <steve.sakoman@linaro.org>
> Tested-by: Steve Sakoman <steve.sakoman@linaro.org>
> ---
> ?MAINTAINERS ? ? ? ? ? ? ? ? ? ?| ? ?4 +
> ?MAKEALL ? ? ? ? ? ? ? ? ? ? ? ?| ? ?1 +
> ?board/isee/igep0020/Makefile ? | ? 49 +++++++++
> ?board/isee/igep0020/config.mk ?| ? 33 ++++++
> ?board/isee/igep0020/igep0020.c | ?129 ++++++++++++++++++++++
> ?board/isee/igep0020/igep0020.h | ?156 +++++++++++++++++++++++++++
> ?boards.cfg ? ? ? ? ? ? ? ? ? ? | ? ?1 +
> ?include/configs/igep0020.h ? ? | ?228 ++++++++++++++++++++++++++++++++++++++++
> ?8 files changed, 601 insertions(+), 0 deletions(-)
> ?create mode 100644 board/isee/igep0020/Makefile
> ?create mode 100644 board/isee/igep0020/config.mk
> ?create mode 100644 board/isee/igep0020/igep0020.c
> ?create mode 100644 board/isee/igep0020/igep0020.h
> ?create mode 100644 include/configs/igep0020.h
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index e003226..99728ae 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -818,6 +818,10 @@ Alex Z
> ? ? ? ?lart ? ? ? ? ? ?SA1100
> ? ? ? ?dnp1110 ? ? ? ? SA1110
>
> +Enric Balletbo i Serra <eballetbo@iseebcn.com>
> +
> + ? ? ? igep0020 ? ? ? ?ARM ARMV7 (OMAP3xx SoC)
> +
> ?-------------------------------------------------------------------------
>
> ?Unknown / orphaned boards:
> diff --git a/MAKEALL b/MAKEALL
> index 1b506d6..78dce8b 100755
> --- a/MAKEALL
> +++ b/MAKEALL
> @@ -490,6 +490,7 @@ LIST_ARM11=" ? ? ? ? ? ? ? ? ? ? ? ?\
> ?LIST_ARMV7=" ? ? ? ? ? \
> ? ? ? ?am3517_evm ? ? ? ? ? ? ?\
> ? ? ? ?devkit8000 ? ? ? ? ? ? ?\
> + ? ? ? igep0020 ? ? ? ? ? ? ? ?\
> ? ? ? ?mx51evk ? ? ? ? ? ? ? ? \
> ? ? ? ?omap3_beagle ? ? ? ? ? ?\
> ? ? ? ?omap3_overo ? ? ? ? ? ? \
> diff --git a/board/isee/igep0020/Makefile b/board/isee/igep0020/Makefile
> new file mode 100644
> index 0000000..2f11879
> --- /dev/null
> +++ b/board/isee/igep0020/Makefile
> @@ -0,0 +1,49 @@
> +#
> +# (C) Copyright 2000, 2001, 2002
> +# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
> +#
> +# See file CREDITS for list of people who contributed to this
> +# project.
> +#
> +# This program is free software; you can redistribute it and/or
> +# modify it under the terms of the GNU General Public License as
> +# published by the Free Software Foundation; either version 2 of
> +# the License, or (at your option) any later version.
> +#
> +# This program is distributed in the hope that it will be useful,
> +# but WITHOUT ANY WARRANTY; without even the implied warranty of
> +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. ?See the
> +# GNU General Public License for more details.
> +#
> +# You should have received a copy of the GNU General Public License
> +# along with this program; if not, write to the Free Software
> +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> +# MA 02111-1307 USA
> +#
> +
> +include $(TOPDIR)/config.mk
> +
> +LIB ? ?= $(obj)lib$(BOARD).a
> +
> +COBJS ?:= igep0020.o
> +
> +SRCS ? := $(COBJS:.o=.c)
> +OBJS ? := $(addprefix $(obj),$(COBJS))
> +
> +$(LIB): ? ? ? ?$(obj).depend $(OBJS)
> + ? ? ? $(AR) $(ARFLAGS) $@ $(OBJS)
> +
> +clean:
> + ? ? ? rm -f $(OBJS)
> +
> +distclean: ? ? clean
> + ? ? ? rm -f $(LIB) core *.bak $(obj).depend
> +
> +#########################################################################
> +
> +# defines $(obj).depend target
> +include $(SRCTREE)/rules.mk
> +
> +sinclude $(obj).depend
> +
> +#########################################################################
> diff --git a/board/isee/igep0020/config.mk b/board/isee/igep0020/config.mk
> new file mode 100644
> index 0000000..b8812f9
> --- /dev/null
> +++ b/board/isee/igep0020/config.mk
> @@ -0,0 +1,33 @@
> +#
> +# (C) Copyright 2009
> +# ISEE 2007 SL, <www.iseebcn.com>
> +#
> +# IGEP0020 uses OMAP3 (ARM-CortexA8) cpu
> +# see http://www.ti.com/ for more information on Texas Instruments
> +#
> +# See file CREDITS for list of people who contributed to this
> +# project.
> +#
> +# This program is free software; you can redistribute it and/or
> +# modify it under the terms of the GNU General Public License as
> +# published by the Free Software Foundation; either version 2 of
> +# the License, or (at your option) any later version.
> +#
> +# This program is distributed in the hope that it will be useful,
> +# but WITHOUT ANY WARRANTY; without even the implied warranty of
> +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. ?See the
> +# GNU General Public License for more details.
> +#
> +# You should have received a copy of the GNU General Public License
> +# along with this program; if not, write to the Free Software
> +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> +# MA 02111-1307 USA
> +#
> +# Physical Address:
> +# 8000'0000 (bank0)
> +# A000/0000 (bank1)
> +# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
> +# (mem base + reserved)
> +
> +# For use with external or internal boots.
> +TEXT_BASE = 0x80008000
> diff --git a/board/isee/igep0020/igep0020.c b/board/isee/igep0020/igep0020.c
> new file mode 100644
> index 0000000..3f7eda1
> --- /dev/null
> +++ b/board/isee/igep0020/igep0020.c
> @@ -0,0 +1,129 @@
> +/*
> + * (C) Copyright 2010
> + * ISEE 2007 SL, <www.iseebcn.com>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. ?See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +#include <common.h>
> +#include <netdev.h>
> +#include <twl4030.h>
> +#include <asm/io.h>
> +#include <asm/arch/gpio.h>
> +#include <asm/arch/mem.h>
> +#include <asm/arch/mux.h>
> +#include <asm/arch/sys_proto.h>
> +#include <asm/mach-types.h>
> +#include "igep0020.h"
> +
> +/* GPMC definitions for LAN9221 chips */
> +static const u32 gpmc_lan_config[] = {
> + ? ?NET_LAN9221_GPMC_CONFIG1,
> + ? ?NET_LAN9221_GPMC_CONFIG2,
> + ? ?NET_LAN9221_GPMC_CONFIG3,
> + ? ?NET_LAN9221_GPMC_CONFIG4,
> + ? ?NET_LAN9221_GPMC_CONFIG5,
> + ? ?NET_LAN9221_GPMC_CONFIG6,
> +};
> +
> +/*
> + * Routine: board_init
> + * Description: Early hardware init.
> + */
> +int board_init(void)
> +{
> + ? ? ? DECLARE_GLOBAL_DATA_PTR;
> +
> + ? ? ? gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
> + ? ? ? /* board id for Linux */
> + ? ? ? gd->bd->bi_arch_number = MACH_TYPE_IGEP0020;
> + ? ? ? /* boot param addr */
> + ? ? ? gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
> +
> + ? ? ? return 0;
> +}
> +
> +/*
> + * Routine: setup_net_chip
> + * Description: Setting up the configuration GPMC registers specific to the
> + * ? ? ? ? ? ? Ethernet hardware.
> + */
> +#if defined(CONFIG_CMD_NET)
> +static void setup_net_chip(void)
> +{
> + ? ? ? struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
> +
> + ? ? ? enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[5], 0x2C000000,
> + ? ? ? ? ? ? ? ? ? ? ? GPMC_SIZE_16M);
> +
> + ? ? ? /* Enable off mode for NWE in PADCONF_GPMC_NWE register */
> + ? ? ? writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
> + ? ? ? /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
> + ? ? ? writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
> + ? ? ? /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
> + ? ? ? writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
> + ? ? ? ? ? ? ? &ctrl_base->gpmc_nadv_ale);
> +
> + ? ? ? /* Make GPIO 64 as output pin and send a magic pulse through it */
> + ? ? ? if (!omap_request_gpio(64)) {
> + ? ? ? ? ? ? ? omap_set_gpio_direction(64, 0);
> + ? ? ? ? ? ? ? omap_set_gpio_dataout(64, 1);
> + ? ? ? ? ? ? ? udelay(1);
> + ? ? ? ? ? ? ? omap_set_gpio_dataout(64, 0);
> + ? ? ? ? ? ? ? udelay(1);
> + ? ? ? ? ? ? ? omap_set_gpio_dataout(64, 1);
> + ? ? ? }
> +}
> +#endif
> +
> +/*
> + * Routine: misc_init_r
> + * Description: Configure board specific parts
> + */
> +int misc_init_r(void)
> +{
> + ? ? ? twl4030_power_init();
> +
> +#if defined(CONFIG_CMD_NET)
> + ? ? ? setup_net_chip();
> +#endif
> +
> + ? ? ? dieid_num_r();
> +
> + ? ? ? return 0;
> +}
> +
> +/*
> + * Routine: set_muxconf_regs
> + * Description: Setting up the configuration Mux registers specific to the
> + * ? ? ? ? ? ? hardware. Many pins need to be moved from protect to primary
> + * ? ? ? ? ? ? mode.
> + */
> +void set_muxconf_regs(void)
> +{
> + ? ? ? MUX_DEFAULT();
> +}
> +
> +int board_eth_init(bd_t *bis)
> +{
> + ? ? ? int rc = 0;
> +#ifdef CONFIG_SMC911X
> + ? ? ? rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
> +#endif
> + ? ? ? return rc;
> +}
> diff --git a/board/isee/igep0020/igep0020.h b/board/isee/igep0020/igep0020.h
> new file mode 100644
> index 0000000..c08d758
> --- /dev/null
> +++ b/board/isee/igep0020/igep0020.h
> @@ -0,0 +1,156 @@
> +/*
> + * (C) Copyright 2010
> + * ISEE 2007 SL, <www.iseebcn.com>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. ?See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +#ifndef _IGEP0020_H_
> +#define _IGEP0020_H_
> +
> +const omap3_sysinfo sysinfo = {
> + ? ? ? DDR_STACKED,
> + ? ? ? "IGEP v2 board",
> + ? ? ? "ONENAND",
> +};
> +
> +/* GPMC CS 5 connected to an SMSC LAN9221 ethernet controller */
> +#define NET_LAN9221_GPMC_CONFIG1 ? ?0x00001000
> +#define NET_LAN9221_GPMC_CONFIG2 ? ?0x00080701
> +#define NET_LAN9221_GPMC_CONFIG3 ? ?0x00020201
> +#define NET_LAN9221_GPMC_CONFIG4 ? ?0x08030703
> +#define NET_LAN9221_GPMC_CONFIG5 ? ?0x00060908
> +#define NET_LAN9221_GPMC_CONFIG6 ? ?0x87030000
> +#define NET_LAN9221_GPMC_CONFIG7 ? ?0x00000f6c
> +
> +static void setup_net_chip(void);
> +
> +/*
> + * IEN ?- Input Enable
> + * IDIS - Input Disable
> + * PTD ?- Pull type Down
> + * PTU ?- Pull type Up
> + * DIS ?- Pull type selection is inactive
> + * EN ? - Pull type selection is active
> + * M0 ? - Mode 0
> + * The commented string gives the final mux configuration for that pin
> + */
> +#define MUX_DEFAULT()\
> + ? ? ? MUX_VAL(CP(SDRC_D0), ? ? ? ?(IEN ?| PTD | DIS | M0)) /* SDRC_D0 */\
> + ? ? ? MUX_VAL(CP(SDRC_D1), ? ? ? ?(IEN ?| PTD | DIS | M0)) /* SDRC_D1 */\
> + ? ? ? MUX_VAL(CP(SDRC_D2), ? ? ? ?(IEN ?| PTD | DIS | M0)) /* SDRC_D2 */\
> + ? ? ? MUX_VAL(CP(SDRC_D3), ? ? ? ?(IEN ?| PTD | DIS | M0)) /* SDRC_D3 */\
> + ? ? ? MUX_VAL(CP(SDRC_D4), ? ? ? ?(IEN ?| PTD | DIS | M0)) /* SDRC_D4 */\
> + ? ? ? MUX_VAL(CP(SDRC_D5), ? ? ? ?(IEN ?| PTD | DIS | M0)) /* SDRC_D5 */\
> + ? ? ? MUX_VAL(CP(SDRC_D6), ? ? ? ?(IEN ?| PTD | DIS | M0)) /* SDRC_D6 */\
> + ? ? ? MUX_VAL(CP(SDRC_D7), ? ? ? ?(IEN ?| PTD | DIS | M0)) /* SDRC_D7 */\
> + ? ? ? MUX_VAL(CP(SDRC_D8), ? ? ? ?(IEN ?| PTD | DIS | M0)) /* SDRC_D8 */\
> + ? ? ? MUX_VAL(CP(SDRC_D9), ? ? ? ?(IEN ?| PTD | DIS | M0)) /* SDRC_D9 */\
> + ? ? ? MUX_VAL(CP(SDRC_D10), ? ? ? (IEN ?| PTD | DIS | M0)) /* SDRC_D10 */\
> + ? ? ? MUX_VAL(CP(SDRC_D11), ? ? ? (IEN ?| PTD | DIS | M0)) /* SDRC_D11 */\
> + ? ? ? MUX_VAL(CP(SDRC_D12), ? ? ? (IEN ?| PTD | DIS | M0)) /* SDRC_D12 */\
> + ? ? ? MUX_VAL(CP(SDRC_D13), ? ? ? (IEN ?| PTD | DIS | M0)) /* SDRC_D13 */\
> + ? ? ? MUX_VAL(CP(SDRC_D14), ? ? ? (IEN ?| PTD | DIS | M0)) /* SDRC_D14 */\
> + ? ? ? MUX_VAL(CP(SDRC_D15), ? ? ? (IEN ?| PTD | DIS | M0)) /* SDRC_D15 */\
> + ? ? ? MUX_VAL(CP(SDRC_D16), ? ? ? (IEN ?| PTD | DIS | M0)) /* SDRC_D16 */\
> + ? ? ? MUX_VAL(CP(SDRC_D17), ? ? ? (IEN ?| PTD | DIS | M0)) /* SDRC_D17 */\
> + ? ? ? MUX_VAL(CP(SDRC_D18), ? ? ? (IEN ?| PTD | DIS | M0)) /* SDRC_D18 */\
> + ? ? ? MUX_VAL(CP(SDRC_D19), ? ? ? (IEN ?| PTD | DIS | M0)) /* SDRC_D19 */\
> + ? ? ? MUX_VAL(CP(SDRC_D20), ? ? ? (IEN ?| PTD | DIS | M0)) /* SDRC_D20 */\
> + ? ? ? MUX_VAL(CP(SDRC_D21), ? ? ? (IEN ?| PTD | DIS | M0)) /* SDRC_D21 */\
> + ? ? ? MUX_VAL(CP(SDRC_D22), ? ? ? (IEN ?| PTD | DIS | M0)) /* SDRC_D22 */\
> + ? ? ? MUX_VAL(CP(SDRC_D23), ? ? ? (IEN ?| PTD | DIS | M0)) /* SDRC_D23 */\
> + ? ? ? MUX_VAL(CP(SDRC_D24), ? ? ? (IEN ?| PTD | DIS | M0)) /* SDRC_D24 */\
> + ? ? ? MUX_VAL(CP(SDRC_D25), ? ? ? (IEN ?| PTD | DIS | M0)) /* SDRC_D25 */\
> + ? ? ? MUX_VAL(CP(SDRC_D26), ? ? ? (IEN ?| PTD | DIS | M0)) /* SDRC_D26 */\
> + ? ? ? MUX_VAL(CP(SDRC_D27), ? ? ? (IEN ?| PTD | DIS | M0)) /* SDRC_D27 */\
> + ? ? ? MUX_VAL(CP(SDRC_D28), ? ? ? (IEN ?| PTD | DIS | M0)) /* SDRC_D28 */\
> + ? ? ? MUX_VAL(CP(SDRC_D29), ? ? ? (IEN ?| PTD | DIS | M0)) /* SDRC_D29 */\
> + ? ? ? MUX_VAL(CP(SDRC_D30), ? ? ? (IEN ?| PTD | DIS | M0)) /* SDRC_D30 */\
> + ? ? ? MUX_VAL(CP(SDRC_D31), ? ? ? (IEN ?| PTD | DIS | M0)) /* SDRC_D31 */\
> + ? ? ? MUX_VAL(CP(SDRC_CLK), ? ? ? (IEN ?| PTD | DIS | M0)) /* SDRC_CLK */\
> + ? ? ? MUX_VAL(CP(SDRC_DQS0), ? ? ?(IEN ?| PTD | DIS | M0)) /* SDRC_DQS0 */\
> + ? ? ? MUX_VAL(CP(SDRC_DQS1), ? ? ?(IEN ?| PTD | DIS | M0)) /* SDRC_DQS1 */\
> + ? ? ? MUX_VAL(CP(SDRC_DQS2), ? ? ?(IEN ?| PTD | DIS | M0)) /* SDRC_DQS2 */\
> + ? ? ? MUX_VAL(CP(SDRC_DQS3), ? ? ?(IEN ?| PTD | DIS | M0)) /* SDRC_DQS3 */\
> + ? ? ? MUX_VAL(CP(GPMC_A1), ? ? ? ?(IDIS | PTD | DIS | M0)) /* GPMC_A1 */\
> + ? ? ? MUX_VAL(CP(GPMC_A2), ? ? ? ?(IDIS | PTD | DIS | M0)) /* GPMC_A2 */\
> + ? ? ? MUX_VAL(CP(GPMC_A3), ? ? ? ?(IDIS | PTD | DIS | M0)) /* GPMC_A3 */\
> + ? ? ? MUX_VAL(CP(GPMC_A4), ? ? ? ?(IDIS | PTD | DIS | M0)) /* GPMC_A4 */\
> + ? ? ? MUX_VAL(CP(GPMC_A5), ? ? ? ?(IDIS | PTD | DIS | M0)) /* GPMC_A5 */\
> + ? ? ? MUX_VAL(CP(GPMC_A6), ? ? ? ?(IDIS | PTD | DIS | M0)) /* GPMC_A6 */\
> + ? ? ? MUX_VAL(CP(GPMC_A7), ? ? ? ?(IDIS | PTD | DIS | M0)) /* GPMC_A7 */\
> + ? ? ? MUX_VAL(CP(GPMC_A8), ? ? ? ?(IDIS | PTD | DIS | M0)) /* GPMC_A8 */\
> + ? ? ? MUX_VAL(CP(GPMC_A9), ? ? ? ?(IDIS | PTD | DIS | M0)) /* GPMC_A9 */\
> + ? ? ? MUX_VAL(CP(GPMC_A10), ? ? ? (IDIS | PTD | DIS | M0)) /* GPMC_A10 */\
> + ? ? ? MUX_VAL(CP(GPMC_D0), ? ? ? ?(IEN ?| PTD | DIS | M0)) /* GPMC_D0 */\
> + ? ? ? MUX_VAL(CP(GPMC_D1), ? ? ? ?(IEN ?| PTD | DIS | M0)) /* GPMC_D1 */\
> + ? ? ? MUX_VAL(CP(GPMC_D2), ? ? ? ?(IEN ?| PTD | DIS | M0)) /* GPMC_D2 */\
> + ? ? ? MUX_VAL(CP(GPMC_D3), ? ? ? ?(IEN ?| PTD | DIS | M0)) /* GPMC_D3 */\
> + ? ? ? MUX_VAL(CP(GPMC_D4), ? ? ? ?(IEN ?| PTD | DIS | M0)) /* GPMC_D4 */\
> + ? ? ? MUX_VAL(CP(GPMC_D5), ? ? ? ?(IEN ?| PTD | DIS | M0)) /* GPMC_D5 */\
> + ? ? ? MUX_VAL(CP(GPMC_D6), ? ? ? ?(IEN ?| PTD | DIS | M0)) /* GPMC_D6 */\
> + ? ? ? MUX_VAL(CP(GPMC_D7), ? ? ? ?(IEN ?| PTD | DIS | M0)) /* GPMC_D7 */\
> + ? ? ? MUX_VAL(CP(GPMC_D8), ? ? ? ?(IEN ?| PTD | DIS | M0)) /* GPMC_D8 */\
> + ? ? ? MUX_VAL(CP(GPMC_D9), ? ? ? ?(IEN ?| PTD | DIS | M0)) /* GPMC_D9 */\
> + ? ? ? MUX_VAL(CP(GPMC_D10), ? ? ? (IEN ?| PTD | DIS | M0)) /* GPMC_D10 */\
> + ? ? ? MUX_VAL(CP(GPMC_D11), ? ? ? (IEN ?| PTD | DIS | M0)) /* GPMC_D11 */\
> + ? ? ? MUX_VAL(CP(GPMC_D12), ? ? ? (IEN ?| PTD | DIS | M0)) /* GPMC_D12 */\
> + ? ? ? MUX_VAL(CP(GPMC_D13), ? ? ? (IEN ?| PTD | DIS | M0)) /* GPMC_D13 */\
> + ? ? ? MUX_VAL(CP(GPMC_D14), ? ? ? (IEN ?| PTD | DIS | M0)) /* GPMC_D14 */\
> + ? ? ? MUX_VAL(CP(GPMC_D15), ? ? ? (IEN ?| PTD | DIS | M0)) /* GPMC_D15 */\
> + ? ? ? MUX_VAL(CP(GPMC_NCS0), ? ? ?(IDIS | PTU | EN ?| M0)) /* GPMC_nCS0 */\
> + ? ? ? MUX_VAL(CP(GPMC_NCS1), ? ? ?(IDIS | PTU | EN ?| M0)) /* GPMC_nCS1 */\
> + ? ? ? MUX_VAL(CP(GPMC_NCS2), ? ? ?(IDIS | PTU | EN ?| M0)) /* GPIO_nCS2 */\
> + ? ? ? MUX_VAL(CP(GPMC_NCS3), ? ? ?(IDIS | PTU | EN ?| M0)) /* GPIO_nCS3 */\
> + ? ? ? MUX_VAL(CP(GPMC_NCS4), ? ? ?(IDIS | PTU | EN ?| M0)) /* GPMC_nCS4 */\
> + ? ? ? MUX_VAL(CP(GPMC_NCS5), ? ? ?(IDIS | PTU | EN ?| M0)) /* GPMC_nCS5 */\
> + ? ? ? MUX_VAL(CP(GPMC_NCS6), ? ? ?(IDIS | PTU | EN ?| M0)) /* GPMC_nCS6 */\
> + ? ? ? MUX_VAL(CP(GPMC_NCS7), ? ? ?(IDIS | PTU | EN ?| M0)) /* GPMC_nCS7 */\
> + ? ? ? MUX_VAL(CP(GPMC_CLK), ? ? ? (IDIS | PTD | DIS | M0)) /* GPMC_CLK */\
> + ? ? ? MUX_VAL(CP(GPMC_NADV_ALE), ?(IDIS | PTD | DIS | M0)) /* GPMC_nADV_ALE */\
> + ? ? ? MUX_VAL(CP(GPMC_NOE), ? ? ? (IDIS | PTD | DIS | M0)) /* GPMC_nOE */\
> + ? ? ? MUX_VAL(CP(GPMC_NWE), ? ? ? (IDIS | PTD | DIS | M0)) /* GPMC_nWE */\
> + ? ? ? MUX_VAL(CP(GPMC_NBE0_CLE), ?(IDIS | PTD | DIS | M0)) /* GPMC_nBE0_CLE */\
> + ? ? ? MUX_VAL(CP(GPMC_NBE1), ? ? ?(IEN ?| PTD | DIS | M0)) /* GPMC_nBE1 */\
> + ? ? ? MUX_VAL(CP(GPMC_NWP), ? ? ? (IEN ?| PTD | DIS | M0)) /* GPMC_nWP */\
> + ? ? ? MUX_VAL(CP(GPMC_WAIT0), ? ? (IEN ?| PTU | EN ?| M0)) /* GPMC_WAIT0 */\
> + ? ? ? MUX_VAL(CP(GPMC_WAIT2), ? ? (IEN ?| PTU | DIS | M4)) /* GPIO_64-ETH_NRST */\
> + ? ? ? MUX_VAL(CP(MMC1_CLK), ? ? ? (IDIS | PTU | EN ?| M0)) /* MMC1_CLK */\
> + ? ? ? MUX_VAL(CP(MMC1_CMD), ? ? ? (IEN ?| PTU | EN ?| M0)) /* MMC1_CMD */\
> + ? ? ? MUX_VAL(CP(MMC1_DAT0), ? ? ?(IEN ?| PTU | EN ?| M0)) /* MMC1_DAT0 */\
> + ? ? ? MUX_VAL(CP(MMC1_DAT1), ? ? ?(IEN ?| PTU | EN ?| M0)) /* MMC1_DAT1 */\
> + ? ? ? MUX_VAL(CP(MMC1_DAT2), ? ? ?(IEN ?| PTU | EN ?| M0)) /* MMC1_DAT2 */\
> + ? ? ? MUX_VAL(CP(MMC1_DAT3), ? ? ?(IEN ?| PTU | EN ?| M0)) /* MMC1_DAT3 */\
> + ? ? ? MUX_VAL(CP(UART3_TX_IRTX), ?(IDIS | PTD | DIS | M0)) /* UART3_TX */\
> + ? ? ? MUX_VAL(CP(UART3_RX_IRRX), ?(IEN ?| PTD | DIS | M0)) /* UART3_RX */\
> + ? ? ? MUX_VAL(CP(I2C1_SCL), ? ? ? (IEN ?| PTU | EN ?| M0)) /* I2C1_SCL */\
> + ? ? ? MUX_VAL(CP(I2C1_SDA), ? ? ? (IEN ?| PTU | EN ?| M0)) /* I2C1_SDA */\
> + ? ? ? MUX_VAL(CP(I2C4_SCL), ? ? ? (IEN ?| PTU | EN ?| M0)) /* I2C4_SCL */\
> + ? ? ? MUX_VAL(CP(I2C4_SDA), ? ? ? (IEN ?| PTU | EN ?| M0)) /* I2C4_SDA */\
> + ? ? ? MUX_VAL(CP(SYS_32K), ? ? ? ?(IEN ?| PTD | DIS | M0)) /* SYS_32K */\
> + ? ? ? MUX_VAL(CP(SYS_BOOT0), ? ? ?(IEN ?| PTD | DIS | M4)) /* GPIO_2 */\
> + ? ? ? MUX_VAL(CP(SYS_BOOT1), ? ? ?(IEN ?| PTD | DIS | M4)) /* GPIO_3 */\
> + ? ? ? MUX_VAL(CP(SYS_BOOT2), ? ? ?(IEN ?| PTD | DIS | M4)) /* GPIO_4 */\
> + ? ? ? MUX_VAL(CP(SYS_BOOT3), ? ? ?(IEN ?| PTD | DIS | M4)) /* GPIO_5 */\
> + ? ? ? MUX_VAL(CP(SYS_BOOT4), ? ? ?(IEN ?| PTD | DIS | M4)) /* GPIO_6 */\
> + ? ? ? MUX_VAL(CP(SYS_BOOT5), ? ? ?(IEN ?| PTD | DIS | M4)) /* GPIO_7 */\
> + ? ? ? MUX_VAL(CP(SYS_BOOT6), ? ? ?(IEN ?| PTD | DIS | M4)) /* GPIO_8 */\
> + ? ? ? MUX_VAL(CP(SDRC_CKE0), ? ? ?(IDIS | PTU | EN ?| M0)) /* SDRC_CKE0 */\
> + ? ? ? MUX_VAL(CP(SDRC_CKE1), ? ? ?(IDIS | PTU | EN ?| M0)) /* SDRC_CKE1 */
> +#endif
> diff --git a/boards.cfg b/boards.cfg
> index 202de1a..6f8db44 100644
> --- a/boards.cfg
> +++ b/boards.cfg
> @@ -262,6 +262,7 @@ omap4_panda arm ? ? armv7 ? ? ? ? ? panda ? ? ? ? ? ti ? ? ? ? ? ? ?omap4
> ?omap4_sdp4430 ?arm ? ? armv7 ? ? ? ? ? sdp4430 ? ? ? ? ti ? ? ? ? ? ? ?omap4
> ?am3517_evm ? ? arm ? ? armv7 ? ? ? ? ? am3517evm ? ? ? logicpd ? ? ? ? omap3
> ?devkit8000 ? ? arm ? ? armv7 ? ? ? ? ? devkit8000 ? ? ?timll ? ? ? ? ? omap3
> +igep0020 ? ? ? arm ? ? armv7 ? ? ? ? ? igep0020 ? ? ? ?isee ? ? ? ? ? ?omap3
> ?s5p_goni ? ? ? arm ? ? armv7 ? ? ? ? ? goni ? ? ? ? ? ?samsung ? ? ? ? s5pc1xx
> ?smdkc100 ? ? ? arm ? ? armv7 ? ? ? ? ? smdkc100 ? ? ? ?samsung ? ? ? ? s5pc1xx
> ?ixdpg425 ? ? ? arm ? ? ixp
> diff --git a/include/configs/igep0020.h b/include/configs/igep0020.h
> new file mode 100644
> index 0000000..34e8a57
> --- /dev/null
> +++ b/include/configs/igep0020.h
> @@ -0,0 +1,228 @@
> +/*
> + * (C) Copyright 2010
> + * ISEE 2007 SL, <www.iseebcn.com>
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. ? ? ? ? See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#ifndef __CONFIG_H
> +#define __CONFIG_H
> +#include <asm/sizes.h>
> +
> +/*
> + * High Level Configuration Options
> + */
> +#define CONFIG_ARMV7 ? ? ? ? ? 1 ? ? ? /* This is an ARM V7 CPU core */
> +#define CONFIG_OMAP ? ? ? ? ? ?1 ? ? ? /* in a TI OMAP core */
> +#define CONFIG_OMAP34XX ? ? ? ? ? ? ? ?1 ? ? ? /* which is a 34XX */
> +#define CONFIG_OMAP3430 ? ? ? ? ? ? ? ?1 ? ? ? /* which is in a 3430 */
> +#define CONFIG_OMAP3_IGEP0020 ?1 ? ? ? /* working with IGEP0020 */
> +
> +#define CONFIG_SDRC ? ?/* The chip has SDRC controller */
> +
> +#include <asm/arch/cpu.h>
> +#include <asm/arch/omap3.h>
> +
> +/*
> + * Display CPU and Board information
> + */
> +#define CONFIG_DISPLAY_CPUINFO ? ? ? ? 1
> +#define CONFIG_DISPLAY_BOARDINFO ? ? ? 1
> +
> +/* Clock Defines */
> +#define V_OSCK ? ? ? ? ? ? ? ? 26000000 ? ? ? ?/* Clock output from T2 */
> +#define V_SCLK ? ? ? ? ? ? ? ? (V_OSCK >> 1)
> +
> +#define CONFIG_MISC_INIT_R
> +
> +#define CONFIG_CMDLINE_TAG ? ? ? ? ? ? 1 ? ? ? /* enable passing of ATAGs */
> +#define CONFIG_SETUP_MEMORY_TAGS ? ? ? 1
> +#define CONFIG_INITRD_TAG ? ? ? ? ? ? ?1
> +#define CONFIG_REVISION_TAG ? ? ? ? ? ?1
> +
> +/*
> + * NS16550 Configuration
> + */
> +
> +#define V_NS16550_CLK ? ? ? ? ? ? ? ? ?48000000 ? ? ? ?/* 48MHz (APLL96/2) */
> +
> +#define CONFIG_SYS_NS16550
> +#define CONFIG_SYS_NS16550_SERIAL
> +#define CONFIG_SYS_NS16550_REG_SIZE ? ?(-4)
> +#define CONFIG_SYS_NS16550_CLK ? ? ? ? V_NS16550_CLK
> +
> +/* select serial console configuration */
> +#define CONFIG_CONS_INDEX ? ? ? ? ? ? ?3
> +#define CONFIG_SYS_NS16550_COM3 ? ? ? ? ? ? ? ?OMAP34XX_UART3
> +#define CONFIG_SERIAL3 ? ? ? ? ? ? ? ? 3
> +
> +/* allow to overwrite serial and ethaddr */
> +#define CONFIG_ENV_OVERWRITE
> +#define CONFIG_BAUDRATE ? ? ? ? ? ? ? ? ? ? ? ?115200
> +#define CONFIG_SYS_BAUDRATE_TABLE ? ? ?{4800, 9600, 19200, 38400, 57600, 115200}
> +#define CONFIG_MMC ? ? ? ? ? ? ? ? ? ? 1
> +#define CONFIG_OMAP3_MMC ? ? ? ? ? ? ? 1
> +#define CONFIG_DOS_PARTITION ? ? ? ? ? 1
> +
> +/* DDR ?*/
> +#define CONFIG_OMAP3_NUMONYX_DDR ? ? ? 1
> +
> +/* USB */
> +#define CONFIG_MUSB_UDC ? ? ? ? ? ? ? ? ? ? ? ?1
> +#define CONFIG_USB_OMAP3 ? ? ? ? ? ? ? 1
> +#define CONFIG_TWL4030_USB ? ? ? ? ? ? 1
> +
> +/* USB device configuration */
> +#define CONFIG_USB_DEVICE ? ? ? ? ? ? ?1
> +#define CONFIG_USB_TTY ? ? ? ? ? ? ? ? 1
> +#define CONFIG_SYS_CONSOLE_IS_IN_ENV ? 1
> +
> +/* Change these to suit your needs */
> +#define CONFIG_USBD_VENDORID ? ? ? ? ? 0x0451
> +#define CONFIG_USBD_PRODUCTID ? ? ? ? ?0x5678
> +#define CONFIG_USBD_MANUFACTURER ? ? ? "Texas Instruments"
> +#define CONFIG_USBD_PRODUCT_NAME ? ? ? "IGEP"
> +
> +/* commands to include */
> +#include <config_cmd_default.h>
> +
> +#define CONFIG_CMD_CACHE
> +#define CONFIG_CMD_EXT2 ? ? ? ? ? ? ? ?/* EXT2 Support ? ? ? ? ? ? ? ? */
> +#define CONFIG_CMD_FAT ? ? ? ? /* FAT support ? ? ? ? ? ? ? ? ?*/
> +#define CONFIG_CMD_I2C ? ? ? ? /* I2C serial bus support ? ? ? */
> +#define CONFIG_CMD_MMC ? ? ? ? /* MMC support ? ? ? ? ? ? ? ? ?*/
> +#define CONFIG_CMD_ONENAND ? ? /* ONENAND support ? ? ? ? ? ? ?*/
> +#define CONFIG_CMD_NET ? ? ? ? /* bootp, tftpboot, rarpboot ? ?*/
> +#define CONFIG_CMD_DHCP
> +#define CONFIG_CMD_PING
> +#define CONFIG_CMD_NFS ? ? ? ? /* NFS support ? ? ? ? ? ? ? ? ?*/
> +#define CONFIG_CMD_MTDPARTS ? ?/* Enable MTD parts commands ? ?*/
> +#define CONFIG_MTD_DEVICE
> +
> +#undef CONFIG_CMD_FLASH ? ? ? ? ? ? ? ?/* flinfo, erase, protect ? ? ? */
> +#undef CONFIG_CMD_IMLS ? ? ? ? /* List all found images ? ? ? ?*/
> +
> +#define CONFIG_SYS_NO_FLASH
> +#define CONFIG_HARD_I2C ? ? ? ? ? ? ? ? ? ? ? ?1
> +#define CONFIG_SYS_I2C_SPEED ? ? ? ? ? 100000
> +#define CONFIG_SYS_I2C_SLAVE ? ? ? ? ? 1
> +#define CONFIG_SYS_I2C_BUS ? ? ? ? ? ? 0
> +#define CONFIG_SYS_I2C_BUS_SELECT ? ? ?1
> +#define CONFIG_DRIVER_OMAP34XX_I2C ? ? 1
> +
> +/*
> + * TWL4030
> + */
> +#define CONFIG_TWL4030_POWER ? ? ? ? ? 1
> +
> +/* Environment information */
> +#define CONFIG_BOOTCOMMAND \
> + ? ? ? "mmc init 0 ; fatload mmc 0 0x80000000 setup.ini ; source \0"
> +
> +#define CONFIG_BOOTDELAY ? ? ? ? ? ? ? 3
> +
> +#define CONFIG_EXTRA_ENV_SETTINGS \
> + ? ? ? "usbtty=cdc_acm\0"
> +
> +#define CONFIG_AUTO_COMPLETE ? ? ? ? ? 1
> +
> +/*
> + * Miscellaneous configurable options
> + */
> +#define CONFIG_SYS_LONGHELP ? ? ? ? ? ?/* undef to save memory */
> +#define CONFIG_SYS_HUSH_PARSER ? ? ? ? /* use "hush" command parser */
> +#define CONFIG_SYS_PROMPT_HUSH_PS2 ? ? "> "
> +#define CONFIG_SYS_PROMPT ? ? ? ? ? ? ?"U-Boot # "
> +#define CONFIG_SYS_CBSIZE ? ? ? ? ? ? ?256 ? ? /* Console I/O Buffer Size */
> +/* Print Buffer Size */
> +#define CONFIG_SYS_PBSIZE ? ? ? ? ? ? ?(CONFIG_SYS_CBSIZE + \
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? sizeof(CONFIG_SYS_PROMPT) + 16)
> +#define CONFIG_SYS_MAXARGS ? ? ? ? ? ? 16 ? ? ?/* max number of command args */
> +/* Boot Argument Buffer Size */
> +#define CONFIG_SYS_BARGSIZE ? ? ? ? ? ?(CONFIG_SYS_CBSIZE)
> +
> +#define CONFIG_SYS_MEMTEST_START ? ? ? (OMAP34XX_SDRC_CS0) ? ? /* memtest */
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? /* works on */
> +#define CONFIG_SYS_MEMTEST_END ? ? ? ? (OMAP34XX_SDRC_CS0 + \
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0x01F00000) /* 31MB */
> +
> +#define CONFIG_SYS_LOAD_ADDR ? ? ? ? ? (OMAP34XX_SDRC_CS0) ? ? /* default */
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? /* load address */
> +
> +#define CONFIG_SYS_MONITOR_LEN ? ? ? ? (256 << 10)
> +
> +/*
> + * OMAP3 has 12 GP timers, they can be driven by the system clock
> + * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
> + * This rate is divided by a local divisor.
> + */
> +#define CONFIG_SYS_TIMERBASE ? ? ? ? ? (OMAP34XX_GPT2)
> +#define CONFIG_SYS_PTV ? ? ? ? ? ? ? ? 2 ? ? ? /* Divisor: 2^(PTV+1) => 8 */
> +#define CONFIG_SYS_HZ ? ? ? ? ? ? ? ? ?1000
> +
> +/*
> + * Stack sizes
> + *
> + * The stack sizes are set up in start.S using the settings below
> + */
> +#define CONFIG_STACKSIZE ? ? ? (128 << 10) ? ? /* regular stack 128 KiB */
> +
> +/*
> + * Physical Memory Map
> + *
> + */
> +#define CONFIG_NR_DRAM_BANKS ? 2 ? ? ? /* CS1 may or may not be populated */
> +#define PHYS_SDRAM_1 ? ? ? ? ? OMAP34XX_SDRC_CS0
> +#define PHYS_SDRAM_1_SIZE ? ? ?(32 << 20) ? ? ?/*@least 32 meg */
> +#define PHYS_SDRAM_2 ? ? ? ? ? OMAP34XX_SDRC_CS1
> +
> +/* SDRAM Bank Allocation method */
> +#define SDRC_R_B_C ? ? ? ? ? ? 1
> +
> +/*
> + * FLASH and environment organization
> + */
> +
> +#define PISMO1_ONEN_SIZE ? ? ? ? ? ? ? GPMC_SIZE_128M /* Configure the PISMO */
> +
> +#define CONFIG_SYS_ONENAND_BASE ? ? ? ? ? ? ? ?ONENAND_MAP
> +
> +#define ONENAND_ENV_OFFSET ? ? ? ? ? ? 0x260000 /* environment starts here */
> +
> +#define CONFIG_ENV_IS_IN_ONENAND ? ? ? 1
> +#define CONFIG_ENV_SIZE ? ? ? ? ? ? ? ? ? ? ? ?(512 << 10) /* Total Size Environment */
> +#define CONFIG_ENV_ADDR ? ? ? ? ? ? ? ? ? ? ? ?ONENAND_ENV_OFFSET
> +
> +/*
> + * Size of malloc() pool
> + */
> +#define CONFIG_SYS_MALLOC_LEN ? ? ? ? ?(CONFIG_ENV_SIZE + (128 << 10))
> +#define CONFIG_SYS_GBL_DATA_SIZE ? ? ? 128 /* bytes for initial data */
> +
> +/*
> + * SMSC911x Ethernet
> + */
> +#if defined(CONFIG_CMD_NET)
> +#define CONFIG_NET_MULTI
> +#define CONFIG_SMC911X
> +#define CONFIG_SMC911X_32_BIT
> +#define CONFIG_SMC911X_BASE ? ?0x2C000000
> +#endif /* (CONFIG_CMD_NET) */
> +
> +#define CONFIG_SYS_SDRAM_BASE ? ? ? ? ?PHYS_SDRAM_1
> +#define CONFIG_SYS_INIT_SP_ADDR ? ? ? ? ? ? ? ?(LOW_LEVEL_SRAM_STACK - CONFIG_SYS_GBL_DATA_SIZE)
> +
> +#endif /* __CONFIG_H */
> --
> 1.7.1
>
>
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2010-10-11 19:49 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2010-10-09 23:13 [U-Boot] [PATCH 0/3] Add support for the IGEP v2 board Enric Balletbo i Serra
2010-10-09 23:13 ` [U-Boot] [PATCH 1/3] mtd: OneNAND: add support for OneNAND manufactured by Numonyx Enric Balletbo i Serra
2010-10-10 4:41 ` Steve Sakoman
2010-10-09 23:13 ` [U-Boot] [PATCH 2/3] OMAP3: SDRC: Introduce Numonyx DDR type Enric Balletbo i Serra
2010-10-10 4:46 ` Steve Sakoman
2010-10-09 23:13 ` [U-Boot] [PATCH 3/3] OMAP3: Add support for the IGEP v2 board Enric Balletbo i Serra
2010-10-10 4:51 ` Steve Sakoman
-- strict thread matches above, loose matches on Subject: below --
2010-10-11 19:48 [U-Boot] [PATCHv4 0/3] " Enric Balletbo i Serra
2010-10-11 19:48 ` [U-Boot] [PATCH 3/3] OMAP3: " Enric Balletbo i Serra
2010-10-11 19:49 ` Enric Balletbò i Serra
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