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From: Steve Sakoman <steve@sakoman.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH] armv7, beagle: Second SDRAM bank don;t work
Date: Thu, 14 Oct 2010 06:54:47 -0700	[thread overview]
Message-ID: <1287064487.7756.21.camel@quadra> (raw)
In-Reply-To: <20101014083852.EBE03134F26@gemini.denx.de>

On Thu, 2010-10-14 at 10:38 +0200, Wolfgang Denk wrote:
> Dear Heiko Schocher,
> 
> In message <1287043393-2036-1-git-send-email-hs@denx.de> you wrote:
> > since commit 3667cbeed5e3c4067e624e52a916b1ebb02c8f05
> > on beagle board the second sdram bank didn;t longer
> > work. Since this patch sdram settings just get copied
> > from bank a, but CMD_NOP, CMD_PRECHARGE, CMD_AUTOREFRESH
> > are not executed and after that mr register is also
> > not updated. This patch adds this for the bank b.
> 
> I would like to see Steve's ACK for the original Beagle board, and
> it's several versions.
> 
> Steve, what Heiko forgets to mention here is that this problem happened
> on a EBV-Beagle, so there are certrain hardware differences.

I suspect that his using an EVB-Beagle (with associated EVB x-load) is
what is causing the issue for him.

With the introduction of the Beagle xM came the need to deal with
several types of POP memory, and the resulting need for customized setup
for the SDRC.

This is best handled in x-load while running from SRAM, since timings
and mux setup are different for each memory type.

The code in Beagle x-load currently looks like this:

void config_3430sdram_ddr(void)
{
	/* reset sdrc controller */
	__raw_writel(SOFTRESET, SDRC_SYSCONFIG);
	wait_on_value(BIT0, BIT0, SDRC_STATUS, 12000000);
	__raw_writel(0, SDRC_SYSCONFIG);

	/* setup sdrc to ball mux */
	__raw_writel(SDP_SDRC_SHARING, SDRC_SHARING);

	if (beagle_revision() == REVISION_XM) {
		if (identify_xm_ddr() == MICRON_DDR) {
			__raw_writel(0x2, SDRC_CS_CFG); /* 256MB/bank */
			__raw_writel(SDP_SDRC_MDCFG_0_DDR_MICRON_XM, SDRC_MCFG_0);
			__raw_writel(SDP_SDRC_MDCFG_0_DDR_MICRON_XM, SDRC_MCFG_1);
			__raw_writel(MICRON_V_ACTIMA_200, SDRC_ACTIM_CTRLA_0);
			__raw_writel(MICRON_V_ACTIMB_200, SDRC_ACTIM_CTRLB_0);
			__raw_writel(MICRON_V_ACTIMA_200, SDRC_ACTIM_CTRLA_1);
			__raw_writel(MICRON_V_ACTIMB_200, SDRC_ACTIM_CTRLB_1);
			__raw_writel(SDP_3430_SDRC_RFR_CTRL_200MHz, SDRC_RFR_CTRL_0);
			__raw_writel(SDP_3430_SDRC_RFR_CTRL_200MHz, SDRC_RFR_CTRL_1);
		} else {
			__raw_writel(0x4, SDRC_CS_CFG); /* 512MB/bank */
			__raw_writel(SDP_SDRC_MDCFG_0_DDR_NUMONYX_XM, SDRC_MCFG_0);
			__raw_writel(SDP_SDRC_MDCFG_0_DDR_NUMONYX_XM, SDRC_MCFG_1);
			__raw_writel(NUMONYX_V_ACTIMA_165, SDRC_ACTIM_CTRLA_0);
			__raw_writel(NUMONYX_V_ACTIMB_165, SDRC_ACTIM_CTRLB_0);
			__raw_writel(NUMONYX_V_ACTIMA_165, SDRC_ACTIM_CTRLA_1);
			__raw_writel(NUMONYX_V_ACTIMB_165, SDRC_ACTIM_CTRLB_1);
			__raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_0);
			__raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_1);
		}
	} else {
		__raw_writel(0x1, SDRC_CS_CFG); /* 128MB/bank */
		__raw_writel(SDP_SDRC_MDCFG_0_DDR, SDRC_MCFG_0);
		__raw_writel(SDP_SDRC_MDCFG_0_DDR, SDRC_MCFG_1);
		__raw_writel(MICRON_V_ACTIMA_165, SDRC_ACTIM_CTRLA_0);
		__raw_writel(MICRON_V_ACTIMB_165, SDRC_ACTIM_CTRLB_0);
		__raw_writel(MICRON_V_ACTIMA_165, SDRC_ACTIM_CTRLA_1);
		__raw_writel(MICRON_V_ACTIMB_165, SDRC_ACTIM_CTRLB_1);
		__raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_0);
		__raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_1);
	}

	__raw_writel(SDP_SDRC_POWER_POP, SDRC_POWER);

	/* init sequence for mDDR/mSDR using manual commands (DDR is different) */
	__raw_writel(CMD_NOP, SDRC_MANUAL_0);
	__raw_writel(CMD_NOP, SDRC_MANUAL_1);

	delay(5000);

	__raw_writel(CMD_PRECHARGE, SDRC_MANUAL_0);
	__raw_writel(CMD_PRECHARGE, SDRC_MANUAL_1);

	__raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0);
	__raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_1);

	__raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0);
	__raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_1);

	/* set mr0 */
	__raw_writel(SDP_SDRC_MR_0_DDR, SDRC_MR_0);
	__raw_writel(SDP_SDRC_MR_0_DDR, SDRC_MR_1);

	/* set up dll */
	__raw_writel(SDP_SDRC_DLLAB_CTRL, SDRC_DLLA_CTRL);
	delay(0x2000);	/* give time to lock */

}

The code in u-boot to copy bank 1 settings to bank 2 was a workaround so that Beagle users
who didn't update x-load immediately would at least have a functioning system.

I don't think that Heiko's patch will do any harm and it might be a good idea so that EVB
Beagle users can use the standard Beagle u-boot.  I will have to verify that it does no
harm on all the various Beagle versions first though.

I will Ack or Nack after I do some testing.

Regards,

Steve

  reply	other threads:[~2010-10-14 13:54 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2010-10-14  8:03 [U-Boot] [PATCH] armv7, beagle: Second SDRAM bank don;t work Heiko Schocher
2010-10-14  8:38 ` Wolfgang Denk
2010-10-14 13:54   ` Steve Sakoman [this message]
2010-10-14 14:06     ` Heiko Schocher
2010-10-14 16:34     ` Wolfgang Denk
2010-10-14 21:15     ` Paulraj, Sandeep
2010-10-14 22:40 ` Steve Sakoman

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