[U-Boot] [PATCH 08/15] powerpc/8xxx: Rework XES boards pci_init_board to use common FSL PCIe code

[Peter Tyser <ptyser@xes-inc.com>]

On Tue, 2010-12-21 at 11:49 -0600, Kumar Gala wrote:
> On Dec 20, 2010, at 10:49 AM, Peter Tyser wrote:
> 
> > Thanks for the cleanup.  What branch should this series be applied to?
> > And are there prerequisites?  I'm having issues applying them to test
> > and review.

Any direction on how these should be applied for testing?

<snip>

> >> --- a/board/xes/common/fsl_8xxx_pci.c
> >> +++ b/board/xes/common/fsl_8xxx_pci.c
> >> @@ -34,15 +34,6 @@
> >> #ifdef CONFIG_PCI1
> >> static struct pci_controller pci1_hose;
> >> #endif
> > 
> > Is there a reason PCI1 wasn't changed over too?  I see pci1_hose is
> > still referenced below, but other boards with a PCI1 don't use similar
> > code.
> 
> I was trying to limit how much clean up I did so left this to just PCIe interfaces.  Normal PCI and PCI-X is something I might get around to but one thing at a time

Ah, OK.  If we're removing the LAW entries for PCI1 in law.c below, how
is a LAW being set for PCI1?  It looks like PCIe laws are set in
fsl_configure_pcie(), and PCI LAWs are set via set_next_law() in
board-specific code?  I'm not seeing the call to set_next_law() in X-ES
board specific code after this change though.

Best,
Peter

> > <snip>
> > 
> >> diff --git a/board/xes/xpedite520x/law.c b/board/xes/xpedite520x/law.c
> >> index bbfcb9d..3afb3ae 100644
> >> --- a/board/xes/xpedite520x/law.c
> >> +++ b/board/xes/xpedite520x/law.c
> >> @@ -38,10 +38,6 @@ struct law_entry law_table[] = {
> >> 	/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
> >> 	SET_LAW(CONFIG_SYS_FLASH_BASE2, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
> >> 	SET_LAW(CONFIG_SYS_NAND_BASE, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
> >> -#if CONFIG_SYS_PCI1_MEM_PHYS
> >> -	SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_1G, LAW_TRGT_IF_PCI_1),
> >> -	SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCI_1),
> >> -#endif
> >> #if CONFIG_SYS_PCI2_MEM_PHYS
> >> 	SET_LAW(CONFIG_SYS_PCI2_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCI_2),
> >> 	SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCI_2),