From: "Eric Bénard" <eric@eukrea.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 2/5] include/asm/arch-at91: update several .h files to ATMEL_xxx name scheme
Date: Tue, 7 Jun 2011 08:35:05 +0200 [thread overview]
Message-ID: <1307428508-26058-2-git-send-email-eric@eukrea.com> (raw)
In-Reply-To: <1307428508-26058-1-git-send-email-eric@eukrea.com>
Signed-off-by: Eric B?nard <eric@eukrea.com>
---
arch/arm/include/asm/arch-at91/at91_matrix.h | 10 +++---
arch/arm/include/asm/arch-at91/at91_rstc.h | 2 +-
arch/arm/include/asm/arch-at91/at91_wdt.h | 2 +-
arch/arm/include/asm/arch-at91/at91sam9_sdramc.h | 30 +++++++++++-----------
arch/arm/include/asm/arch-at91/at91sam9_smc.h | 12 ++++----
5 files changed, 28 insertions(+), 28 deletions(-)
diff --git a/arch/arm/include/asm/arch-at91/at91_matrix.h b/arch/arm/include/asm/arch-at91/at91_matrix.h
index f99b1d4..a9ba9e9 100644
--- a/arch/arm/include/asm/arch-at91/at91_matrix.h
+++ b/arch/arm/include/asm/arch-at91/at91_matrix.h
@@ -26,18 +26,18 @@
#ifdef __ASSEMBLY__
#if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9G20)
-#define AT91_ASM_MATRIX_CSA0 (AT91_MATRIX_BASE + 0x11C)
+#define AT91_ASM_MATRIX_CSA0 (ATMEL_BASE_MATRIX + 0x11C)
#elif defined(CONFIG_AT91SAM9261)
-#define AT91_ASM_MATRIX_CSA0 (AT91_MATRIX_BASE + 0x30)
+#define AT91_ASM_MATRIX_CSA0 (ATMEL_BASE_MATRIX + 0x30)
#elif defined(CONFIG_AT91SAM9263)
-#define AT91_ASM_MATRIX_CSA0 (AT91_MATRIX_BASE + 0x120)
+#define AT91_ASM_MATRIX_CSA0 (ATMEL_BASE_MATRIX + 0x120)
#elif defined(CONFIG_AT91SAM9G45)
-#define AT91_ASM_MATRIX_CSA0 (AT91_MATRIX_BASE + 0x128)
+#define AT91_ASM_MATRIX_CSA0 (ATMEL_BASE_MATRIX + 0x128)
#else
#error AT91_ASM_MATRIX_CSA0 is not definied for current CPU
#endif
-#define AT91_ASM_MATRIX_MCFG AT91_MATRIX_BASE
+#define AT91_ASM_MATRIX_MCFG ATMEL_BASE_MATRIX
#else
#if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9G20)
diff --git a/arch/arm/include/asm/arch-at91/at91_rstc.h b/arch/arm/include/asm/arch-at91/at91_rstc.h
index 510eed5..15ffd18 100644
--- a/arch/arm/include/asm/arch-at91/at91_rstc.h
+++ b/arch/arm/include/asm/arch-at91/at91_rstc.h
@@ -16,7 +16,7 @@
#ifndef AT91_RSTC_H
#define AT91_RSTC_H
-#define AT91_ASM_RSTC_MR (AT91_RSTC_BASE + 0x08)
+#define AT91_ASM_RSTC_MR (ATMEL_BASE_RSTC + 0x08)
#ifndef __ASSEMBLY__
diff --git a/arch/arm/include/asm/arch-at91/at91_wdt.h b/arch/arm/include/asm/arch-at91/at91_wdt.h
index cf08daf..dc22ea1 100644
--- a/arch/arm/include/asm/arch-at91/at91_wdt.h
+++ b/arch/arm/include/asm/arch-at91/at91_wdt.h
@@ -19,7 +19,7 @@
#ifdef __ASSEMBLY__
-#define AT91_ASM_WDT_MR (AT91_WDT_BASE + 0x04)
+#define AT91_ASM_WDT_MR (ATMEL_BASE_WDT + 0x04)
#else
diff --git a/arch/arm/include/asm/arch-at91/at91sam9_sdramc.h b/arch/arm/include/asm/arch-at91/at91sam9_sdramc.h
index c3da3a6..54159a7 100644
--- a/arch/arm/include/asm/arch-at91/at91sam9_sdramc.h
+++ b/arch/arm/include/asm/arch-at91/at91sam9_sdramc.h
@@ -19,19 +19,19 @@
#ifdef __ASSEMBLY__
-#ifndef AT91_SDRAMC_BASE
-#define AT91_SDRAMC_BASE AT91_SDRAMC0_BASE
+#ifndef ATMEL_BASE_SDRAMC
+#define ATMEL_BASE_SDRAMC AT91_SDRAMC0_BASE
#endif
-#define AT91_ASM_SDRAMC_MR AT91_SDRAMC_BASE
-#define AT91_ASM_SDRAMC_TR (AT91_SDRAMC_BASE + 0x04)
-#define AT91_ASM_SDRAMC_CR (AT91_SDRAMC_BASE + 0x08)
-#define AT91_ASM_SDRAMC_MDR (AT91_SDRAMC_BASE + 0x24)
+#define AT91_ASM_SDRAMC_MR ATMEL_BASE_SDRAMC
+#define AT91_ASM_SDRAMC_TR (ATMEL_BASE_SDRAMC + 0x04)
+#define AT91_ASM_SDRAMC_CR (ATMEL_BASE_SDRAMC + 0x08)
+#define AT91_ASM_SDRAMC_MDR (ATMEL_BASE_SDRAMC + 0x24)
#endif
/* SDRAM Controller (SDRAMC) registers */
-#define AT91_SDRAMC_MR (AT91_SDRAMC + 0x00) /* SDRAM Controller Mode Register */
+#define AT91_SDRAMC_MR (ATMEL_BASE_SDRAMC + 0x00) /* SDRAM Controller Mode Register */
#define AT91_SDRAMC_MODE (0xf << 0) /* Command Mode */
#define AT91_SDRAMC_MODE_NORMAL 0
#define AT91_SDRAMC_MODE_NOP 1
@@ -41,10 +41,10 @@
#define AT91_SDRAMC_MODE_EXT_LMR 5
#define AT91_SDRAMC_MODE_DEEP 6
-#define AT91_SDRAMC_TR (AT91_SDRAMC + 0x04) /* SDRAM Controller Refresh Timer Register */
+#define AT91_SDRAMC_TR (ATMEL_BASE_SDRAMC + 0x04) /* SDRAM Controller Refresh Timer Register */
#define AT91_SDRAMC_COUNT (0xfff << 0) /* Refresh Timer Counter */
-#define AT91_SDRAMC_CR (AT91_SDRAMC + 0x08) /* SDRAM Controller Configuration Register */
+#define AT91_SDRAMC_CR (ATMEL_BASE_SDRAMC + 0x08) /* SDRAM Controller Configuration Register */
#define AT91_SDRAMC_NC (3 << 0) /* Number of Column Bits */
#define AT91_SDRAMC_NC_8 (0 << 0)
#define AT91_SDRAMC_NC_9 (1 << 0)
@@ -71,7 +71,7 @@
#define AT91_SDRAMC_TRAS (0xf << 24) /* Active to Precharge Delay */
#define AT91_SDRAMC_TXSR (0xf << 28) /* Exit Self Refresh to Active Delay */
-#define AT91_SDRAMC_LPR (AT91_SDRAMC + 0x10) /* SDRAM Controller Low Power Register */
+#define AT91_SDRAMC_LPR (ATMEL_BASE_SDRAMC + 0x10) /* SDRAM Controller Low Power Register */
#define AT91_SDRAMC_LPCB (3 << 0) /* Low-power Configurations */
#define AT91_SDRAMC_LPCB_DISABLE 0
#define AT91_SDRAMC_LPCB_SELF_REFRESH 1
@@ -85,13 +85,13 @@
#define AT91_SDRAMC_TIMEOUT_64_CLK_CYCLES (1 << 12)
#define AT91_SDRAMC_TIMEOUT_128_CLK_CYCLES (2 << 12)
-#define AT91_SDRAMC_IER (AT91_SDRAMC + 0x14) /* SDRAM Controller Interrupt Enable Register */
-#define AT91_SDRAMC_IDR (AT91_SDRAMC + 0x18) /* SDRAM Controller Interrupt Disable Register */
-#define AT91_SDRAMC_IMR (AT91_SDRAMC + 0x1C) /* SDRAM Controller Interrupt Mask Register */
-#define AT91_SDRAMC_ISR (AT91_SDRAMC + 0x20) /* SDRAM Controller Interrupt Status Register */
+#define AT91_SDRAMC_IER (ATMEL_BASE_SDRAMC + 0x14) /* SDRAM Controller Interrupt Enable Register */
+#define AT91_SDRAMC_IDR (ATMEL_BASE_SDRAMC + 0x18) /* SDRAM Controller Interrupt Disable Register */
+#define AT91_SDRAMC_IMR (ATMEL_BASE_SDRAMC + 0x1C) /* SDRAM Controller Interrupt Mask Register */
+#define AT91_SDRAMC_ISR (ATMEL_BASE_SDRAMC + 0x20) /* SDRAM Controller Interrupt Status Register */
#define AT91_SDRAMC_RES (1 << 0) /* Refresh Error Status */
-#define AT91_SDRAMC_MDR (AT91_SDRAMC + 0x24) /* SDRAM Memory Device Register */
+#define AT91_SDRAMC_MDR (ATMEL_BASE_SDRAMC + 0x24) /* SDRAM Memory Device Register */
#define AT91_SDRAMC_MD (3 << 0) /* Memory Device Type */
#define AT91_SDRAMC_MD_SDRAM 0
#define AT91_SDRAMC_MD_LOW_POWER_SDRAM 1
diff --git a/arch/arm/include/asm/arch-at91/at91sam9_smc.h b/arch/arm/include/asm/arch-at91/at91sam9_smc.h
index d180c8a..2ea2791 100644
--- a/arch/arm/include/asm/arch-at91/at91sam9_smc.h
+++ b/arch/arm/include/asm/arch-at91/at91sam9_smc.h
@@ -18,14 +18,14 @@
#ifdef __ASSEMBLY__
-#ifndef AT91_SMC_BASE
-#define AT91_SMC_BASE AT91_SMC0_BASE
+#ifndef ATMEL_BASE_SMC
+#define ATMEL_BASE_SMC ATMEL_BASE_SMC0
#endif
-#define AT91_ASM_SMC_SETUP0 AT91_SMC_BASE
-#define AT91_ASM_SMC_PULSE0 (AT91_SMC_BASE + 0x04)
-#define AT91_ASM_SMC_CYCLE0 (AT91_SMC_BASE + 0x08)
-#define AT91_ASM_SMC_MODE0 (AT91_SMC_BASE + 0x0C)
+#define AT91_ASM_SMC_SETUP0 ATMEL_BASE_SMC
+#define AT91_ASM_SMC_PULSE0 (ATMEL_BASE_SMC + 0x04)
+#define AT91_ASM_SMC_CYCLE0 (ATMEL_BASE_SMC + 0x08)
+#define AT91_ASM_SMC_MODE0 (ATMEL_BASE_SMC + 0x0C)
#else
--
1.7.4.4
next prev parent reply other threads:[~2011-06-07 6:35 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-06-07 6:35 [U-Boot] [PATCH 1/5] at91sam9260_devices: fix following atmal rework Eric Bénard
2011-06-07 6:35 ` Eric Bénard [this message]
2011-06-07 6:35 ` [U-Boot] [PATCH 3/5] arm926ejs/at91/lowlevel_init.S: temporary fix Eric Bénard
2011-06-07 8:04 ` Reinhard Meyer
2011-06-07 8:32 ` Eric Bénard
2011-06-07 6:35 ` [U-Boot] [PATCH 4/5] cpu9260/9G20: fix board support Eric Bénard
2011-06-07 6:35 ` [U-Boot] [PATCH 5/5] cpuat91: " Eric Bénard
2011-06-07 7:56 ` [U-Boot] [PATCH 1/5] at91sam9260_devices: fix following atmal rework Reinhard Meyer
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1307428508-26058-2-git-send-email-eric@eukrea.com \
--to=eric@eukrea.com \
--cc=u-boot@lists.denx.de \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox