From: Aneesh V <aneesh@ti.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH v4 3/9] armv7: rename cache related CONFIG flags
Date: Fri, 17 Jun 2011 15:00:48 +0530 [thread overview]
Message-ID: <1308303054-8727-4-git-send-email-aneesh@ti.com> (raw)
In-Reply-To: <1299589658-30896-1-git-send-email-aneesh@ti.com>
Replace the cache related CONFIG flags with more meaningful
names. Following are the changes:
CONFIG_L2_OFF -> CONFIG_SYS_L2CACHE_OFF
CONFIG_SYS_NO_ICACHE -> CONFIG_SYS_ICACHE_OFF
CONFIG_SYS_NO_DCACHE -> CONFIG_SYS_DCACHE_OFF
Signed-off-by: Aneesh V <aneesh@ti.com>
V2:
* Changed CONFIG_L2_OFF -> CONFIG_SYS_NO_L2CACHE
V4:
* Changed all three flags to the final names suggested as above
and accordingly changed the commit message
---
arch/arm/cpu/arm1136/start.S | 4 ++--
arch/arm/cpu/armv7/cpu.c | 3 ---
arch/arm/include/asm/global_data.h | 2 +-
arch/arm/lib/Makefile | 2 --
arch/arm/lib/board.c | 2 +-
arch/arm/lib/cache-cp15.c | 6 +++---
board/armltd/integrator/split_by_variant.sh | 8 ++++----
common/cmd_bdinfo.c | 2 +-
include/configs/B2.h | 3 ++-
include/configs/assabet.h | 2 +-
include/configs/ca9x4_ct_vxp.h | 2 +-
include/configs/cerf250.h | 2 +-
include/configs/cradle.h | 2 +-
include/configs/csb226.h | 2 +-
include/configs/dnp1110.h | 2 +-
include/configs/efikamx.h | 2 +-
include/configs/evb4510.h | 3 ++-
include/configs/gcplus.h | 2 +-
include/configs/innokom.h | 2 +-
include/configs/jornada.h | 2 +-
include/configs/lart.h | 2 +-
include/configs/lubbock.h | 2 +-
include/configs/mx51evk.h | 2 +-
include/configs/mx53evk.h | 2 +-
include/configs/omap4_panda.h | 2 +-
include/configs/omap4_sdp4430.h | 2 +-
include/configs/pleb2.h | 2 +-
include/configs/pxa255_idp.h | 2 +-
include/configs/s5pc210_universal.h | 2 +-
include/configs/shannon.h | 2 +-
include/configs/tegra2-common.h | 2 +-
include/configs/trizepsiv.h | 2 +-
include/configs/vision2.h | 2 +-
include/configs/xaeniax.h | 2 +-
include/configs/xm250.h | 2 +-
include/configs/zylonite.h | 2 +-
36 files changed, 42 insertions(+), 45 deletions(-)
diff --git a/arch/arm/cpu/arm1136/start.S b/arch/arm/cpu/arm1136/start.S
index 3c5f3ef..200a800 100644
--- a/arch/arm/cpu/arm1136/start.S
+++ b/arch/arm/cpu/arm1136/start.S
@@ -512,10 +512,10 @@ fiq:
.align 5
.global arm1136_cache_flush
arm1136_cache_flush:
-#if !defined(CONFIG_SYS_NO_ICACHE)
+#if !defined(CONFIG_SYS_ICACHE_OFF)
mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache
#endif
-#if !defined(CONFIG_SYS_NO_DCACHE)
+#if !defined(CONFIG_SYS_DCACHE_OFF)
mcr p15, 0, r1, c7, c14, 0 @ invalidate D cache
#endif
mov pc, lr @ back to caller
diff --git a/arch/arm/cpu/armv7/cpu.c b/arch/arm/cpu/armv7/cpu.c
index a01e0d6..bc4238f 100644
--- a/arch/arm/cpu/armv7/cpu.c
+++ b/arch/arm/cpu/armv7/cpu.c
@@ -35,9 +35,6 @@
#include <command.h>
#include <asm/system.h>
#include <asm/cache.h>
-#ifndef CONFIG_L2_OFF
-#include <asm/arch/sys_proto.h>
-#endif
static void cache_flush(void);
diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h
index 2a84d27..7578d53 100644
--- a/arch/arm/include/asm/global_data.h
+++ b/arch/arm/include/asm/global_data.h
@@ -70,7 +70,7 @@ typedef struct global_data {
unsigned long irq_sp; /* irq stack pointer */
unsigned long start_addr_sp; /* start_addr_stackpointer */
unsigned long reloc_off;
-#if !(defined(CONFIG_SYS_NO_ICACHE) && defined(CONFIG_SYS_NO_DCACHE))
+#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
unsigned long tlb_addr;
#endif
void **jt; /* jump table */
diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile
index 03b1b5e..f993d74 100644
--- a/arch/arm/lib/Makefile
+++ b/arch/arm/lib/Makefile
@@ -39,9 +39,7 @@ GLCOBJS += div0.o
COBJS-y += board.o
COBJS-y += bootm.o
COBJS-y += cache.o
-ifndef CONFIG_SYS_NO_CP15_CACHE
COBJS-y += cache-cp15.o
-endif
COBJS-y += interrupts.o
COBJS-y += reset.o
SOBJS-$(CONFIG_USE_ARCH_MEMSET) += memset.o
diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c
index 1a784a1..6342e97 100644
--- a/arch/arm/lib/board.c
+++ b/arch/arm/lib/board.c
@@ -329,7 +329,7 @@ void board_init_f (ulong bootflag)
debug ("Reserving %ldk for protected RAM at %08lx\n", reg, addr);
#endif /* CONFIG_PRAM */
-#if !(defined(CONFIG_SYS_NO_ICACHE) && defined(CONFIG_SYS_NO_DCACHE))
+#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
/* reserve TLB table */
addr -= (4096 * 4);
diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c
index d9175f0..ba73fb9 100644
--- a/arch/arm/lib/cache-cp15.c
+++ b/arch/arm/lib/cache-cp15.c
@@ -24,7 +24,7 @@
#include <common.h>
#include <asm/system.h>
-#if !(defined(CONFIG_SYS_NO_ICACHE) && defined(CONFIG_SYS_NO_DCACHE))
+#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
#define CACHE_SETUP 0x1a
@@ -118,7 +118,7 @@ static void cache_disable(uint32_t cache_bit)
}
#endif
-#ifdef CONFIG_SYS_NO_ICACHE
+#ifdef CONFIG_SYS_ICACHE_OFF
void icache_enable (void)
{
return;
@@ -150,7 +150,7 @@ int icache_status(void)
}
#endif
-#ifdef CONFIG_SYS_NO_DCACHE
+#ifdef CONFIG_SYS_DCACHE_OFF
void dcache_enable (void)
{
return;
diff --git a/board/armltd/integrator/split_by_variant.sh b/board/armltd/integrator/split_by_variant.sh
index d869dd2..19fc832 100755
--- a/board/armltd/integrator/split_by_variant.sh
+++ b/board/armltd/integrator/split_by_variant.sh
@@ -103,16 +103,16 @@ case "$cpu" in
#undef CONFIG_CM_INIT /* CM may not have initialization reg */
#undef CONFIG_CM_TCRAM /* CM may not have TCRAM */
/* May not be processor without cache support */
-#define CONFIG_SYS_NO_ICACHE 1
-#define CONFIG_SYS_NO_DCACHE 1
+#define CONFIG_SYS_ICACHE_OFF 1
+#define CONFIG_SYS_DCACHE_OFF 1
_EOF
;;
arm720t)
cat >> ${config_file} << _EOF
/* May not be processor without cache support */
-#define CONFIG_SYS_NO_ICACHE 1
-#define CONFIG_SYS_NO_DCACHE 1
+#define CONFIG_SYS_ICACHE_OFF 1
+#define CONFIG_SYS_DCACHE_OFF 1
_EOF
;;
esac
diff --git a/common/cmd_bdinfo.c b/common/cmd_bdinfo.c
index 75924f8..6051120 100644
--- a/common/cmd_bdinfo.c
+++ b/common/cmd_bdinfo.c
@@ -345,7 +345,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
printf("ip_addr = %pI4\n", &bd->bi_ip_addr);
#endif
printf("baudrate = %d bps\n", bd->bi_baudrate);
-#if !(defined(CONFIG_SYS_NO_ICACHE) && defined(CONFIG_SYS_NO_DCACHE))
+#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
print_num("TLB addr", gd->tlb_addr);
#endif
print_num("relocaddr", gd->relocaddr);
diff --git a/include/configs/B2.h b/include/configs/B2.h
index 7846a92..e181fa8 100644
--- a/include/configs/B2.h
+++ b/include/configs/B2.h
@@ -38,7 +38,8 @@
#define CONFIG_B2 1 /* on an B2 Board */
#define CONFIG_ARM_THUMB 1 /* this is an ARM7TDMI */
#undef CONFIG_ARM7_REVD /* disable ARM720 REV.D Workarounds */
-#define CONFIG_SYS_NO_CP15_CACHE
+#define CONFIG_SYS_ICACHE_OFF
+#define CONFIG_SYS_DCACHE_OFF
#define CONFIG_ARCH_CPU_INIT
#define CONFIG_S3C44B0_CLOCK_SPEED 75 /* we have a 75Mhz S3C44B0*/
diff --git a/include/configs/assabet.h b/include/configs/assabet.h
index 5cd1836..dc9bd88 100644
--- a/include/configs/assabet.h
+++ b/include/configs/assabet.h
@@ -38,7 +38,7 @@
#undef CONFIG_USE_IRQ
/* we will never enable dcache, because we have to setup MMU first */
-#define CONFIG_SYS_NO_DCACHE
+#define CONFIG_SYS_DCACHE_OFF
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS 1
diff --git a/include/configs/ca9x4_ct_vxp.h b/include/configs/ca9x4_ct_vxp.h
index 7f83249..f0ac79a 100644
--- a/include/configs/ca9x4_ct_vxp.h
+++ b/include/configs/ca9x4_ct_vxp.h
@@ -41,7 +41,7 @@
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS 1
-#define CONFIG_L2_OFF 1
+#define CONFIG_SYS_L2CACHE_OFF 1
#define CONFIG_INITRD_TAG 1
#define CONFIG_OF_LIBFDT 1
diff --git a/include/configs/cerf250.h b/include/configs/cerf250.h
index 9696487..7e179be 100644
--- a/include/configs/cerf250.h
+++ b/include/configs/cerf250.h
@@ -43,7 +43,7 @@
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
/* we will never enable dcache, because we have to setup MMU first */
-#define CONFIG_SYS_NO_DCACHE
+#define CONFIG_SYS_DCACHE_OFF
/*
* Size of malloc() pool
diff --git a/include/configs/cradle.h b/include/configs/cradle.h
index c21af38..21a8e64 100644
--- a/include/configs/cradle.h
+++ b/include/configs/cradle.h
@@ -38,7 +38,7 @@
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
/* we will never enable dcache, because we have to setup MMU first */
-#define CONFIG_SYS_NO_DCACHE
+#define CONFIG_SYS_DCACHE_OFF
#define CONFIG_SYS_TEXT_BASE 0x0
/*
* Size of malloc() pool
diff --git a/include/configs/csb226.h b/include/configs/csb226.h
index 505740c..dcfbc6e 100644
--- a/include/configs/csb226.h
+++ b/include/configs/csb226.h
@@ -44,7 +44,7 @@
/* for timer/console/ethernet */
/* we will never enable dcache, because we have to setup MMU first */
-#define CONFIG_SYS_NO_DCACHE
+#define CONFIG_SYS_DCACHE_OFF
#define CONFIG_SYS_TEXT_BASE 0x0
/*
* Hardware drivers
diff --git a/include/configs/dnp1110.h b/include/configs/dnp1110.h
index 69c6420..7d79d57 100644
--- a/include/configs/dnp1110.h
+++ b/include/configs/dnp1110.h
@@ -42,7 +42,7 @@
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
/* we will never enable dcache, because we have to setup MMU first */
-#define CONFIG_SYS_NO_DCACHE
+#define CONFIG_SYS_DCACHE_OFF
/*
* Size of malloc() pool
diff --git a/include/configs/efikamx.h b/include/configs/efikamx.h
index 571c3cb..a04ac49 100644
--- a/include/configs/efikamx.h
+++ b/include/configs/efikamx.h
@@ -38,7 +38,7 @@
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
-#define CONFIG_L2_OFF
+#define CONFIG_SYS_L2CACHE_OFF
/*
* Bootloader Components Configuration
diff --git a/include/configs/evb4510.h b/include/configs/evb4510.h
index fb05727..23a2efa 100644
--- a/include/configs/evb4510.h
+++ b/include/configs/evb4510.h
@@ -43,7 +43,8 @@
#define CONFIG_ARM_THUMB 1 /* this is an ARM7TDMI */
#define CONFIG_S3C4510B 1 /* it's a S3C4510B chip */
#define CONFIG_EVB4510 1 /* on an EVB4510 Board */
-#define CONFIG_SYS_NO_CP15_CACHE
+#define CONFIG_SYS_ICACHE_OFF
+#define CONFIG_SYS_DCACHE_OFF
#define CONFIG_USE_IRQ
#define CONFIG_STACKSIZE_IRQ (4*1024)
diff --git a/include/configs/gcplus.h b/include/configs/gcplus.h
index fd39ab4..9412daa 100644
--- a/include/configs/gcplus.h
+++ b/include/configs/gcplus.h
@@ -49,7 +49,7 @@
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
/* we will never enable dcache, because we have to setup MMU first */
-#define CONFIG_SYS_NO_DCACHE
+#define CONFIG_SYS_DCACHE_OFF
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS 1
diff --git a/include/configs/innokom.h b/include/configs/innokom.h
index 744d65c..2e4b346 100644
--- a/include/configs/innokom.h
+++ b/include/configs/innokom.h
@@ -43,7 +43,7 @@
#define CONFIG_SYS_TEXT_BASE 0x0
/* we will never enable dcache, because we have to setup MMU first */
-#define CONFIG_SYS_NO_DCACHE
+#define CONFIG_SYS_DCACHE_OFF
/*
* Hardware drivers
diff --git a/include/configs/jornada.h b/include/configs/jornada.h
index 41b09aa..84ad2d8 100644
--- a/include/configs/jornada.h
+++ b/include/configs/jornada.h
@@ -32,7 +32,7 @@
#define CONFIG_SYS_TEXT_BASE 0xC1F00000
/* we will never enable dcache, because we have to setup MMU first */
-#define CONFIG_SYS_NO_DCACHE
+#define CONFIG_SYS_DCACHE_OFF
#undef CONFIG_USE_IRQ
/* Console setting */
diff --git a/include/configs/lart.h b/include/configs/lart.h
index 795cf34..7316b23 100644
--- a/include/configs/lart.h
+++ b/include/configs/lart.h
@@ -36,7 +36,7 @@
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
/* we will never enable dcache, because we have to setup MMU first */
-#define CONFIG_SYS_NO_DCACHE
+#define CONFIG_SYS_DCACHE_OFF
/*
* Size of malloc() pool
diff --git a/include/configs/lubbock.h b/include/configs/lubbock.h
index b7d53b6..b6ee919 100644
--- a/include/configs/lubbock.h
+++ b/include/configs/lubbock.h
@@ -47,7 +47,7 @@
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
/* we will never enable dcache, because we have to setup MMU first */
-#define CONFIG_SYS_NO_DCACHE
+#define CONFIG_SYS_DCACHE_OFF
/*
* Size of malloc() pool
diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h
index 207b20c..fd42afc 100644
--- a/include/configs/mx51evk.h
+++ b/include/configs/mx51evk.h
@@ -35,7 +35,7 @@
#define CONFIG_SYS_TEXT_BASE 0x97800000
-#define CONFIG_L2_OFF
+#define CONFIG_SYS_L2CACHE_OFF
#include <asm/arch/imx-regs.h>
/*
diff --git a/include/configs/mx53evk.h b/include/configs/mx53evk.h
index 78122a7..5f54035 100644
--- a/include/configs/mx53evk.h
+++ b/include/configs/mx53evk.h
@@ -29,7 +29,7 @@
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
-#define CONFIG_L2_OFF
+#define CONFIG_SYS_L2CACHE_OFF
#include <asm/arch/imx-regs.h>
diff --git a/include/configs/omap4_panda.h b/include/configs/omap4_panda.h
index b4e7f41..ab878f9 100644
--- a/include/configs/omap4_panda.h
+++ b/include/configs/omap4_panda.h
@@ -46,7 +46,7 @@
#define CONFIG_DISPLAY_BOARDINFO 1
/* Keep L2 Cache Disabled */
-#define CONFIG_L2_OFF 1
+#define CONFIG_SYS_L2CACHE_OFF 1
/* Clock Defines */
#define V_OSCK 38400000 /* Clock output from T2 */
diff --git a/include/configs/omap4_sdp4430.h b/include/configs/omap4_sdp4430.h
index 584a52b..0ac407a 100644
--- a/include/configs/omap4_sdp4430.h
+++ b/include/configs/omap4_sdp4430.h
@@ -47,7 +47,7 @@
#define CONFIG_DISPLAY_BOARDINFO 1
/* Keep L2 Cache Disabled */
-#define CONFIG_L2_OFF 1
+#define CONFIG_SYS_L2CACHE_OFF 1
/* Clock Defines */
#define V_OSCK 38400000 /* Clock output from T2 */
diff --git a/include/configs/pleb2.h b/include/configs/pleb2.h
index 9dbb406..ad82213 100644
--- a/include/configs/pleb2.h
+++ b/include/configs/pleb2.h
@@ -44,7 +44,7 @@
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
/* we will never enable dcache, because we have to setup MMU first */
-#define CONFIG_SYS_NO_DCACHE
+#define CONFIG_SYS_DCACHE_OFF
/*
* Size of malloc() pool
diff --git a/include/configs/pxa255_idp.h b/include/configs/pxa255_idp.h
index c1c7f80..e591d87 100644
--- a/include/configs/pxa255_idp.h
+++ b/include/configs/pxa255_idp.h
@@ -69,7 +69,7 @@
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
/* we will never enable dcache, because we have to setup MMU first */
-#define CONFIG_SYS_NO_DCACHE
+#define CONFIG_SYS_DCACHE_OFF
/*
* Size of malloc() pool
diff --git a/include/configs/s5pc210_universal.h b/include/configs/s5pc210_universal.h
index 5915984..bbe104b 100644
--- a/include/configs/s5pc210_universal.h
+++ b/include/configs/s5pc210_universal.h
@@ -43,7 +43,7 @@
#define CONFIG_DISPLAY_BOARDINFO
/* Keep L2 Cache Disabled */
-#define CONFIG_L2_OFF 1
+#define CONFIG_SYS_L2CACHE_OFF 1
#define CONFIG_SYS_SDRAM_BASE 0x40000000
#define CONFIG_SYS_TEXT_BASE 0x44800000
diff --git a/include/configs/shannon.h b/include/configs/shannon.h
index c0e6643..fce4121 100644
--- a/include/configs/shannon.h
+++ b/include/configs/shannon.h
@@ -44,7 +44,7 @@
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
/* we will never enable dcache, because we have to setup MMU first */
-#define CONFIG_SYS_NO_DCACHE
+#define CONFIG_SYS_DCACHE_OFF
/*
* Size of malloc() pool
diff --git a/include/configs/tegra2-common.h b/include/configs/tegra2-common.h
index febce35..2d36d23 100644
--- a/include/configs/tegra2-common.h
+++ b/include/configs/tegra2-common.h
@@ -31,7 +31,7 @@
#define CONFIG_ARMCORTEXA9 /* This is an ARM V7 CPU core */
#define CONFIG_TEGRA2 /* in a NVidia Tegra2 core */
#define CONFIG_MACH_TEGRA_GENERIC /* which is a Tegra generic machine */
-#define CONFIG_L2_OFF /* No L2 cache */
+#define CONFIG_SYS_L2CACHE_OFF /* No L2 cache */
#define CONFIG_ENABLE_CORTEXA9 /* enable CPU (A9 complex) */
diff --git a/include/configs/trizepsiv.h b/include/configs/trizepsiv.h
index 2512f93..ec052c4 100644
--- a/include/configs/trizepsiv.h
+++ b/include/configs/trizepsiv.h
@@ -49,7 +49,7 @@
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
/* we will never enable dcache, because we have to setup MMU first */
-#define CONFIG_SYS_NO_DCACHE
+#define CONFIG_SYS_DCACHE_OFF
#define RTC
diff --git a/include/configs/vision2.h b/include/configs/vision2.h
index 66795b5..50c920d 100644
--- a/include/configs/vision2.h
+++ b/include/configs/vision2.h
@@ -26,7 +26,7 @@
#define CONFIG_MX51 /* in a mx51 */
-#define CONFIG_L2_OFF
+#define CONFIG_SYS_L2CACHE_OFF
#define CONFIG_SYS_TEXT_BASE 0x97800000
#include <asm/arch/imx-regs.h>
diff --git a/include/configs/xaeniax.h b/include/configs/xaeniax.h
index a75c426..205e86c 100644
--- a/include/configs/xaeniax.h
+++ b/include/configs/xaeniax.h
@@ -51,7 +51,7 @@
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
/* we will never enable dcache, because we have to setup MMU first */
-#define CONFIG_SYS_NO_DCACHE
+#define CONFIG_SYS_DCACHE_OFF
/*
* select serial console configuration
diff --git a/include/configs/xm250.h b/include/configs/xm250.h
index 232baf3..39d0da7 100644
--- a/include/configs/xm250.h
+++ b/include/configs/xm250.h
@@ -38,7 +38,7 @@
#define CONFIG_SYS_TEXT_BASE 0x0
/* we will never enable dcache, because we have to setup MMU first */
-#define CONFIG_SYS_NO_DCACHE
+#define CONFIG_SYS_DCACHE_OFF
/*
* Size of malloc() pool; this lives below the uppermost 128 KiB which are
diff --git a/include/configs/zylonite.h b/include/configs/zylonite.h
index 1e03b01..5f153e3 100644
--- a/include/configs/zylonite.h
+++ b/include/configs/zylonite.h
@@ -48,7 +48,7 @@
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
/* we will never enable dcache, because we have to setup MMU first */
-#define CONFIG_SYS_NO_DCACHE
+#define CONFIG_SYS_DCACHE_OFF
/*
* Size of malloc() pool
--
1.7.0.4
next prev parent reply other threads:[~2011-06-17 9:30 UTC|newest]
Thread overview: 105+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-03-08 13:07 [U-Boot] [PATCH v2 00/10] armv7: cache maintenance operations Aneesh V
2011-03-08 13:07 ` [U-Boot] [PATCH v2 01/10] arm: make default implementation of cache_flush() weakly linked Aneesh V
2011-03-08 13:07 ` [U-Boot] [PATCH v2 02/10] armv7: add miscellaneous utility macros Aneesh V
2011-03-08 13:07 ` [U-Boot] [PATCH v2 03/10] armv7: cache maintenance operations for armv7 Aneesh V
2011-03-08 13:07 ` [U-Boot] [PATCH v2 04/10] armv7: replace CONFIG_L2_OFF with CONFIG_SYS_NO_L2CACHE Aneesh V
2011-03-08 13:07 ` [U-Boot] [PATCH v2 05/10] armv7: integrate cache maintenance support Aneesh V
2011-03-08 13:07 ` [U-Boot] [PATCH v2 06/10] arm: minor fixes for cache and mmu handling Aneesh V
2011-03-08 13:07 ` [U-Boot] [PATCH v2 07/10] armv7: add PL310 support to u-boot Aneesh V
2011-03-08 13:07 ` [U-Boot] [PATCH v2 08/10] armv7: adapt omap4 to the new cache maintenance framework Aneesh V
2011-03-08 13:07 ` [U-Boot] [PATCH v2 09/10] armv7: adapt omap3 " Aneesh V
2011-03-08 13:07 ` [U-Boot] [PATCH v2 10/10] armv7: adapt s5pc1xx " Aneesh V
2011-04-27 1:05 ` [U-Boot] [PATCH v2 00/10] armv7: cache maintenance operations Simon Glass
2011-05-05 4:48 ` Simon Glass
2011-05-10 10:25 ` Aneesh V
2011-05-12 12:11 ` [U-Boot] [PATCH v3 " Aneesh V
2011-05-12 12:11 ` [U-Boot] [PATCH v3 01/10] arm: make default implementation of cache_flush() weakly linked Aneesh V
2011-05-12 12:11 ` [U-Boot] [PATCH v3 02/10] armv7: add miscellaneous utility macros Aneesh V
2011-05-15 18:44 ` Wolfgang Denk
2011-05-15 22:15 ` Simon Glass
2011-05-16 2:23 ` Eric Cooper
2011-05-16 14:50 ` Simon Glass
2011-05-16 15:52 ` Wolfgang Denk
2011-05-16 5:51 ` Wolfgang Denk
2011-05-17 3:47 ` Simon Glass
2011-05-17 5:27 ` Wolfgang Denk
2011-05-17 8:44 ` Aneesh V
2011-05-17 9:27 ` Wolfgang Denk
2011-05-31 7:54 ` V, Aneesh
2011-06-01 2:13 ` Simon Glass
2011-06-01 6:01 ` Aneesh V
2011-05-16 15:07 ` Aneesh V
2011-06-06 15:57 ` Aneesh V
2011-06-06 18:50 ` Wolfgang Denk
2011-06-07 9:01 ` Aneesh V
2011-06-07 10:39 ` Wolfgang Denk
2011-06-07 12:14 ` Aneesh V
2011-06-07 15:19 ` Simon Glass
2011-06-07 15:40 ` Wolfgang Denk
2011-06-08 11:53 ` Aneesh V
2011-06-08 21:41 ` Wolfgang Denk
2011-06-14 8:45 ` Aneesh V
2011-06-14 10:51 ` Wolfgang Denk
2011-06-14 11:39 ` Aneesh V
2011-06-14 13:53 ` Wolfgang Denk
2011-06-14 15:11 ` Simon Glass
2011-06-14 18:54 ` Wolfgang Denk
2011-06-15 15:19 ` Simon Glass
2011-06-15 8:48 ` Aneesh V
2011-06-15 9:20 ` Wolfgang Denk
2011-06-15 11:01 ` Aneesh V
2011-06-15 12:04 ` Wolfgang Denk
2011-06-15 12:42 ` Graeme Russ
2011-06-15 12:51 ` Wolfgang Denk
2011-06-15 13:03 ` Graeme Russ
2011-06-16 11:07 ` Graeme Russ
2011-06-16 11:46 ` Wolfgang Denk
2011-06-16 23:58 ` Graeme Russ
2011-06-16 5:39 ` Aneesh V
2011-06-16 6:19 ` Graeme Russ
2011-06-16 8:15 ` Wolfgang Denk
2011-06-16 11:10 ` Graeme Russ
2011-05-12 12:11 ` [U-Boot] [PATCH v3 03/10] armv7: cache maintenance operations for armv7 Aneesh V
2011-05-15 18:51 ` Wolfgang Denk
2011-05-17 9:17 ` Aneesh V
2011-05-17 9:31 ` Wolfgang Denk
2011-05-17 9:37 ` Aneesh V
2011-05-17 9:58 ` Aneesh V
2011-06-16 14:17 ` Simon Glass
2011-05-12 12:11 ` [U-Boot] [PATCH v3 04/10] armv7: replace CONFIG_L2_OFF with CONFIG_SYS_NO_L2CACHE Aneesh V
2011-05-15 18:53 ` Wolfgang Denk
2011-05-17 9:59 ` Aneesh V
2011-05-17 11:09 ` Wolfgang Denk
2011-06-06 11:39 ` Aneesh V
2011-06-15 10:13 ` Wolfgang Denk
2011-05-12 12:11 ` [U-Boot] [PATCH v3 05/10] armv7: integrate cache maintenance support Aneesh V
2011-05-15 18:55 ` Wolfgang Denk
2011-05-17 10:20 ` Aneesh V
2011-05-17 11:14 ` Wolfgang Denk
2011-05-17 12:06 ` Aneesh V
2011-05-17 12:28 ` Wolfgang Denk
2011-05-17 13:28 ` Aneesh V
2011-05-17 21:37 ` Wolfgang Denk
2011-05-12 12:11 ` [U-Boot] [PATCH v3 06/10] arm: minor fixes for cache and mmu handling Aneesh V
2011-05-12 12:11 ` [U-Boot] [PATCH v3 07/10] armv7: add PL310 support to u-boot Aneesh V
2011-05-12 12:11 ` [U-Boot] [PATCH v3 08/10] armv7: adapt omap4 to the new cache maintenance framework Aneesh V
2011-05-15 18:57 ` Wolfgang Denk
2011-05-12 12:11 ` [U-Boot] [PATCH v3 09/10] armv7: adapt omap3 " Aneesh V
2011-05-15 18:58 ` Wolfgang Denk
2011-05-12 12:11 ` [U-Boot] [PATCH v3 10/10] armv7: adapt s5pc1xx " Aneesh V
2011-05-15 18:59 ` Wolfgang Denk
2011-06-17 9:30 ` [U-Boot] [PATCH v4 0/9] armv7: cache maintenance operations Aneesh V
2011-06-22 17:41 ` Albert ARIBAUD
2011-06-23 5:57 ` V, Aneesh
2011-06-23 19:24 ` Paulraj, Sandeep
2011-06-28 1:44 ` Minkyu Kang
2011-06-28 5:41 ` Albert ARIBAUD
2011-06-17 9:30 ` [U-Boot] [PATCH v4 1/9] arm: make default implementation of cache_flush() weakly linked Aneesh V
2011-06-17 9:30 ` [U-Boot] [PATCH v4 2/9] armv7: cache maintenance operations for armv7 Aneesh V
2011-06-17 9:30 ` Aneesh V [this message]
2011-06-17 9:30 ` [U-Boot] [PATCH v4 4/9] armv7: integrate cache maintenance support Aneesh V
2011-06-17 9:30 ` [U-Boot] [PATCH v4 5/9] arm: minor fixes for cache and mmu handling Aneesh V
2011-06-17 9:30 ` [U-Boot] [PATCH v4 6/9] armv7: add PL310 support to u-boot Aneesh V
2011-06-17 9:30 ` [U-Boot] [PATCH v4 7/9] armv7: adapt omap4 to the new cache maintenance framework Aneesh V
2011-06-17 9:30 ` [U-Boot] [PATCH v4 8/9] armv7: adapt omap3 " Aneesh V
2011-06-17 9:30 ` [U-Boot] [PATCH v4 9/9] armv7: adapt s5pc1xx " Aneesh V
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