[U-Boot] [PATCH 0/3] Fixups for P2041/P2040 support

[U-Boot] [PATCH 0/3] Fixups for P2041/P2040 support

[Kumar Gala]

We have a few minor differences between P2041 & P2040 that we need to
handle or we run into issues.  We also rename a few things to make the
P2041 the superset device.

P2040 is a reduced P2041 (missing 10g/XAUI and L2-cache).

- k

[U-Boot] [PATCH 1/3] powerpc/85xx: Rename P2040 id & SERDES to P2041

[Kumar Gala]

P2041 is the superset part that covers both P2040 & P2041.  The only
difference between the two devices is that P2041 supports 10g/XAUI and
has an L2 cache.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
 arch/powerpc/cpu/mpc85xx/Makefile       |    6 +-
 arch/powerpc/cpu/mpc85xx/p2040_ids.c    |  109 -------------------------------
 arch/powerpc/cpu/mpc85xx/p2040_serdes.c |   90 -------------------------
 arch/powerpc/cpu/mpc85xx/p2041_ids.c    |  109 +++++++++++++++++++++++++++++++
 arch/powerpc/cpu/mpc85xx/p2041_serdes.c |   90 +++++++++++++++++++++++++
 5 files changed, 202 insertions(+), 202 deletions(-)
 delete mode 100644 arch/powerpc/cpu/mpc85xx/p2040_ids.c
 delete mode 100644 arch/powerpc/cpu/mpc85xx/p2040_serdes.c
 create mode 100644 arch/powerpc/cpu/mpc85xx/p2041_ids.c
 create mode 100644 arch/powerpc/cpu/mpc85xx/p2041_serdes.c

diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile
index 222ea7e..d6ec611 100644
--- a/arch/powerpc/cpu/mpc85xx/Makefile
+++ b/arch/powerpc/cpu/mpc85xx/Makefile
@@ -78,8 +78,8 @@ COBJS-$(CONFIG_PCI)	+= pci.o
 COBJS-$(CONFIG_SYS_DPAA_QBMAN) += portals.o
 
 # various SoC specific assignments
-COBJS-$(CONFIG_PPC_P2040) += p2040_ids.o
-COBJS-$(CONFIG_PPC_P2041) += p2040_ids.o
+COBJS-$(CONFIG_PPC_P2040) += p2041_ids.o
+COBJS-$(CONFIG_PPC_P2041) += p2041_ids.o
 COBJS-$(CONFIG_PPC_P3041) += p3041_ids.o
 COBJS-$(CONFIG_PPC_P4080) += p4080_ids.o
 COBJS-$(CONFIG_PPC_P5020) += p5020_ids.o
@@ -113,7 +113,7 @@ COBJS-$(CONFIG_P1024)	+= p1021_serdes.o
 COBJS-$(CONFIG_P1025)	+= p1021_serdes.o
 COBJS-$(CONFIG_P2010)	+= p2020_serdes.o
 COBJS-$(CONFIG_P2020)	+= p2020_serdes.o
-COBJS-$(CONFIG_PPC_P2040) += p2040_serdes.o
+COBJS-$(CONFIG_PPC_P2040) += p2041_serdes.o
 COBJS-$(CONFIG_PPC_P2041) += p2041_serdes.o
 COBJS-$(CONFIG_PPC_P3041) += p3041_serdes.o
 COBJS-$(CONFIG_PPC_P4080) += p4080_serdes.o
diff --git a/arch/powerpc/cpu/mpc85xx/p2040_ids.c b/arch/powerpc/cpu/mpc85xx/p2040_ids.c
deleted file mode 100644
index 112ea56..0000000
--- a/arch/powerpc/cpu/mpc85xx/p2040_ids.c
+++ /dev/null
@@ -1,109 +0,0 @@
-/*
- * Copyright 2011 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/fsl_portals.h>
-#include <asm/fsl_liodn.h>
-
-#ifdef CONFIG_SYS_DPAA_QBMAN
-struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
-	/* dqrr liodn, frame data liodn, liodn off, sdest */
-	SET_QP_INFO( 1,  2,  1, 0),
-	SET_QP_INFO( 3,  4,  2, 1),
-	SET_QP_INFO( 5,  6,  3, 2),
-	SET_QP_INFO( 7,  8,  4, 3),
-	SET_QP_INFO( 9, 10,  5, 4),
-	SET_QP_INFO( 0,  0,  0, 5),
-	SET_QP_INFO( 0,  0,  0, 6),
-	SET_QP_INFO( 0,  0,  0, 7),
-	SET_QP_INFO( 0,  0,  0, 0), /* for now sdest to 0 */
-	SET_QP_INFO( 0,  0,  0, 0), /* for now sdest to 0 */
-};
-#endif
-
-struct liodn_id_table liodn_tbl[] = {
-#ifdef CONFIG_SYS_DPAA_QBMAN
-	SET_QMAN_LIODN(31),
-	SET_BMAN_LIODN(32),
-#endif
-
-	SET_SDHC_LIODN(1, 64),
-
-	SET_PME_LIODN(117),
-
-	SET_USB_LIODN(1, "fsl-usb2-mph", 125),
-	SET_USB_LIODN(2, "fsl-usb2-dr", 126),
-
-	SET_SATA_LIODN(1, 127),
-	SET_SATA_LIODN(2, 128),
-
-	SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 1, 193),
-	SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 2, 194),
-	SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 3, 195),
-
-	SET_DMA_LIODN(1, 197),
-	SET_DMA_LIODN(2, 198),
-
-	SET_GUTS_LIODN("fsl,rapidio-delta", 199, rio1liodnr, 0),
-	SET_GUTS_LIODN(NULL, 200, rio2liodnr, 0),
-	SET_GUTS_LIODN(NULL, 201, rio1maintliodnr, 0),
-	SET_GUTS_LIODN(NULL, 202, rio2maintliodnr, 0),
-};
-int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl);
-
-#ifdef CONFIG_SYS_DPAA_FMAN
-struct liodn_id_table fman1_liodn_tbl[] = {
-	SET_FMAN_RX_1G_LIODN(1, 0, 10),
-	SET_FMAN_RX_1G_LIODN(1, 1, 11),
-	SET_FMAN_RX_1G_LIODN(1, 2, 12),
-	SET_FMAN_RX_1G_LIODN(1, 3, 13),
-	SET_FMAN_RX_1G_LIODN(1, 4, 14),
-#if (CONFIG_SYS_NUM_FM1_10GEC == 1)
-	SET_FMAN_RX_10G_LIODN(1, 0, 15),
-#endif
-};
-int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl);
-#endif
-
-struct liodn_id_table sec_liodn_tbl[] = {
-	SET_SEC_JR_LIODN_ENTRY(0, 129, 130),
-	SET_SEC_JR_LIODN_ENTRY(1, 131, 132),
-	SET_SEC_JR_LIODN_ENTRY(2, 133, 134),
-	SET_SEC_JR_LIODN_ENTRY(3, 135, 136),
-	SET_SEC_RTIC_LIODN_ENTRY(a, 154),
-	SET_SEC_RTIC_LIODN_ENTRY(b, 155),
-	SET_SEC_RTIC_LIODN_ENTRY(c, 156),
-	SET_SEC_RTIC_LIODN_ENTRY(d, 157),
-	SET_SEC_DECO_LIODN_ENTRY(0, 97, 98),
-	SET_SEC_DECO_LIODN_ENTRY(1, 99, 100),
-};
-int sec_liodn_tbl_sz = ARRAY_SIZE(sec_liodn_tbl);
-
-struct liodn_id_table liodn_bases[] = {
-	[FSL_HW_PORTAL_SEC]  = SET_LIODN_BASE_2(64, 100),
-#ifdef CONFIG_SYS_DPAA_FMAN
-	[FSL_HW_PORTAL_FMAN1] = SET_LIODN_BASE_1(32),
-#endif
-#ifdef CONFIG_SYS_DPAA_PME
-	[FSL_HW_PORTAL_PME]   = SET_LIODN_BASE_2(136, 172),
-#endif
-};
diff --git a/arch/powerpc/cpu/mpc85xx/p2040_serdes.c b/arch/powerpc/cpu/mpc85xx/p2040_serdes.c
deleted file mode 100644
index 83bc82f..0000000
--- a/arch/powerpc/cpu/mpc85xx/p2040_serdes.c
+++ /dev/null
@@ -1,90 +0,0 @@
-/*
- * Copyright 2010-2011 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/fsl_serdes.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include "fsl_corenet_serdes.h"
-
-static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = {
-	[0x2] = {NONE, NONE, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1,
-		NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
-		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE, },
-	[0x5] = {NONE, NONE, PCIE1, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2,
-		NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
-		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE, },
-	[0x8] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2,
-		PCIE2, PCIE2, PCIE2, NONE, NONE, NONE, NONE, SATA1,
-		SATA2, NONE, NONE, NONE, NONE, },
-	[0x9] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2,
-		PCIE2, PCIE2, PCIE2, NONE, NONE, NONE, NONE,
-		NONE, NONE, NONE, NONE, NONE, NONE, },
-	[0xa] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2,
-		PCIE2, PCIE2, PCIE2, NONE, NONE, PCIE3, PCIE3, PCIE3,
-		PCIE3, NONE, NONE, NONE, NONE, },
-	[0xf] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SRIO2,
-		SRIO2, SRIO1, SRIO1, NONE, NONE, PCIE3, SGMII_FM1_DTSEC5,
-		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE, },
-	[0x14] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2,
-		PCIE2, SRIO1, SRIO1, NONE, NONE, AURORA,
-		SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE,
-		NONE, NONE, NONE, },
-	[0x16] = {NONE, NONE, PCIE1, PCIE3, PCIE2, PCIE2, SGMII_FM1_DTSEC3,
-		SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE, SATA1, SATA2, NONE,
-		NONE, NONE, NONE, },
-	[0x17] = {NONE, NONE, PCIE1, PCIE3, PCIE2, PCIE2, SGMII_FM1_DTSEC3,
-		SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE, NONE,
-		NONE, NONE, NONE, NONE, NONE, },
-	[0x19] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2,
-		PCIE2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE,
-		NONE, NONE, SATA1, SATA2, NONE, NONE, NONE, NONE, },
-	[0x1a] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SRIO2,
-		SRIO2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE,
-		NONE, NONE, SATA1, SATA2, NONE, NONE, NONE, NONE, },
-	[0x1c] = {NONE, NONE, PCIE1, SGMII_FM1_DTSEC2, PCIE2, PCIE2,
-		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, AURORA,
-		SGMII_FM1_DTSEC5, NONE, NONE, NONE, NONE, NONE, NONE, },
-};
-
-enum srds_prtcl serdes_get_prtcl(int cfg, int lane)
-{
-	if (!serdes_lane_enabled(lane))
-		return NONE;
-
-	return serdes_cfg_tbl[cfg][lane];
-}
-
-int is_serdes_prtcl_valid(u32 prtcl)
-{
-	int i;
-
-	if (prtcl > ARRAY_SIZE(serdes_cfg_tbl))
-		return 0;
-
-	for (i = 0; i < SRDS_MAX_LANES; i++) {
-		if (serdes_cfg_tbl[prtcl][i] != NONE)
-			return 1;
-	}
-
-	return 0;
-}
diff --git a/arch/powerpc/cpu/mpc85xx/p2041_ids.c b/arch/powerpc/cpu/mpc85xx/p2041_ids.c
new file mode 100644
index 0000000..112ea56
--- /dev/null
+++ b/arch/powerpc/cpu/mpc85xx/p2041_ids.c
@@ -0,0 +1,109 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+
+#ifdef CONFIG_SYS_DPAA_QBMAN
+struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
+	/* dqrr liodn, frame data liodn, liodn off, sdest */
+	SET_QP_INFO( 1,  2,  1, 0),
+	SET_QP_INFO( 3,  4,  2, 1),
+	SET_QP_INFO( 5,  6,  3, 2),
+	SET_QP_INFO( 7,  8,  4, 3),
+	SET_QP_INFO( 9, 10,  5, 4),
+	SET_QP_INFO( 0,  0,  0, 5),
+	SET_QP_INFO( 0,  0,  0, 6),
+	SET_QP_INFO( 0,  0,  0, 7),
+	SET_QP_INFO( 0,  0,  0, 0), /* for now sdest to 0 */
+	SET_QP_INFO( 0,  0,  0, 0), /* for now sdest to 0 */
+};
+#endif
+
+struct liodn_id_table liodn_tbl[] = {
+#ifdef CONFIG_SYS_DPAA_QBMAN
+	SET_QMAN_LIODN(31),
+	SET_BMAN_LIODN(32),
+#endif
+
+	SET_SDHC_LIODN(1, 64),
+
+	SET_PME_LIODN(117),
+
+	SET_USB_LIODN(1, "fsl-usb2-mph", 125),
+	SET_USB_LIODN(2, "fsl-usb2-dr", 126),
+
+	SET_SATA_LIODN(1, 127),
+	SET_SATA_LIODN(2, 128),
+
+	SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 1, 193),
+	SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 2, 194),
+	SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 3, 195),
+
+	SET_DMA_LIODN(1, 197),
+	SET_DMA_LIODN(2, 198),
+
+	SET_GUTS_LIODN("fsl,rapidio-delta", 199, rio1liodnr, 0),
+	SET_GUTS_LIODN(NULL, 200, rio2liodnr, 0),
+	SET_GUTS_LIODN(NULL, 201, rio1maintliodnr, 0),
+	SET_GUTS_LIODN(NULL, 202, rio2maintliodnr, 0),
+};
+int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl);
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+struct liodn_id_table fman1_liodn_tbl[] = {
+	SET_FMAN_RX_1G_LIODN(1, 0, 10),
+	SET_FMAN_RX_1G_LIODN(1, 1, 11),
+	SET_FMAN_RX_1G_LIODN(1, 2, 12),
+	SET_FMAN_RX_1G_LIODN(1, 3, 13),
+	SET_FMAN_RX_1G_LIODN(1, 4, 14),
+#if (CONFIG_SYS_NUM_FM1_10GEC == 1)
+	SET_FMAN_RX_10G_LIODN(1, 0, 15),
+#endif
+};
+int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl);
+#endif
+
+struct liodn_id_table sec_liodn_tbl[] = {
+	SET_SEC_JR_LIODN_ENTRY(0, 129, 130),
+	SET_SEC_JR_LIODN_ENTRY(1, 131, 132),
+	SET_SEC_JR_LIODN_ENTRY(2, 133, 134),
+	SET_SEC_JR_LIODN_ENTRY(3, 135, 136),
+	SET_SEC_RTIC_LIODN_ENTRY(a, 154),
+	SET_SEC_RTIC_LIODN_ENTRY(b, 155),
+	SET_SEC_RTIC_LIODN_ENTRY(c, 156),
+	SET_SEC_RTIC_LIODN_ENTRY(d, 157),
+	SET_SEC_DECO_LIODN_ENTRY(0, 97, 98),
+	SET_SEC_DECO_LIODN_ENTRY(1, 99, 100),
+};
+int sec_liodn_tbl_sz = ARRAY_SIZE(sec_liodn_tbl);
+
+struct liodn_id_table liodn_bases[] = {
+	[FSL_HW_PORTAL_SEC]  = SET_LIODN_BASE_2(64, 100),
+#ifdef CONFIG_SYS_DPAA_FMAN
+	[FSL_HW_PORTAL_FMAN1] = SET_LIODN_BASE_1(32),
+#endif
+#ifdef CONFIG_SYS_DPAA_PME
+	[FSL_HW_PORTAL_PME]   = SET_LIODN_BASE_2(136, 172),
+#endif
+};
diff --git a/arch/powerpc/cpu/mpc85xx/p2041_serdes.c b/arch/powerpc/cpu/mpc85xx/p2041_serdes.c
new file mode 100644
index 0000000..83bc82f
--- /dev/null
+++ b/arch/powerpc/cpu/mpc85xx/p2041_serdes.c
@@ -0,0 +1,90 @@
+/*
+ * Copyright 2010-2011 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_serdes.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include "fsl_corenet_serdes.h"
+
+static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = {
+	[0x2] = {NONE, NONE, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1,
+		NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE, },
+	[0x5] = {NONE, NONE, PCIE1, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2,
+		NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE, },
+	[0x8] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2,
+		PCIE2, PCIE2, PCIE2, NONE, NONE, NONE, NONE, SATA1,
+		SATA2, NONE, NONE, NONE, NONE, },
+	[0x9] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2,
+		PCIE2, PCIE2, PCIE2, NONE, NONE, NONE, NONE,
+		NONE, NONE, NONE, NONE, NONE, NONE, },
+	[0xa] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2,
+		PCIE2, PCIE2, PCIE2, NONE, NONE, PCIE3, PCIE3, PCIE3,
+		PCIE3, NONE, NONE, NONE, NONE, },
+	[0xf] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SRIO2,
+		SRIO2, SRIO1, SRIO1, NONE, NONE, PCIE3, SGMII_FM1_DTSEC5,
+		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE, },
+	[0x14] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2,
+		PCIE2, SRIO1, SRIO1, NONE, NONE, AURORA,
+		SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE,
+		NONE, NONE, NONE, },
+	[0x16] = {NONE, NONE, PCIE1, PCIE3, PCIE2, PCIE2, SGMII_FM1_DTSEC3,
+		SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE, SATA1, SATA2, NONE,
+		NONE, NONE, NONE, },
+	[0x17] = {NONE, NONE, PCIE1, PCIE3, PCIE2, PCIE2, SGMII_FM1_DTSEC3,
+		SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE, NONE,
+		NONE, NONE, NONE, NONE, NONE, },
+	[0x19] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2,
+		PCIE2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE,
+		NONE, NONE, SATA1, SATA2, NONE, NONE, NONE, NONE, },
+	[0x1a] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SRIO2,
+		SRIO2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE,
+		NONE, NONE, SATA1, SATA2, NONE, NONE, NONE, NONE, },
+	[0x1c] = {NONE, NONE, PCIE1, SGMII_FM1_DTSEC2, PCIE2, PCIE2,
+		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, AURORA,
+		SGMII_FM1_DTSEC5, NONE, NONE, NONE, NONE, NONE, NONE, },
+};
+
+enum srds_prtcl serdes_get_prtcl(int cfg, int lane)
+{
+	if (!serdes_lane_enabled(lane))
+		return NONE;
+
+	return serdes_cfg_tbl[cfg][lane];
+}
+
+int is_serdes_prtcl_valid(u32 prtcl)
+{
+	int i;
+
+	if (prtcl > ARRAY_SIZE(serdes_cfg_tbl))
+		return 0;
+
+	for (i = 0; i < SRDS_MAX_LANES; i++) {
+		if (serdes_cfg_tbl[prtcl][i] != NONE)
+			return 1;
+	}
+
+	return 0;
+}
-- 
1.7.3.4

[U-Boot] [PATCH 2/3] powerpc/85xx: Add support for P2041[e] XAUI in SERDES

[Kumar Gala]

We add XAUI_FM1 into the SERDES tables for P2041[e] devices.  However
for the P2040[e] devices that dont support XAUI we handle this at
runtime via SVR checks.  If we are on a P2040[e] device the SERDES
functions will behave as follows:

is_serdes_prtcl_valid() will always report invalid if prtcl passed in is
XAUI_FM1.

serdes_get_prtcl() will report NONE if the prtcl in the table is set to
XAUI_FM1.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
 arch/powerpc/cpu/mpc85xx/p2041_serdes.c |   26 +++++++++++++++++++++-----
 1 files changed, 21 insertions(+), 5 deletions(-)

diff --git a/arch/powerpc/cpu/mpc85xx/p2041_serdes.c b/arch/powerpc/cpu/mpc85xx/p2041_serdes.c
index 83bc82f..f68f281 100644
--- a/arch/powerpc/cpu/mpc85xx/p2041_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/p2041_serdes.c
@@ -37,8 +37,8 @@ static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = {
 		PCIE2, PCIE2, PCIE2, NONE, NONE, NONE, NONE, SATA1,
 		SATA2, NONE, NONE, NONE, NONE, },
 	[0x9] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2,
-		PCIE2, PCIE2, PCIE2, NONE, NONE, NONE, NONE,
-		NONE, NONE, NONE, NONE, NONE, NONE, },
+		PCIE2, PCIE2, PCIE2, NONE, NONE, XAUI_FM1, XAUI_FM1,
+		XAUI_FM1, XAUI_FM1, NONE, NONE, NONE, NONE, },
 	[0xa] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2,
 		PCIE2, PCIE2, PCIE2, NONE, NONE, PCIE3, PCIE3, PCIE3,
 		PCIE3, NONE, NONE, NONE, NONE, },
@@ -53,8 +53,8 @@ static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = {
 		SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE, SATA1, SATA2, NONE,
 		NONE, NONE, NONE, },
 	[0x17] = {NONE, NONE, PCIE1, PCIE3, PCIE2, PCIE2, SGMII_FM1_DTSEC3,
-		SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE, NONE,
-		NONE, NONE, NONE, NONE, NONE, },
+		SGMII_FM1_DTSEC4, NONE, NONE, XAUI_FM1, XAUI_FM1, XAUI_FM1,
+		XAUI_FM1, NONE, NONE, NONE, NONE, },
 	[0x19] = {NONE, NONE, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE2,
 		PCIE2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE,
 		NONE, NONE, SATA1, SATA2, NONE, NONE, NONE, NONE, },
@@ -68,19 +68,35 @@ static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = {
 
 enum srds_prtcl serdes_get_prtcl(int cfg, int lane)
 {
+	enum srds_prtcl prtcl;
+	u32 svr = get_svr();
+	u32 ver = SVR_SOC_VER(svr);
+
 	if (!serdes_lane_enabled(lane))
 		return NONE;
 
-	return serdes_cfg_tbl[cfg][lane];
+	prtcl = serdes_cfg_tbl[cfg][lane];
+
+	/* P2040[e] does not support XAUI */
+	if (((ver == SVR_P2040) || (ver == SVR_P2040_E)) && (prtcl == XAUI_FM1))
+		prtcl = NONE;
+
+	return prtcl;
 }
 
 int is_serdes_prtcl_valid(u32 prtcl)
 {
 	int i;
+	u32 svr = get_svr();
+	u32 ver = SVR_SOC_VER(svr);
 
 	if (prtcl > ARRAY_SIZE(serdes_cfg_tbl))
 		return 0;
 
+	/* P2040[e] does not support XAUI */
+	if (((ver == SVR_P2040) || (ver == SVR_P2040_E)) && (prtcl == XAUI_FM1))
+		return 0;
+
 	for (i = 0; i < SRDS_MAX_LANES; i++) {
 		if (serdes_cfg_tbl[prtcl][i] != NONE)
 			return 1;
-- 
1.7.3.4

[U-Boot] [PATCH 3/3] powerpc/85xx: Handle the lack of L2 cache on P2040/P2040E

[Kumar Gala]

The P2040/P2040E have no L2 cache.  So we utilize the SVR to determine
if we are one of these devices and skip the L2 init code in cpu_init.c
and release.  For the device tree we skip the updating of the L2 cache
properties but we still update the chain of caches so the CPC/L3 node
can be properly updated.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
 arch/powerpc/cpu/mpc85xx/cpu_init.c |    7 +++++++
 arch/powerpc/cpu/mpc85xx/fdt.c      |   23 +++++++++++++++--------
 arch/powerpc/cpu/mpc85xx/release.S  |   15 ++++++++++++++-
 3 files changed, 36 insertions(+), 9 deletions(-)

diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 6becd5b..cb63f49 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -389,6 +389,12 @@ int cpu_init_r(void)
 		puts("enabled\n");
 	}
 #elif defined(CONFIG_BACKSIDE_L2_CACHE)
+	if ((SVR_SOC_VER(get_svr()) == SVR_P2040) ||
+	    (SVR_SOC_VER(get_svr()) == SVR_P2040_E)) {
+		puts("N/A\n");
+		goto skip_l2;
+	}
+
 	u32 l2cfg0 = mfspr(SPRN_L2CFG0);
 
 	/* invalidate the L2 cache */
@@ -412,6 +418,7 @@ int cpu_init_r(void)
 #else
 	puts("disabled\n");
 #endif
+skip_l2:
 
 	enable_cpc();
 
diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c
index 0e8aed4..b237776 100644
--- a/arch/powerpc/cpu/mpc85xx/fdt.c
+++ b/arch/powerpc/cpu/mpc85xx/fdt.c
@@ -228,6 +228,12 @@ static inline void ft_fixup_l2cache(void *blob)
 	u32 *ph;
 	u32 l2cfg0 = mfspr(SPRN_L2CFG0);
 	u32 size, line_size, num_ways, num_sets;
+	int has_l2 = 1;
+
+	/* P2040/P2040E has no L2, so dont set any L2 props */
+	if ((SVR_SOC_VER(get_svr()) == SVR_P2040) ||
+	    (SVR_SOC_VER(get_svr()) == SVR_P2040_E))
+		has_l2 = 0;
 
 	size = (l2cfg0 & 0x3fff) * 64 * 1024;
 	num_ways = ((l2cfg0 >> 14) & 0x1f) + 1;
@@ -250,21 +256,22 @@ static inline void ft_fixup_l2cache(void *blob)
 			goto next;
 		}
 
+		if (has_l2) {
 #ifdef CONFIG_SYS_CACHE_STASHING
-		{
 			u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0);
 			if (reg)
 				fdt_setprop_cell(blob, l2_off, "cache-stash-id",
 					 (*reg * 2) + 32 + 1);
-		}
 #endif
 
-		fdt_setprop(blob, l2_off, "cache-unified", NULL, 0);
-		fdt_setprop_cell(blob, l2_off, "cache-block-size", line_size);
-		fdt_setprop_cell(blob, l2_off, "cache-size", size);
-		fdt_setprop_cell(blob, l2_off, "cache-sets", num_sets);
-		fdt_setprop_cell(blob, l2_off, "cache-level", 2);
-		fdt_setprop(blob, l2_off, "compatible", "cache", 6);
+			fdt_setprop(blob, l2_off, "cache-unified", NULL, 0);
+			fdt_setprop_cell(blob, l2_off, "cache-block-size",
+						line_size);
+			fdt_setprop_cell(blob, l2_off, "cache-size", size);
+			fdt_setprop_cell(blob, l2_off, "cache-sets", num_sets);
+			fdt_setprop_cell(blob, l2_off, "cache-level", 2);
+			fdt_setprop(blob, l2_off, "compatible", "cache", 6);
+		}
 
 		if (l3_off < 0) {
 			ph = (u32 *)fdt_getprop(blob, l2_off, "next-level-cache", 0);
diff --git a/arch/powerpc/cpu/mpc85xx/release.S b/arch/powerpc/cpu/mpc85xx/release.S
index 56a853e..6678ed4 100644
--- a/arch/powerpc/cpu/mpc85xx/release.S
+++ b/arch/powerpc/cpu/mpc85xx/release.S
@@ -1,5 +1,5 @@
 /*
- * Copyright 2008-2010 Freescale Semiconductor, Inc.
+ * Copyright 2008-2011 Freescale Semiconductor, Inc.
  * Kumar Gala <kumar.gala@freescale.com>
  *
  * See file CREDITS for list of people who contributed to this
@@ -144,6 +144,18 @@ __secondary_start_page:
 #endif
 
 #ifdef CONFIG_BACKSIDE_L2_CACHE
+	/* skip L2 setup on P2040/P2040E as they have no L2 */
+	mfspr	r2,SPRN_SVR
+	lis	r3,SVR_P2040 at h
+	ori	r3,r3,SVR_P2040 at l
+	cmpw	r2,r3
+	beq 3f
+
+	lis	r3,SVR_P2040_E at h
+	ori	r3,r3,SVR_P2040_E at l
+	cmpw	r2,r3
+	beq 3f
+
 	/* Enable/invalidate the L2 cache */
 	msync
 	lis	r2,(L2CSR0_L2FI|L2CSR0_L2LFC)@h
@@ -169,6 +181,7 @@ __secondary_start_page:
 	andis.	r1,r3,L2CSR0_L2E at h
 	beq	2b
 #endif
+3:
 
 #define EPAPR_MAGIC		(0x45504150)
 #define ENTRY_ADDR_UPPER	0
-- 
1.7.3.4

[U-Boot] [PATCH 1/3] powerpc/85xx: Rename P2040 id & SERDES to P2041

[Kumar Gala]

On Jul 21, 2011, at 12:20 AM, Kumar Gala wrote:

> P2041 is the superset part that covers both P2040 & P2041.  The only
> difference between the two devices is that P2041 supports 10g/XAUI and
> has an L2 cache.
> 
> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
> ---
> arch/powerpc/cpu/mpc85xx/Makefile       |    6 +-
> arch/powerpc/cpu/mpc85xx/p2040_ids.c    |  109 -------------------------------
> arch/powerpc/cpu/mpc85xx/p2040_serdes.c |   90 -------------------------
> arch/powerpc/cpu/mpc85xx/p2041_ids.c    |  109 +++++++++++++++++++++++++++++++
> arch/powerpc/cpu/mpc85xx/p2041_serdes.c |   90 +++++++++++++++++++++++++
> 5 files changed, 202 insertions(+), 202 deletions(-)
> delete mode 100644 arch/powerpc/cpu/mpc85xx/p2040_ids.c
> delete mode 100644 arch/powerpc/cpu/mpc85xx/p2040_serdes.c
> create mode 100644 arch/powerpc/cpu/mpc85xx/p2041_ids.c
> create mode 100644 arch/powerpc/cpu/mpc85xx/p2041_serdes.c

applied to 85xx

- k

[U-Boot] [PATCH 2/3] powerpc/85xx: Add support for P2041[e] XAUI in SERDES

[Kumar Gala]

On Jul 21, 2011, at 12:20 AM, Kumar Gala wrote:

> We add XAUI_FM1 into the SERDES tables for P2041[e] devices.  However
> for the P2040[e] devices that dont support XAUI we handle this at
> runtime via SVR checks.  If we are on a P2040[e] device the SERDES
> functions will behave as follows:
> 
> is_serdes_prtcl_valid() will always report invalid if prtcl passed in is
> XAUI_FM1.
> 
> serdes_get_prtcl() will report NONE if the prtcl in the table is set to
> XAUI_FM1.
> 
> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
> ---
> arch/powerpc/cpu/mpc85xx/p2041_serdes.c |   26 +++++++++++++++++++++-----
> 1 files changed, 21 insertions(+), 5 deletions(-)

applied to 85xx

- k

[U-Boot] [PATCH 3/3] powerpc/85xx: Handle the lack of L2 cache on P2040/P2040E

[Kumar Gala]

On Jul 21, 2011, at 12:20 AM, Kumar Gala wrote:

> The P2040/P2040E have no L2 cache.  So we utilize the SVR to determine
> if we are one of these devices and skip the L2 init code in cpu_init.c
> and release.  For the device tree we skip the updating of the L2 cache
> properties but we still update the chain of caches so the CPC/L3 node
> can be properly updated.
> 
> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
> ---
> arch/powerpc/cpu/mpc85xx/cpu_init.c |    7 +++++++
> arch/powerpc/cpu/mpc85xx/fdt.c      |   23 +++++++++++++++--------
> arch/powerpc/cpu/mpc85xx/release.S  |   15 ++++++++++++++-
> 3 files changed, 36 insertions(+), 9 deletions(-)

applied to 85xx

- k