[U-Boot] [PATCH 1/4] powerpc/85xx: Expanding the window of CCSRBAR in AS=1 from 4k to 1M

[U-Boot] [PATCH 1/4] powerpc/85xx: Expanding the window of CCSRBAR in AS=1 from 4k to 1M

[Kumar Gala]

From: Poonam Aggrwal <poonam.aggrwal@freescale.com>

For an IFC Erratum (A-003399) we will need to access IFC registers in
cpu_init_early_f() so expand the TLB covering CCSR to 1M.

Since we need a TLB to cover 1M we move to using TLB1 array for all the
early mappings so we can cover various sizes beyond 4k.

Additionally removed volatile from ccsr_virt declaration as its not needed
for IO accessors

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
 arch/powerpc/cpu/mpc85xx/cpu_init_early.c |   25 +++++++++++++++++--------
 1 files changed, 17 insertions(+), 8 deletions(-)

diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
index 32aa94b..97e8424 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
@@ -21,15 +21,24 @@
 #include <asm/processor.h>
 #include <asm/mmu.h>
 #include <asm/fsl_law.h>
+#include <asm/io.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
+/*
+ * We need a dummy virtual address to access the first 4k of CCSRBAR at.  This
+ * virtual address is while we are in AS=1 address space and should not conflict
+ * with CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_CCSRBAR or CONFIG_SYS_MONITOR_BASE.
+ * We use 0x1000 to make sure NULL access still cause some fault error
+ */
+#define CCSRBAR_VIRT_DUMMY	(0x1000)
+
 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS)
 #ifdef CONFIG_FSL_CORENET
 static void setup_ccsrbar(void)
 {
 	u32 temp;
-	volatile u32 *ccsr_virt = (volatile u32 *)(CONFIG_SYS_CCSRBAR + 0x1000);
+	u32 *ccsr_virt = (u32 *)(CCSRBAR_VIRT_DUMMY);
 	volatile ccsr_local_t *ccm;
 
 	/*
@@ -60,7 +69,7 @@ static void setup_ccsrbar(void)
 static void setup_ccsrbar(void)
 {
 	u32 temp;
-	volatile u32 *ccsr_virt = (volatile u32 *)(CONFIG_SYS_CCSRBAR + 0x1000);
+	u32 *ccsr_virt = (u32 *)(CCSRBAR_VIRT_DUMMY);
 
 	temp = in_be32(ccsr_virt);
 	out_be32(ccsr_virt, CONFIG_SYS_CCSRBAR_PHYS >> 12);
@@ -85,8 +94,8 @@ void cpu_init_early_f(void)
 	for (i = 0; i < sizeof(gd_t); i++)
 		((char *)gd)[i] = 0;
 
-	mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(0);
-	mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_TSIZE(BOOKE_PAGESZ_4K);
+	mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(13);
+	mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_TSIZE(BOOKE_PAGESZ_1M);
 	mas2 = FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G);
 	mas3 = FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS, 0, MAS3_SW|MAS3_SR);
 	mas7 = FSL_BOOKE_MAS7(CONFIG_SYS_CCSRBAR_PHYS);
@@ -95,9 +104,9 @@ void cpu_init_early_f(void)
 
 	/* set up CCSR if we want it moved */
 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS)
-	mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(1);
-	/* mas1 is the same as above */
-	mas2 = FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR + 0x1000, MAS2_I|MAS2_G);
+	mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(12);
+	mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_TSIZE(BOOKE_PAGESZ_4K);
+	mas2 = FSL_BOOKE_MAS2(CCSRBAR_VIRT_DUMMY, MAS2_I|MAS2_G);
 	mas3 = FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_DEFAULT, 0, MAS3_SW|MAS3_SR);
 	mas7 = FSL_BOOKE_MAS7(CONFIG_SYS_CCSRBAR_DEFAULT);
 
@@ -107,6 +116,6 @@ void cpu_init_early_f(void)
 #endif
 
 	init_laws();
-	invalidate_tlb(0);
+	invalidate_tlb(1);
 	init_tlbs();
 }
-- 
1.7.3.4

[U-Boot] [PATCH 2/4] fsl_ifc: Add the workaround for erratum IFC-A002769 (enable on P1010)

[Kumar Gala]

From: Poonam Aggrwal <poonam.aggrwal@freescale.com>

Issue:
The NOR-FCM does not support access to unaligned addresses for 16 bit port size

Impact:
When 16 bit port size is used, accesses not aligned to 16 bit address boundary
will result in incorrect data

Workaround:
The workaround is to switch to GPCM mode for NOR Flash access.

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
 arch/powerpc/cpu/mpc85xx/cmd_errata.c     |    3 +++
 arch/powerpc/include/asm/config_mpc85xx.h |    2 ++
 arch/powerpc/include/asm/fsl_ifc.h        |    5 +++++
 3 files changed, 10 insertions(+), 0 deletions(-)

diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
index 7b9f773..446f759 100644
--- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
+++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
@@ -87,6 +87,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	puts("Work-around for Erratum DDR111 enabled\n");
 	puts("Work-around for Erratum DDR134 enabled\n");
 #endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A002769
+	puts("Work-around for Erratum IFC-A002769 enabled\n");
+#endif
 	return 0;
 }
 
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index aa0f312..ccd8246 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -112,6 +112,7 @@
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v2.2"
 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
+#define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
 
 /* P1011 is single core version of P1020 */
 #elif defined(CONFIG_P1011)
@@ -160,6 +161,7 @@
 #define CONFIG_NUM_DDR_CONTROLLERS	1
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
+#define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
 
 /* P1015 is single core version of P1024 */
 #elif defined(CONFIG_P1015)
diff --git a/arch/powerpc/include/asm/fsl_ifc.h b/arch/powerpc/include/asm/fsl_ifc.h
index fb12363..7d95eb4 100644
--- a/arch/powerpc/include/asm/fsl_ifc.h
+++ b/arch/powerpc/include/asm/fsl_ifc.h
@@ -951,5 +951,10 @@ struct fsl_ifc {
 	struct fsl_ifc_gpcm ifc_gpcm;
 };
 
+#ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A002769
+#undef CSPR_MSEL_NOR
+#define CSPR_MSEL_NOR	CSPR_MSEL_GPCM
+#endif
+
 #endif /* __ASSEMBLY__ */
 #endif /* __ASM_PPC_FSL_IFC_H */
-- 
1.7.3.4

[U-Boot] [PATCH 3/4] powerpc/P1010: Add workaround for erratum P1010-A003549 (related to IFC)

[Kumar Gala]

From: Poonam Aggrwal <poonam.aggrwal@freescale.com>

Issue:
Peripheral connected to IFC_CS3 may hamper booting from IFC.

Impact:
Boot from IFC may not be successful if IFC_CS3 is used.

Workaround:
If IFC_CS3 is used, gate IFC_CS3 while booting from NAND or NOR.
Also Software should select IFC_CS3 using PMUXCR[26:27] = 0x01.

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
 arch/powerpc/cpu/mpc85xx/cmd_errata.c     |    3 +++
 arch/powerpc/cpu/mpc85xx/cpu_init_early.c |   12 ++++++++++++
 arch/powerpc/include/asm/config_mpc85xx.h |    2 ++
 3 files changed, 17 insertions(+), 0 deletions(-)

diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
index 446f759..c2fb5b8 100644
--- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
+++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
@@ -90,6 +90,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 #ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A002769
 	puts("Work-around for Erratum IFC-A002769 enabled\n");
 #endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_P1010_A003549
+	puts("Work-around for Erratum P1010-A003549 enabled\n");
+#endif
 	return 0;
 }
 
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
index 97e8424..05097b9 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
@@ -83,6 +83,9 @@ void cpu_init_early_f(void)
 {
 	u32 mas0, mas1, mas2, mas3, mas7;
 	int i;
+#ifdef CONFIG_SYS_FSL_ERRATUM_P1010_A003549
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+#endif
 
 	/* Pointer is writable since we allocated a register for it */
 	gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
@@ -115,6 +118,15 @@ void cpu_init_early_f(void)
 	setup_ccsrbar();
 #endif
 
+/*
+ * Work Around for IFC Erratum A-003549. This issue is P1010
+ * specific. LCLK(a free running clk signal) is muxed with IFC_CS3 on P1010 SOC
+ * Hence specifically selecting CS3.
+ */
+#ifdef CONFIG_SYS_FSL_ERRATUM_P1010_A003549
+	setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_LCLK_IFC_CS3);
+#endif
+
 	init_laws();
 	invalidate_tlb(1);
 	init_tlbs();
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index ccd8246..171ea12 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -113,6 +113,7 @@
 #define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v2.2"
 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
+#define CONFIG_SYS_FSL_ERRATUM_P1010_A003549
 
 /* P1011 is single core version of P1020 */
 #elif defined(CONFIG_P1011)
@@ -162,6 +163,7 @@
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
+#define CONFIG_SYS_FSL_ERRATUM_P1010_A003549
 
 /* P1015 is single core version of P1024 */
 #elif defined(CONFIG_P1015)
-- 
1.7.3.4

[U-Boot] [PATCH 4/4] fsl_ifc: Add the workaround for erratum IFC A-003399(enabled on P1010)

[Kumar Gala]

From: Poonam Aggrwal <poonam.aggrwal@freescale.com>

Issue: Address masking doesn't work properly.
When sum of the base address, defined by BA, and memory bank size,
defined by AM, exceeds 4GB (0xffff_ffff) then AMASKn[AM] doesn't mask
CSPRn[BA] bits.

Impact:
This will impact booting when we are reprogramming CSPR0(BA) and
AMASK0(AMASK) while executing from NOR Flash.

Workaround:
Re-programming of CSPR(BA) and AMASK is done while not executing from NOR
Flash. The code which programs the BA and AMASK is executed from L2-SRAM.

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
 arch/powerpc/cpu/mpc85xx/cmd_errata.c     |    3 +
 arch/powerpc/cpu/mpc85xx/cpu_init_early.c |   86 +++++++++++++++++++++++++++++
 arch/powerpc/cpu/mpc85xx/cpu_init_nand.c  |    2 +
 arch/powerpc/cpu/mpc8xxx/fsl_ifc.c        |    2 +
 arch/powerpc/include/asm/config_mpc85xx.h |    2 +
 5 files changed, 95 insertions(+), 0 deletions(-)

diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
index c2fb5b8..0478ec1 100644
--- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
+++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
@@ -93,6 +93,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 #ifdef CONFIG_SYS_FSL_ERRATUM_P1010_A003549
 	puts("Work-around for Erratum P1010-A003549 enabled\n");
 #endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A003399
+	puts("Work-around for Erratum IFC A-003399 enabled\n");
+#endif
 	return 0;
 }
 
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
index 05097b9..77c33bf 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
@@ -78,6 +78,42 @@ static void setup_ccsrbar(void)
 #endif
 #endif
 
+#if defined(CONFIG_SYS_FSL_ERRATUM_IFC_A003399) && !defined(CONFIG_SYS_RAMBOOT)
+void setup_ifc(void)
+{
+	struct fsl_ifc *ifc_regs = (void *)CONFIG_SYS_IFC_ADDR;
+	u32 _mas0, _mas1, _mas2, _mas3, _mas7;
+	phys_addr_t flash_phys = CONFIG_SYS_FLASH_BASE_PHYS;
+
+	/*
+	 * Adjust the TLB we were running out of to match the phys addr of the
+	 * chip select we are adjusting and will return to.
+	 */
+	flash_phys += (~CONFIG_SYS_AMASK0) + 1 - 4*1024*1024;
+
+	_mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(15);
+	_mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_IPROT | 
+			MAS1_TSIZE(BOOKE_PAGESZ_4M);
+	_mas2 = FSL_BOOKE_MAS2(CONFIG_SYS_TEXT_BASE, MAS2_I|MAS2_G);
+	_mas3 = FSL_BOOKE_MAS3(flash_phys, 0, MAS3_SW|MAS3_SR|MAS3_SX);
+	_mas7 = FSL_BOOKE_MAS7(flash_phys);
+
+	mtspr(MAS0, _mas0);
+	mtspr(MAS1, _mas1);
+	mtspr(MAS2, _mas2);
+	mtspr(MAS3, _mas3);
+	mtspr(MAS7, _mas7);
+
+	asm volatile("isync;msync;tlbwe;isync");
+
+	out_be32(&(ifc_regs->cspr_cs[0].cspr), CONFIG_SYS_CSPR0);
+	out_be32(&(ifc_regs->csor_cs[0].csor), CONFIG_SYS_CSOR0);
+	out_be32(&(ifc_regs->amask_cs[0].amask), CONFIG_SYS_AMASK0);
+
+	return ;
+}
+#endif
+
 /* We run cpu_init_early_f in AS = 1 */
 void cpu_init_early_f(void)
 {
@@ -86,6 +122,11 @@ void cpu_init_early_f(void)
 #ifdef CONFIG_SYS_FSL_ERRATUM_P1010_A003549
 	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 #endif
+#if defined(CONFIG_SYS_FSL_ERRATUM_IFC_A003399) && !defined(CONFIG_SYS_RAMBOOT)
+	ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
+	u32  *l2srbar, *dst, *src;
+	void (*setup_ifc_sram)(void);
+#endif
 
 	/* Pointer is writable since we allocated a register for it */
 	gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
@@ -128,6 +169,51 @@ void cpu_init_early_f(void)
 #endif
 
 	init_laws();
+
+/*
+ * Work Around for IFC Erratum A003399, issue will hit only when execution
+ * from NOR Flash
+ */
+#if defined(CONFIG_SYS_FSL_ERRATUM_IFC_A003399) && !defined(CONFIG_SYS_RAMBOOT)
+#define SRAM_BASE_ADDR	(0x00000000)
+	/* TLB for SRAM */
+	mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(9);
+	mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS |
+		MAS1_TSIZE(BOOKE_PAGESZ_1M);
+	mas2 = FSL_BOOKE_MAS2(SRAM_BASE_ADDR, MAS2_I);
+	mas3 = FSL_BOOKE_MAS3(SRAM_BASE_ADDR, 0, MAS3_SX|MAS3_SW|MAS3_SR);
+	mas7 = FSL_BOOKE_MAS7(0);
+
+	write_tlb(mas0, mas1, mas2, mas3, mas7);
+
+	out_be32(&l2cache->l2srbar0, SRAM_BASE_ADDR);
+
+	out_be32(&l2cache->l2errdis,
+		(MPC85xx_L2ERRDIS_MBECC | MPC85xx_L2ERRDIS_SBECC));
+
+	out_be32(&l2cache->l2ctl,
+		(MPC85xx_L2CTL_L2E | MPC85xx_L2CTL_L2SRAM_ENTIRE));
+
+	/*
+	 * Copy the code in setup_ifc to L2SRAM. Do a word copy
+	 * because NOR Flash on P1010 does not support byte
+	 * access (Erratum IFC-A002769)
+	 */
+	setup_ifc_sram = (void *)SRAM_BASE_ADDR;
+	dst = (u32 *) SRAM_BASE_ADDR;
+	src = (u32 *) setup_ifc;
+	for (i = 0; i < 1024; i++)
+		*l2srbar++ = *src++;
+
+	setup_ifc_sram();
+
+	/* CLEANUP */
+	clrbits_be32(&l2cache->l2ctl,
+			(MPC85xx_L2CTL_L2E |
+			 MPC85xx_L2CTL_L2SRAM_ENTIRE));
+	out_be32(&l2cache->l2srbar0, 0x0);
+#endif
+
 	invalidate_tlb(1);
 	init_tlbs();
 }
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c b/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c
index 6d01479..f33db02 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c
@@ -43,12 +43,14 @@ void cpu_init_f(void)
 #endif
 #endif
 #ifdef CONFIG_FSL_IFC
+#ifndef	CONFIG_SYS_FSL_ERRATUM_IFC_A003399
 #if defined(CONFIG_SYS_CSPR0) && defined(CONFIG_SYS_CSOR0)
 	set_ifc_cspr(IFC_CS0, CONFIG_SYS_CSPR0);
 	set_ifc_amask(IFC_CS0, CONFIG_SYS_AMASK0);
 	set_ifc_csor(IFC_CS0, CONFIG_SYS_CSOR0);
 #endif
 #endif
+#endif
 
 #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
 	ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
diff --git a/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c b/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c
index e794821..6682496 100644
--- a/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c
+++ b/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c
@@ -43,10 +43,12 @@ void init_early_memctl_regs(void)
 	set_ifc_ftim(IFC_CS0, IFC_FTIM2, CONFIG_SYS_CS0_FTIM2);
 	set_ifc_ftim(IFC_CS0, IFC_FTIM3, CONFIG_SYS_CS0_FTIM3);
 
+#if !defined(CONFIG_SYS_FSL_ERRATUM_IFC_A003399) || defined(CONFIG_SYS_RAMBOOT)
 	set_ifc_cspr(IFC_CS0, CONFIG_SYS_CSPR0);
 	set_ifc_amask(IFC_CS0, CONFIG_SYS_AMASK0);
 	set_ifc_csor(IFC_CS0, CONFIG_SYS_CSOR0);
 #endif
+#endif
 
 #if defined(CONFIG_SYS_CSPR1) && defined(CONFIG_SYS_CSOR1)
 	set_ifc_ftim(IFC_CS1, IFC_FTIM0, CONFIG_SYS_CS1_FTIM0);
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index 171ea12..eeb2b41 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -114,6 +114,7 @@
 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
 #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549
+#define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
 
 /* P1011 is single core version of P1020 */
 #elif defined(CONFIG_P1011)
@@ -164,6 +165,7 @@
 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
 #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549
+#define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
 
 /* P1015 is single core version of P1024 */
 #elif defined(CONFIG_P1015)
-- 
1.7.3.4

[U-Boot] [PATCH 4/4] fsl_ifc: Add the workaround for erratum IFC A-003399(enabled on P1010)

[Wolfgang Denk]

Dear Kumar Gala,

In message <1312180248-28528-4-git-send-email-galak@kernel.crashing.org> you wrote:
> From: Poonam Aggrwal <poonam.aggrwal@freescale.com>
> 
> Issue: Address masking doesn't work properly.
> When sum of the base address, defined by BA, and memory bank size,
> defined by AM, exceeds 4GB (0xffff_ffff) then AMASKn[AM] doesn't mask
> CSPRn[BA] bits.
> 
> Impact:
> This will impact booting when we are reprogramming CSPR0(BA) and
> AMASK0(AMASK) while executing from NOR Flash.
> 
> Workaround:
> Re-programming of CSPR(BA) and AMASK is done while not executing from NOR
> Flash. The code which programs the BA and AMASK is executed from L2-SRAM.
> 
> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

Checkpatch says:

ERROR: trailing whitespace
#148: FILE: arch/powerpc/cpu/mpc85xx/cpu_init_early.c:95:
+^I_mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_IPROT | $

Please cleanup.



Kumar,  could you __please__ get used to running your patches throuch
checkpatch __before__ submitting?  Thanks.


Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
The use of COBOL cripples the mind; its teaching  should,  therefore,
be regarded as a criminal offense.                   - E. W. Dijkstra

[U-Boot] [PATCH 4/4] fsl_ifc: Add the workaround for erratum IFC A-003399(enabled on P1010)

[Kumar Gala]

On Aug 1, 2011, at 5:21 AM, Wolfgang Denk wrote:

> Dear Kumar Gala,
> 
> In message <1312180248-28528-4-git-send-email-galak@kernel.crashing.org> you wrote:
>> From: Poonam Aggrwal <poonam.aggrwal@freescale.com>
>> 
>> Issue: Address masking doesn't work properly.
>> When sum of the base address, defined by BA, and memory bank size,
>> defined by AM, exceeds 4GB (0xffff_ffff) then AMASKn[AM] doesn't mask
>> CSPRn[BA] bits.
>> 
>> Impact:
>> This will impact booting when we are reprogramming CSPR0(BA) and
>> AMASK0(AMASK) while executing from NOR Flash.
>> 
>> Workaround:
>> Re-programming of CSPR(BA) and AMASK is done while not executing from NOR
>> Flash. The code which programs the BA and AMASK is executed from L2-SRAM.
>> 
>> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
>> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
> 
> Checkpatch says:
> 
> ERROR: trailing whitespace
> #148: FILE: arch/powerpc/cpu/mpc85xx/cpu_init_early.c:95:
> +^I_mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_IPROT | $
> 
> Please cleanup.
> 
> 
> 
> Kumar,  could you __please__ get used to running your patches throuch
> checkpatch __before__ submitting?  Thanks.

I try to, but not all of them are by me ;)

Will be nice when have a version of checkpatch in u-boot source tree.

- k

[U-Boot] [PATCH v2 4/4] fsl_ifc: Add the workaround for erratum IFC A-003399(enabled on P1010)

[Kumar Gala]

From: Poonam Aggrwal <poonam.aggrwal@freescale.com>

Issue: Address masking doesn't work properly.
When sum of the base address, defined by BA, and memory bank size,
defined by AM, exceeds 4GB (0xffff_ffff) then AMASKn[AM] doesn't mask
CSPRn[BA] bits.

Impact:
This will impact booting when we are reprogramming CSPR0(BA) and
AMASK0(AMASK) while executing from NOR Flash.

Workaround:
Re-programming of CSPR(BA) and AMASK is done while not executing from NOR
Flash. The code which programs the BA and AMASK is executed from L2-SRAM.

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
* Fix whitespace issue

 arch/powerpc/cpu/mpc85xx/cmd_errata.c     |    3 +
 arch/powerpc/cpu/mpc85xx/cpu_init_early.c |   86 +++++++++++++++++++++++++++++
 arch/powerpc/cpu/mpc85xx/cpu_init_nand.c  |    2 +
 arch/powerpc/cpu/mpc8xxx/fsl_ifc.c        |    2 +
 arch/powerpc/include/asm/config_mpc85xx.h |    2 +
 5 files changed, 95 insertions(+), 0 deletions(-)

diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
index c2fb5b8..0478ec1 100644
--- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
+++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
@@ -93,6 +93,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 #ifdef CONFIG_SYS_FSL_ERRATUM_P1010_A003549
 	puts("Work-around for Erratum P1010-A003549 enabled\n");
 #endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A003399
+	puts("Work-around for Erratum IFC A-003399 enabled\n");
+#endif
 	return 0;
 }

diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
index 05097b9..724c3cf 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
@@ -78,6 +78,42 @@ static void setup_ccsrbar(void)
 #endif
 #endif

+#if defined(CONFIG_SYS_FSL_ERRATUM_IFC_A003399) && !defined(CONFIG_SYS_RAMBOOT)
+void setup_ifc(void)
+{
+	struct fsl_ifc *ifc_regs = (void *)CONFIG_SYS_IFC_ADDR;
+	u32 _mas0, _mas1, _mas2, _mas3, _mas7;
+	phys_addr_t flash_phys = CONFIG_SYS_FLASH_BASE_PHYS;
+
+	/*
+	 * Adjust the TLB we were running out of to match the phys addr of the
+	 * chip select we are adjusting and will return to.
+	 */
+	flash_phys += (~CONFIG_SYS_AMASK0) + 1 - 4*1024*1024;
+
+	_mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(15);
+	_mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_IPROT |
+			MAS1_TSIZE(BOOKE_PAGESZ_4M);
+	_mas2 = FSL_BOOKE_MAS2(CONFIG_SYS_TEXT_BASE, MAS2_I|MAS2_G);
+	_mas3 = FSL_BOOKE_MAS3(flash_phys, 0, MAS3_SW|MAS3_SR|MAS3_SX);
+	_mas7 = FSL_BOOKE_MAS7(flash_phys);
+
+	mtspr(MAS0, _mas0);
+	mtspr(MAS1, _mas1);
+	mtspr(MAS2, _mas2);
+	mtspr(MAS3, _mas3);
+	mtspr(MAS7, _mas7);
+
+	asm volatile("isync;msync;tlbwe;isync");
+
+	out_be32(&(ifc_regs->cspr_cs[0].cspr), CONFIG_SYS_CSPR0);
+	out_be32(&(ifc_regs->csor_cs[0].csor), CONFIG_SYS_CSOR0);
+	out_be32(&(ifc_regs->amask_cs[0].amask), CONFIG_SYS_AMASK0);
+
+	return ;
+}
+#endif
+
 /* We run cpu_init_early_f in AS = 1 */
 void cpu_init_early_f(void)
 {
@@ -86,6 +122,11 @@ void cpu_init_early_f(void)
 #ifdef CONFIG_SYS_FSL_ERRATUM_P1010_A003549
 	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 #endif
+#if defined(CONFIG_SYS_FSL_ERRATUM_IFC_A003399) && !defined(CONFIG_SYS_RAMBOOT)
+	ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
+	u32  *l2srbar, *dst, *src;
+	void (*setup_ifc_sram)(void);
+#endif

 	/* Pointer is writable since we allocated a register for it */
 	gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
@@ -128,6 +169,51 @@ void cpu_init_early_f(void)
 #endif

 	init_laws();
+
+/*
+ * Work Around for IFC Erratum A003399, issue will hit only when execution
+ * from NOR Flash
+ */
+#if defined(CONFIG_SYS_FSL_ERRATUM_IFC_A003399) && !defined(CONFIG_SYS_RAMBOOT)
+#define SRAM_BASE_ADDR	(0x00000000)
+	/* TLB for SRAM */
+	mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(9);
+	mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS |
+		MAS1_TSIZE(BOOKE_PAGESZ_1M);
+	mas2 = FSL_BOOKE_MAS2(SRAM_BASE_ADDR, MAS2_I);
+	mas3 = FSL_BOOKE_MAS3(SRAM_BASE_ADDR, 0, MAS3_SX|MAS3_SW|MAS3_SR);
+	mas7 = FSL_BOOKE_MAS7(0);
+
+	write_tlb(mas0, mas1, mas2, mas3, mas7);
+
+	out_be32(&l2cache->l2srbar0, SRAM_BASE_ADDR);
+
+	out_be32(&l2cache->l2errdis,
+		(MPC85xx_L2ERRDIS_MBECC | MPC85xx_L2ERRDIS_SBECC));
+
+	out_be32(&l2cache->l2ctl,
+		(MPC85xx_L2CTL_L2E | MPC85xx_L2CTL_L2SRAM_ENTIRE));
+
+	/*
+	 * Copy the code in setup_ifc to L2SRAM. Do a word copy
+	 * because NOR Flash on P1010 does not support byte
+	 * access (Erratum IFC-A002769)
+	 */
+	setup_ifc_sram = (void *)SRAM_BASE_ADDR;
+	dst = (u32 *) SRAM_BASE_ADDR;
+	src = (u32 *) setup_ifc;
+	for (i = 0; i < 1024; i++)
+		*l2srbar++ = *src++;
+
+	setup_ifc_sram();
+
+	/* CLEANUP */
+	clrbits_be32(&l2cache->l2ctl,
+			(MPC85xx_L2CTL_L2E |
+			 MPC85xx_L2CTL_L2SRAM_ENTIRE));
+	out_be32(&l2cache->l2srbar0, 0x0);
+#endif
+
 	invalidate_tlb(1);
 	init_tlbs();
 }
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c b/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c
index 6d01479..f33db02 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c
@@ -43,12 +43,14 @@ void cpu_init_f(void)
 #endif
 #endif
 #ifdef CONFIG_FSL_IFC
+#ifndef	CONFIG_SYS_FSL_ERRATUM_IFC_A003399
 #if defined(CONFIG_SYS_CSPR0) && defined(CONFIG_SYS_CSOR0)
 	set_ifc_cspr(IFC_CS0, CONFIG_SYS_CSPR0);
 	set_ifc_amask(IFC_CS0, CONFIG_SYS_AMASK0);
 	set_ifc_csor(IFC_CS0, CONFIG_SYS_CSOR0);
 #endif
 #endif
+#endif

 #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
 	ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
diff --git a/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c b/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c
index e794821..6682496 100644
--- a/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c
+++ b/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c
@@ -43,10 +43,12 @@ void init_early_memctl_regs(void)
 	set_ifc_ftim(IFC_CS0, IFC_FTIM2, CONFIG_SYS_CS0_FTIM2);
 	set_ifc_ftim(IFC_CS0, IFC_FTIM3, CONFIG_SYS_CS0_FTIM3);

+#if !defined(CONFIG_SYS_FSL_ERRATUM_IFC_A003399) || defined(CONFIG_SYS_RAMBOOT)
 	set_ifc_cspr(IFC_CS0, CONFIG_SYS_CSPR0);
 	set_ifc_amask(IFC_CS0, CONFIG_SYS_AMASK0);
 	set_ifc_csor(IFC_CS0, CONFIG_SYS_CSOR0);
 #endif
+#endif

 #if defined(CONFIG_SYS_CSPR1) && defined(CONFIG_SYS_CSOR1)
 	set_ifc_ftim(IFC_CS1, IFC_FTIM0, CONFIG_SYS_CS1_FTIM0);
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index 171ea12..eeb2b41 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -114,6 +114,7 @@
 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
 #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549
+#define CONFIG_SYS_FSL_ERRATUM_IFC_A003399

 /* P1011 is single core version of P1020 */
 #elif defined(CONFIG_P1011)
@@ -164,6 +165,7 @@
 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
 #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549
+#define CONFIG_SYS_FSL_ERRATUM_IFC_A003399

 /* P1015 is single core version of P1024 */
 #elif defined(CONFIG_P1015)
-- 
1.7.3.4

[U-Boot] [PATCH 4/4] fsl_ifc: Add the workaround for erratum IFC A-003399(enabled on P1010)

[Wolfgang Denk]

Dear Kumar Gala,

In message <08144324-BE32-4A54-BC2D-B920F18F3D43@kernel.crashing.org> you wrote:
> 
> > Kumar,  could you __please__ get used to running your patches throuch
> > checkpatch __before__ submitting?  Thanks.
> 
> I try to, but not all of them are by me ;)

I know.  But you submitted them, so you are responsible.

> Will be nice when have a version of checkpatch in u-boot source tree.

Indeed.  Submit a patch?

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
"Success covers a multitude of blunders."       - George Bernard Shaw