* [U-Boot] Update at91sam9m10g45 SoC and AT91SAM9M10G45-EK board to new style @ 2011-08-04 10:10 Thomas Petazzoni 2011-08-04 10:10 ` [U-Boot] [PATCH 1/2] atmel: update at91sam9m10g45 SoC support " Thomas Petazzoni 2011-08-04 10:10 ` [U-Boot] [PATCH 2/2] atmel: Update support of board AT91SAM9M10G45-EK " Thomas Petazzoni 0 siblings, 2 replies; 8+ messages in thread From: Thomas Petazzoni @ 2011-08-04 10:10 UTC (permalink / raw) To: u-boot Hello, These two patches update the support of the AT91SAM9M10G45 SoC and the corresponding AT91SAM9M10G45-EK evaluation platform to the next AT91 organization. For the moment, only the nandflash configuration is supported, the dataflash configuration will come later on. Note however that the AT91 Ethernet driver doesn't work in the current master, due to the D-cache being enabled by c2dd0d45540397704de9b13287417d21049d34c6. Waiting for a proper solution to this problem, I am currently doing the testing with the following workaround: diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c index 90709d0..761e233 100644 --- a/arch/arm/lib/board.c +++ b/arch/arm/lib/board.c @@ -450,7 +450,9 @@ void board_init_r (gd_t *id, ulong dest_addr) * Enable D$: * I$, if needed, must be already enabled in start.S */ +#if 0 dcache_enable(); +#endif debug ("monitor flash len: %08lX\n", monitor_flash_len); board_init(); /* Setup chipselects */ Best regards, Thomas Petazzoni -- Thomas Petazzoni, Free Electrons Kernel, drivers, real-time and embedded Linux development, consulting, training and support. http://free-electrons.com ^ permalink raw reply related [flat|nested] 8+ messages in thread
* [U-Boot] [PATCH 1/2] atmel: update at91sam9m10g45 SoC support to new style 2011-08-04 10:10 [U-Boot] Update at91sam9m10g45 SoC and AT91SAM9M10G45-EK board to new style Thomas Petazzoni @ 2011-08-04 10:10 ` Thomas Petazzoni 2011-08-04 13:59 ` Reinhard Meyer 2011-08-04 10:10 ` [U-Boot] [PATCH 2/2] atmel: Update support of board AT91SAM9M10G45-EK " Thomas Petazzoni 1 sibling, 1 reply; 8+ messages in thread From: Thomas Petazzoni @ 2011-08-04 10:10 UTC (permalink / raw) To: u-boot Based on earlier work by Alex Waterman <awaterman@dawning.com>. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> --- .../cpu/arm926ejs/at91/at91sam9m10g45_devices.c | 28 ++-- arch/arm/include/asm/arch-at91/at91sam9g45.h | 12 ++ .../arm/include/asm/arch-at91/at91sam9g45_matrix.h | 194 +++++++------------- 3 files changed, 94 insertions(+), 140 deletions(-) diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9m10g45_devices.c b/arch/arm/cpu/arm926ejs/at91/at91sam9m10g45_devices.c index 4ad9b1f..c75d4d8 100644 --- a/arch/arm/cpu/arm926ejs/at91/at91sam9m10g45_devices.c +++ b/arch/arm/cpu/arm926ejs/at91/at91sam9m10g45_devices.c @@ -26,42 +26,42 @@ #include <asm/arch/at91_common.h> #include <asm/arch/at91_pmc.h> #include <asm/arch/gpio.h> -#include <asm/arch/io.h> +#include <asm/io.h> void at91_serial0_hw_init(void) { - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; at91_set_a_periph(AT91_PIO_PORTB, 19, 1); /* TXD0 */ at91_set_a_periph(AT91_PIO_PORTB, 18, 0); /* RXD0 */ - writel(1 << AT91SAM9G45_ID_US0, &pmc->pcer); + writel(1 << ATMEL_ID_USART0, &pmc->pcer); } void at91_serial1_hw_init(void) { - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; at91_set_a_periph(AT91_PIO_PORTB, 4, 1); /* TXD1 */ at91_set_a_periph(AT91_PIO_PORTB, 5, 0); /* RXD1 */ - writel(1 << AT91SAM9G45_ID_US1, &pmc->pcer); + writel(1 << ATMEL_ID_USART1, &pmc->pcer); } void at91_serial2_hw_init(void) { - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; at91_set_a_periph(AT91_PIO_PORTD, 6, 1); /* TXD2 */ at91_set_a_periph(AT91_PIO_PORTD, 7, 0); /* RXD2 */ - writel(1 << AT91SAM9G45_ID_US2, &pmc->pcer); + writel(1 << ATMEL_ID_USART2, &pmc->pcer); } void at91_serial3_hw_init(void) { - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; at91_set_a_periph(AT91_PIO_PORTB, 12, 0); /* DRXD */ at91_set_a_periph(AT91_PIO_PORTB, 13, 1); /* DTXD */ - writel(1 << AT91_ID_SYS, &pmc->pcer); + writel(1 << ATMEL_ID_USART3, &pmc->pcer); } void at91_serial_hw_init(void) @@ -83,17 +83,17 @@ void at91_serial_hw_init(void) #endif } -#ifdef CONFIG_ATMEL_SPI +#if defined(CONFIG_HAS_DATAFLASH) || defined(CONFIG_ATMEL_SPI) void at91_spi0_hw_init(unsigned long cs_mask) { - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; at91_set_a_periph(AT91_PIO_PORTB, 0, 0); /* SPI0_MISO */ at91_set_a_periph(AT91_PIO_PORTB, 1, 0); /* SPI0_MOSI */ at91_set_a_periph(AT91_PIO_PORTB, 2, 0); /* SPI0_SPCK */ /* Enable clock */ - writel(1 << AT91SAM9G45_ID_SPI0, &pmc->pcer); + writel(1 << ATMEL_ID_SPI0, &pmc->pcer); if (cs_mask & (1 << 0)) { at91_set_a_periph(AT91_PIO_PORTB, 3, 0); @@ -123,14 +123,14 @@ void at91_spi0_hw_init(unsigned long cs_mask) void at91_spi1_hw_init(unsigned long cs_mask) { - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; at91_set_a_periph(AT91_PIO_PORTB, 14, 0); /* SPI1_MISO */ at91_set_a_periph(AT91_PIO_PORTB, 15, 0); /* SPI1_MOSI */ at91_set_a_periph(AT91_PIO_PORTB, 16, 0); /* SPI1_SPCK */ /* Enable clock */ - writel(1 << AT91SAM9G45_ID_SPI1, &pmc->pcer); + writel(1 << ATMEL_ID_SPI1, &pmc->pcer); if (cs_mask & (1 << 0)) { at91_set_a_periph(AT91_PIO_PORTB, 17, 0); diff --git a/arch/arm/include/asm/arch-at91/at91sam9g45.h b/arch/arm/include/asm/arch-at91/at91sam9g45.h index 364b86c..4df6b09 100644 --- a/arch/arm/include/asm/arch-at91/at91sam9g45.h +++ b/arch/arm/include/asm/arch-at91/at91sam9g45.h @@ -129,6 +129,18 @@ #define ATMEL_BASE_VDEC 0x00900000 /* Video Decoder Controller */ /* + * External memory + */ +#define ATMEL_BASE_CS0 0x10000000 +#define ATMEL_BASE_CS1 0x20000000 +#define ATMEL_BASE_CS2 0x30000000 +#define ATMEL_BASE_CS3 0x40000000 +#define ATMEL_BASE_CS4 0x50000000 +#define ATMEL_BASE_CS5 0x60000000 +#define ATMEL_BASE_CS6 0x70000000 +#define ATMEL_BASE_CS7 0x80000000 + +/* * Other misc defines */ #define ATMEL_PIO_PORTS 5 /* this SoCs has 5 PIO */ diff --git a/arch/arm/include/asm/arch-at91/at91sam9g45_matrix.h b/arch/arm/include/asm/arch-at91/at91sam9g45_matrix.h index 1620e1b..bace7e4 100644 --- a/arch/arm/include/asm/arch-at91/at91sam9g45_matrix.h +++ b/arch/arm/include/asm/arch-at91/at91sam9g45_matrix.h @@ -15,139 +15,81 @@ #ifndef AT91SAM9G45_MATRIX_H #define AT91SAM9G45_MATRIX_H -#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */ -#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */ -#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */ -#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */ -#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */ -#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */ -#define AT91_MATRIX_MCFG6 (AT91_MATRIX + 0x18) /* Master Configuration Register 6 */ -#define AT91_MATRIX_MCFG7 (AT91_MATRIX + 0x1C) /* Master Configuration Register 7 */ -#define AT91_MATRIX_MCFG8 (AT91_MATRIX + 0x20) /* Master Configuration Register 8 */ -#define AT91_MATRIX_MCFG9 (AT91_MATRIX + 0x24) /* Master Configuration Register 9 */ -#define AT91_MATRIX_MCFG10 (AT91_MATRIX + 0x28) /* Master Configuration Register 10 */ -#define AT91_MATRIX_MCFG11 (AT91_MATRIX + 0x2C) /* Master Configuration Register 11 */ -#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */ -#define AT91_MATRIX_ULBT_INFINITE (0 << 0) -#define AT91_MATRIX_ULBT_SINGLE (1 << 0) -#define AT91_MATRIX_ULBT_FOUR (2 << 0) -#define AT91_MATRIX_ULBT_EIGHT (3 << 0) -#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0) -#define AT91_MATRIX_ULBT_THIRTYTWO (5 << 0) -#define AT91_MATRIX_ULBT_SIXTYFOUR (6 << 0) -#define AT91_MATRIX_ULBT_128 (7 << 0) +#ifndef __ASSEMBLY__ -#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */ -#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */ -#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */ -#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */ -#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */ -#define AT91_MATRIX_SCFG5 (AT91_MATRIX + 0x54) /* Slave Configuration Register 5 */ -#define AT91_MATRIX_SCFG6 (AT91_MATRIX + 0x58) /* Slave Configuration Register 6 */ -#define AT91_MATRIX_SCFG7 (AT91_MATRIX + 0x5C) /* Slave Configuration Register 7 */ -#define AT91_MATRIX_SLOT_CYCLE (0x1ff << 0) /* Maximum Number of Allowed Cycles for a Burst */ -#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */ -#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) -#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) -#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) -#define AT91_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */ +struct at91_matrix { + u32 mcfg[16]; + u32 scfg[16]; + u32 pras[16][2]; + u32 mrcr; /* 0x100 Master Remap Control */ + u32 filler[3]; + u32 tcmr; + u32 filler2; + u32 ddrmpr; + u32 filler3[3]; + u32 ebicsa; + u32 filler4[47]; + u32 wpmr; + u32 wpsr; +}; -#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */ -#define AT91_MATRIX_PRBS0 (AT91_MATRIX + 0x84) /* Priority Register B for Slave 0 */ -#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */ -#define AT91_MATRIX_PRBS1 (AT91_MATRIX + 0x8C) /* Priority Register B for Slave 1 */ -#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */ -#define AT91_MATRIX_PRBS2 (AT91_MATRIX + 0x94) /* Priority Register B for Slave 2 */ -#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */ -#define AT91_MATRIX_PRBS3 (AT91_MATRIX + 0x9C) /* Priority Register B for Slave 3 */ -#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */ -#define AT91_MATRIX_PRBS4 (AT91_MATRIX + 0xA4) /* Priority Register B for Slave 4 */ -#define AT91_MATRIX_PRAS5 (AT91_MATRIX + 0xA8) /* Priority Register A for Slave 5 */ -#define AT91_MATRIX_PRBS5 (AT91_MATRIX + 0xAC) /* Priority Register B for Slave 5 */ -#define AT91_MATRIX_PRAS6 (AT91_MATRIX + 0xB0) /* Priority Register A for Slave 6 */ -#define AT91_MATRIX_PRBS6 (AT91_MATRIX + 0xB4) /* Priority Register B for Slave 6 */ -#define AT91_MATRIX_PRAS7 (AT91_MATRIX + 0xB8) /* Priority Register A for Slave 7 */ -#define AT91_MATRIX_PRBS7 (AT91_MATRIX + 0xBC) /* Priority Register B for Slave 7 */ -#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */ -#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */ -#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */ -#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */ -#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */ -#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */ -#define AT91_MATRIX_M6PR (3 << 24) /* Master 6 Priority */ -#define AT91_MATRIX_M7PR (3 << 28) /* Master 7 Priority */ -#define AT91_MATRIX_M8PR (3 << 0) /* Master 8 Priority (in Register B) */ -#define AT91_MATRIX_M9PR (3 << 4) /* Master 9 Priority (in Register B) */ -#define AT91_MATRIX_M10PR (3 << 8) /* Master 10 Priority (in Register B) */ -#define AT91_MATRIX_M11PR (3 << 12) /* Master 11 Priority (in Register B) */ +#endif /* __ASSEMBLY__ */ -#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */ -#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ -#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ -#define AT91_MATRIX_RCB2 (1 << 2) -#define AT91_MATRIX_RCB3 (1 << 3) -#define AT91_MATRIX_RCB4 (1 << 4) -#define AT91_MATRIX_RCB5 (1 << 5) -#define AT91_MATRIX_RCB6 (1 << 6) -#define AT91_MATRIX_RCB7 (1 << 7) -#define AT91_MATRIX_RCB8 (1 << 8) -#define AT91_MATRIX_RCB9 (1 << 9) -#define AT91_MATRIX_RCB10 (1 << 10) -#define AT91_MATRIX_RCB11 (1 << 11) +#define AT91_MATRIX_ULBT_INFINITE (0 << 0) +#define AT91_MATRIX_ULBT_SINGLE (1 << 0) +#define AT91_MATRIX_ULBT_FOUR (2 << 0) +#define AT91_MATRIX_ULBT_EIGHT (3 << 0) +#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0) +#define AT91_MATRIX_ULBT_THIRTYTWO (5 << 0) +#define AT91_MATRIX_ULBT_SIXTYFOUR (6 << 0) +#define AT91_MATRIX_ULBT_128 (7 << 0) -#define AT91_MATRIX_TCMR (AT91_MATRIX + 0x110) /* TCM Configuration Register */ -#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */ -#define AT91_MATRIX_ITCM_0 (0 << 0) -#define AT91_MATRIX_ITCM_32 (6 << 0) -#define AT91_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */ -#define AT91_MATRIX_DTCM_0 (0 << 4) -#define AT91_MATRIX_DTCM_32 (6 << 4) -#define AT91_MATRIX_DTCM_64 (7 << 4) -#define AT91_MATRIX_TCM_NWS (0x1 << 11) /* Wait state TCM register */ -#define AT91_MATRIX_TCM_NO_WS (0x0 << 11) -#define AT91_MATRIX_TCM_ONE_WS (0x1 << 11) +#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) +#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) +#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) +#define AT91_MATRIX_FIXED_DEFMSTR_SHIFT 18 -#define AT91_MATRIX_VIDEO (AT91_MATRIX + 0x118) /* Video Mode Configuration Register */ -#define AT91C_VDEC_SEL (0x1 << 0) /* Video Mode Selection */ -#define AT91C_VDEC_SEL_OFF (0 << 0) -#define AT91C_VDEC_SEL_ON (1 << 0) +#define AT91_MATRIX_M0PR_SHIFT 0 +#define AT91_MATRIX_M1PR_SHIFT 4 +#define AT91_MATRIX_M2PR_SHIFT 8 +#define AT91_MATRIX_M3PR_SHIFT 12 +#define AT91_MATRIX_M4PR_SHIFT 16 +#define AT91_MATRIX_M5PR_SHIFT 20 +#define AT91_MATRIX_M6PR_SHIFT 24 +#define AT91_MATRIX_M7PR_SHIFT 28 -#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x128) /* EBI Chip Select Assignment Register */ -#define AT91_MATRIX_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */ -#define AT91_MATRIX_EBI_CS1A_SMC (0 << 1) -#define AT91_MATRIX_EBI_CS1A_SDRAMC (1 << 1) -#define AT91_MATRIX_EBI_CS3A (1 << 3) /* Chip Select 3 Assignment */ -#define AT91_MATRIX_EBI_CS3A_SMC (0 << 3) -#define AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA (1 << 3) -#define AT91_MATRIX_EBI_CS4A (1 << 4) /* Chip Select 4 Assignment */ -#define AT91_MATRIX_EBI_CS4A_SMC (0 << 4) -#define AT91_MATRIX_EBI_CS4A_SMC_CF0 (1 << 4) -#define AT91_MATRIX_EBI_CS5A (1 << 5) /* Chip Select 5 Assignment */ -#define AT91_MATRIX_EBI_CS5A_SMC (0 << 5) -#define AT91_MATRIX_EBI_CS5A_SMC_CF1 (1 << 5) -#define AT91_MATRIX_EBI_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ -#define AT91_MATRIX_EBI_DBPU_ON (0 << 8) -#define AT91_MATRIX_EBI_DBPU_OFF (1 << 8) -#define AT91_MATRIX_EBI_VDDIOMSEL (1 << 16) /* Memory voltage selection */ -#define AT91_MATRIX_EBI_VDDIOMSEL_1_8V (0 << 16) -#define AT91_MATRIX_EBI_VDDIOMSEL_3_3V (1 << 16) -#define AT91_MATRIX_EBI_EBI_IOSR (1 << 17) /* EBI I/O slew rate selection */ -#define AT91_MATRIX_EBI_EBI_IOSR_REDUCED (0 << 17) -#define AT91_MATRIX_EBI_EBI_IOSR_NORMAL (1 << 17) -#define AT91_MATRIX_EBI_DDR_IOSR (1 << 18) /* DDR2 dedicated port I/O slew rate selection */ -#define AT91_MATRIX_EBI_DDR_IOSR_REDUCED (0 << 18) -#define AT91_MATRIX_EBI_DDR_IOSR_NORMAL (1 << 18) +#define AT91_MATRIX_M8PR_SHIFT 0 /* register B */ +#define AT91_MATRIX_M9PR_SHIFT 4 /* register B */ +#define AT91_MATRIX_M10PR_SHIFT 8 /* register B */ +#define AT91_MATRIX_M11PR_SHIFT 12 /* register B */ -#define AT91_MATRIX_WPMR (AT91_MATRIX + 0x1E4) /* Write Protect Mode Register */ -#define AT91_MATRIX_WPMR_WPEN (1 << 0) /* Write Protect ENable */ -#define AT91_MATRIX_WPMR_WP_WPDIS (0 << 0) -#define AT91_MATRIX_WPMR_WP_WPEN (1 << 0) -#define AT91_MATRIX_WPMR_WPKEY (0xFFFFFF << 8) /* Write Protect KEY */ +#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ +#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ +#define AT91_MATRIX_RCB2 (1 << 2) +#define AT91_MATRIX_RCB3 (1 << 3) +#define AT91_MATRIX_RCB4 (1 << 4) +#define AT91_MATRIX_RCB5 (1 << 5) +#define AT91_MATRIX_RCB6 (1 << 6) +#define AT91_MATRIX_RCB7 (1 << 7) +#define AT91_MATRIX_RCB8 (1 << 8) +#define AT91_MATRIX_RCB9 (1 << 9) +#define AT91_MATRIX_RCB10 (1 << 10) -#define AT91_MATRIX_WPSR (AT91_MATRIX + 0x1E8) /* Write Protect Status Register */ -#define AT91_MATRIX_WPSR_WPVS (1 << 0) /* Write Protect Violation Status */ -#define AT91_MATRIX_WPSR_NO_WPV (0 << 0) -#define AT91_MATRIX_WPSR_WPV (1 << 0) -#define AT91_MATRIX_WPSR_WPVSRC (0xFFFF << 8) /* Write Protect Violation Source */ +#define AT91_MATRIX_EBI_CS1A_SMC (0 << 1) +#define AT91_MATRIX_EBI_CS1A_SDRAMC (1 << 1) +#define AT91_MATRIX_EBI_CS3A_SMC (0 << 3) +#define AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA (1 << 3) +#define AT91_MATRIX_EBI_CS4A_SMC (0 << 4) +#define AT91_MATRIX_EBI_CS4A_SMC_CF0 (1 << 4) +#define AT91_MATRIX_EBI_CS5A_SMC (0 << 5) +#define AT91_MATRIX_EBI_CS5A_SMC_CF1 (1 << 5) +#define AT91_MATRIX_EBI_DBPU_ON (0 << 8) +#define AT91_MATRIX_EBI_DBPU_OFF (1 << 8) +#define AT91_MATRIX_EBI_VDDIOMSEL_1_8V (0 << 16) +#define AT91_MATRIX_EBI_VDDIOMSEL_3_3V (1 << 16) +#define AT91_MATRIX_EBI_EBI_IOSR_REDUCED (0 << 17) +#define AT91_MATRIX_EBI_EBI_IOSR_NORMAL (1 << 17) +#define AT91_MATRIX_EBI_DDR_IOSR_REDUCED (0 << 18) +#define AT91_MATRIX_EBI_DDR_IOSR_NORMAL (1 << 18) #endif -- 1.7.4.1 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* [U-Boot] [PATCH 1/2] atmel: update at91sam9m10g45 SoC support to new style 2011-08-04 10:10 ` [U-Boot] [PATCH 1/2] atmel: update at91sam9m10g45 SoC support " Thomas Petazzoni @ 2011-08-04 13:59 ` Reinhard Meyer 2011-08-04 18:54 ` Thomas Petazzoni 0 siblings, 1 reply; 8+ messages in thread From: Reinhard Meyer @ 2011-08-04 13:59 UTC (permalink / raw) To: u-boot Dear Thomas Petazzoni, > Based on earlier work by Alex Waterman <awaterman@dawning.com>. > > Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> > --- > .../cpu/arm926ejs/at91/at91sam9m10g45_devices.c | 28 ++-- > arch/arm/include/asm/arch-at91/at91sam9g45.h | 12 ++ > .../arm/include/asm/arch-at91/at91sam9g45_matrix.h | 194 +++++++------------- > 3 files changed, 94 insertions(+), 140 deletions(-) This patch still has the same issues I complained about at http://patchwork.ozlabs.org/patch/102811/ please fix them. Also your *_matrix.h is space corrupted (indentation done by space not tab). Tabs must be used! Please, and again, refer to the templates done in the 926x SoCs. WARNING: please, no space for starting a line, excluding comments #184: FILE: arch/arm/include/asm/arch-at91/at91sam9g45_matrix.h:21: + u32 mcfg[16];$ WARNING: please, no space for starting a line, excluding comments #185: FILE: arch/arm/include/asm/arch-at91/at91sam9g45_matrix.h:22: + u32 scfg[16];$ WARNING: please, no space for starting a line, excluding comments #186: FILE: arch/arm/include/asm/arch-at91/at91sam9g45_matrix.h:23: + u32 pras[16][2];$ WARNING: please, no space for starting a line, excluding comments #187: FILE: arch/arm/include/asm/arch-at91/at91sam9g45_matrix.h:24: + u32 mrcr; /* 0x100 Master Remap Control */$ WARNING: please, no space for starting a line, excluding comments #188: FILE: arch/arm/include/asm/arch-at91/at91sam9g45_matrix.h:25: + u32 filler[3];$ WARNING: please, no space for starting a line, excluding comments #189: FILE: arch/arm/include/asm/arch-at91/at91sam9g45_matrix.h:26: + u32 tcmr;$ WARNING: please, no space for starting a line, excluding comments #190: FILE: arch/arm/include/asm/arch-at91/at91sam9g45_matrix.h:27: + u32 filler2;$ WARNING: please, no space for starting a line, excluding comments #191: FILE: arch/arm/include/asm/arch-at91/at91sam9g45_matrix.h:28: + u32 ddrmpr;$ WARNING: please, no space for starting a line, excluding comments #192: FILE: arch/arm/include/asm/arch-at91/at91sam9g45_matrix.h:29: + u32 filler3[3];$ WARNING: please, no space for starting a line, excluding comments #193: FILE: arch/arm/include/asm/arch-at91/at91sam9g45_matrix.h:30: + u32 ebicsa;$ WARNING: please, no space for starting a line, excluding comments #194: FILE: arch/arm/include/asm/arch-at91/at91sam9g45_matrix.h:31: + u32 filler4[47];$ WARNING: please, no space for starting a line, excluding comments #195: FILE: arch/arm/include/asm/arch-at91/at91sam9g45_matrix.h:32: + u32 wpmr;$ WARNING: please, no space for starting a line, excluding comments #196: FILE: arch/arm/include/asm/arch-at91/at91sam9g45_matrix.h:33: + u32 wpsr;$ WARNING: line over 80 characters #315: FILE: arch/arm/include/asm/arch-at91/at91sam9g45_matrix.h:66: +#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ WARNING: line over 80 characters #316: FILE: arch/arm/include/asm/arch-at91/at91sam9g45_matrix.h:67: +#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ total: 0 errors, 15 warnings, 312 lines checked U-Boot-1-2-atmel-update-at91sam9m10g45-SoC-support-to-new-style.patch has style problems, please review. Best Regards, Reinhard ^ permalink raw reply [flat|nested] 8+ messages in thread
* [U-Boot] [PATCH 1/2] atmel: update at91sam9m10g45 SoC support to new style 2011-08-04 13:59 ` Reinhard Meyer @ 2011-08-04 18:54 ` Thomas Petazzoni 0 siblings, 0 replies; 8+ messages in thread From: Thomas Petazzoni @ 2011-08-04 18:54 UTC (permalink / raw) To: u-boot Hello Reinhard, Le Thu, 04 Aug 2011 13:59:18 +0000, Reinhard Meyer <u-boot@emk-elektronik.de> a ?crit : > This patch still has the same issues I complained about at > > http://patchwork.ozlabs.org/patch/102811/ Thanks a lot for the review. I have just posted an updated version, which I hope, fixes the various issues you mentioned. Best regards, Thomas -- Thomas Petazzoni, Free Electrons Kernel, drivers, real-time and embedded Linux development, consulting, training and support. http://free-electrons.com ^ permalink raw reply [flat|nested] 8+ messages in thread
* [U-Boot] [PATCH 2/2] atmel: Update support of board AT91SAM9M10G45-EK to new style 2011-08-04 10:10 [U-Boot] Update at91sam9m10g45 SoC and AT91SAM9M10G45-EK board to new style Thomas Petazzoni 2011-08-04 10:10 ` [U-Boot] [PATCH 1/2] atmel: update at91sam9m10g45 SoC support " Thomas Petazzoni @ 2011-08-04 10:10 ` Thomas Petazzoni 2011-08-04 14:09 ` Reinhard Meyer 1 sibling, 1 reply; 8+ messages in thread From: Thomas Petazzoni @ 2011-08-04 10:10 UTC (permalink / raw) To: u-boot Based on earlier work by Alex Waterman <awaterman@dawning.com>. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> --- Makefile | 21 --- board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c | 121 +++++++++------- board/atmel/at91sam9m10g45ek/led.c | 6 +- boards.cfg | 1 + include/configs/at91sam9m10g45ek.h | 187 +++++++++++------------ 5 files changed, 160 insertions(+), 176 deletions(-) diff --git a/Makefile b/Makefile index 156b21b..7ff3bda 100644 --- a/Makefile +++ b/Makefile @@ -802,27 +802,6 @@ M5485HFE_config : unconfig ## ARM926EJ-S Systems ######################################################################### -at91sam9m10g45ek_nandflash_config \ -at91sam9m10g45ek_dataflash_config \ -at91sam9m10g45ek_dataflash_cs0_config \ -at91sam9m10g45ek_config \ -at91sam9g45ekes_nandflash_config \ -at91sam9g45ekes_dataflash_config \ -at91sam9g45ekes_dataflash_cs0_config \ -at91sam9g45ekes_config : unconfig - @mkdir -p $(obj)include - @if [ "$(findstring 9m10,$@)" ] ; then \ - echo "#define CONFIG_AT91SAM9M10G45EK 1" >>$(obj)include/config.h ; \ - else \ - echo "#define CONFIG_AT91SAM9G45EKES 1" >>$(obj)include/config.h ; \ - fi; - @if [ "$(findstring _nandflash,$@)" ] ; then \ - echo "#define CONFIG_SYS_USE_NANDFLASH 1" >>$(obj)include/config.h ; \ - else \ - echo "#define CONFIG_ATMEL_SPI 1" >>$(obj)include/config.h ; \ - fi; - @$(MKCONFIG) -n $@ -a at91sam9m10g45ek arm arm926ejs at91sam9m10g45ek atmel at91 - pm9g45_config : unconfig @mkdir -p $(obj)include @$(MKCONFIG) -a pm9g45 arm arm926ejs pm9g45 ronetix at91 diff --git a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c index f92b20f..40ee345 100644 --- a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c +++ b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c @@ -23,17 +23,14 @@ */ #include <common.h> -#include <asm/sizes.h> -#include <asm/arch/at91sam9g45.h> -#include <asm/arch/at91sam9_matrix.h> +#include <asm/io.h> +#include <asm/arch/at91sam9g45_matrix.h> #include <asm/arch/at91sam9_smc.h> #include <asm/arch/at91_common.h> #include <asm/arch/at91_pmc.h> #include <asm/arch/at91_rstc.h> -#include <asm/arch/clk.h> #include <asm/arch/gpio.h> -#include <asm/arch/io.h> -#include <asm/arch/hardware.h> +#include <asm/arch/clk.h> #include <lcd.h> #include <atmel_lcdc.h> #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB) @@ -49,35 +46,38 @@ DECLARE_GLOBAL_DATA_PTR; */ #ifdef CONFIG_CMD_NAND -static void at91sam9m10g45ek_nand_hw_init(void) +void at91sam9m10g45ek_nand_hw_init(void) { + struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; + struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; unsigned long csa; /* Enable CS3 */ - csa = at91_sys_read(AT91_MATRIX_EBICSA); - at91_sys_write(AT91_MATRIX_EBICSA, - csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA); + csa = readl(&matrix->ebicsa); + csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA; + writel(csa, &matrix->ebicsa); /* Configure SMC CS3 for NAND/SmartMedia */ - at91_sys_write(AT91_SMC_SETUP(3), - AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) | - AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0)); - at91_sys_write(AT91_SMC_PULSE(3), - AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(3) | - AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(2)); - at91_sys_write(AT91_SMC_CYCLE(3), - AT91_SMC_NWECYCLE_(7) | AT91_SMC_NRDCYCLE_(4)); - at91_sys_write(AT91_SMC_MODE(3), - AT91_SMC_READMODE | AT91_SMC_WRITEMODE | - AT91_SMC_EXNWMODE_DISABLE | + writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | + AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), + &smc->cs[3].setup); + writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(3) | + AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(2), + &smc->cs[3].pulse); + writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(4), + &smc->cs[3].cycle); + writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | + AT91_SMC_MODE_EXNW_DISABLE | #ifdef CONFIG_SYS_NAND_DBW_16 - AT91_SMC_DBW_16 | + AT91_SMC_MODE_DBW_16 | #else /* CONFIG_SYS_NAND_DBW_8 */ - AT91_SMC_DBW_8 | + AT91_SMC_MODE_DBW_8 | #endif - AT91_SMC_TDF_(3)); + AT91_SMC_MODE_TDF_CYCLE(3), + &smc->cs[3].mode); - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_PIOC); + writel(1 << ATMEL_ID_PIOC, &pmc->pcer); /* Configure RDY/BSY */ at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); @@ -90,7 +90,9 @@ static void at91sam9m10g45ek_nand_hw_init(void) #ifdef CONFIG_CMD_USB static void at91sam9m10g45ek_usb_hw_init(void) { - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_PIODE); + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + + writel(1 << ATMEL_ID_PIODE, &pmc->pcer); at91_set_gpio_output(AT91_PIN_PD1, 0); at91_set_gpio_output(AT91_PIN_PD3, 0); @@ -100,47 +102,50 @@ static void at91sam9m10g45ek_usb_hw_init(void) #ifdef CONFIG_MACB static void at91sam9m10g45ek_macb_hw_init(void) { - unsigned long rstc; + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA; + struct at91_rstc *rstc = (struct at91_rstc *)ATMEL_BASE_RSTC; + unsigned long erstl; /* Enable clock */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_EMAC); + writel(1 << ATMEL_ID_EMAC, &pmc->pcer); /* * Disable pull-up on: - * RXDV (PA15) => PHY normal mode (not Test mode) - * ERX0 (PA12) => PHY ADDR0 - * ERX1 (PA13) => PHY ADDR1 => PHYADDR = 0x0 + * RXDV (PA15) => PHY normal mode (not Test mode) + * ERX0 (PA12) => PHY ADDR0 + * ERX1 (PA13) => PHY ADDR1 => PHYADDR = 0x0 * * PHY has internal pull-down */ writel(pin_to_mask(AT91_PIN_PA15) | pin_to_mask(AT91_PIN_PA12) | pin_to_mask(AT91_PIN_PA13), - pin_to_controller(AT91_PIN_PA0) + PIO_PUDR); + &pioa->pudr); - rstc = at91_sys_read(AT91_RSTC_MR); + erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK; /* Need to reset PHY -> 500ms reset */ - at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY | - (AT91_RSTC_ERSTL & (0x0D << 8)) | - AT91_RSTC_URSTEN); + writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(13) | + AT91_RSTC_MR_URSTEN, &rstc->mr); - at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST); + writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr); /* Wait for end hardware reset */ - while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL)); + while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL)) + ; /* Restore NRST value */ - at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY | - (rstc) | - AT91_RSTC_URSTEN); + writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN, + &rstc->mr); /* Re-enable pull-up */ writel(pin_to_mask(AT91_PIN_PA15) | pin_to_mask(AT91_PIN_PA12) | pin_to_mask(AT91_PIN_PA13), - pin_to_controller(AT91_PIN_PA0) + PIO_PUER); + &pioa->puer); + /* And the pins. */ at91_macb_hw_init(); } #endif @@ -161,7 +166,7 @@ vidinfo_t panel_info = { vl_vsync_len: 1, vl_upper_margin:40, vl_lower_margin:1, - mmio: AT91SAM9G45_LCDC_BASE, + mmio : ATMEL_BASE_LCDC, }; @@ -177,6 +182,8 @@ void lcd_disable(void) static void at91sam9m10g45ek_lcd_hw_init(void) { + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + at91_set_A_periph(AT91_PIN_PE0, 0); /* LCDDPWR */ at91_set_A_periph(AT91_PIN_PE2, 0); /* LCDCC */ at91_set_A_periph(AT91_PIN_PE3, 0); /* LCDVSYNC */ @@ -208,7 +215,7 @@ static void at91sam9m10g45ek_lcd_hw_init(void) at91_set_A_periph(AT91_PIN_PE29, 0); /* LCDD22 */ at91_set_A_periph(AT91_PIN_PE30, 0); /* LCDD23 */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_LCDC); + writel(1 << ATMEL_ID_LCDC, &pmc->pcer); gd->fb_base = CONFIG_AT91SAM9G45_LCD_BASE; } @@ -227,7 +234,7 @@ void lcd_show_board_info(void) lcd_printf ("(C) 2008 ATMEL Corp\n"); lcd_printf ("at91support at atmel.com\n"); lcd_printf ("%s CPU at %s MHz\n", - CONFIG_SYS_AT91_CPU_NAME, + ATMEL_CPU_NAME, strmhz(temp, get_cpu_clk_rate())); dram_size = 0; @@ -254,10 +261,10 @@ int board_init(void) #elif defined CONFIG_AT91SAM9G45EKES gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9G45EKES; #endif + /* adress of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; - at91_serial_hw_init(); #ifdef CONFIG_CMD_NAND at91sam9m10g45ek_nand_hw_init(); #endif @@ -270,11 +277,9 @@ int board_init(void) #ifdef CONFIG_ATMEL_SPI at91_spi0_hw_init(1 << 4); #endif - #ifdef CONFIG_MACB at91sam9m10g45ek_macb_hw_init(); #endif - #ifdef CONFIG_LCD at91sam9m10g45ek_lcd_hw_init(); #endif @@ -283,8 +288,8 @@ int board_init(void) int dram_init(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM; - gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; + gd->ram_size = get_ram_size((void*) CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); return 0; } @@ -298,7 +303,7 @@ int board_eth_init(bd_t *bis) { int rc = 0; #ifdef CONFIG_MACB - rc = macb_eth_initialize(0, (void *)AT91SAM9G45_BASE_EMAC, 0x00); + rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00); #endif return rc; } @@ -338,3 +343,15 @@ void spi_cs_deactivate(struct spi_slave *slave) } } #endif /* CONFIG_ATMEL_SPI */ + +extern void at91_serial_hw_init(void); +/* + * (re)Initialize the serial hardware. + */ +int board_early_init_f(void) +{ + + at91_serial_hw_init(); + return 0; + +} diff --git a/board/atmel/at91sam9m10g45ek/led.c b/board/atmel/at91sam9m10g45ek/led.c index ff59a2d..dadbd6a 100644 --- a/board/atmel/at91sam9m10g45ek/led.c +++ b/board/atmel/at91sam9m10g45ek/led.c @@ -23,15 +23,17 @@ */ #include <common.h> +#include <asm/io.h> #include <asm/arch/at91sam9g45.h> #include <asm/arch/at91_pmc.h> #include <asm/arch/gpio.h> -#include <asm/arch/io.h> void coloured_LED_init(void) { + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + /* Enable clock */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_PIODE); + writel(1 << ATMEL_ID_PIODE, &pmc->pcer); at91_set_gpio_output(CONFIG_RED_LED, 1); at91_set_gpio_output(CONFIG_GREEN_LED, 1); diff --git a/boards.cfg b/boards.cfg index 38ccb8c..9dd313b 100644 --- a/boards.cfg +++ b/boards.cfg @@ -96,6 +96,7 @@ at91sam9rlek_dataflash arm arm926ejs at91sam9rlek atmel at91sam9xeek_nandflash arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9XE,SYS_USE_NANDFLASH at91sam9xeek_dataflash_cs0 arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9XE,SYS_USE_DATAFLASH_CS0 at91sam9xeek_dataflash_cs1 arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9XE,SYS_USE_DATAFLASH_CS1 +at91sam9m10g45ek_nandflash arm arm926ejs at91sam9m10g45ek atmel at91 at91sam9m10g45ek:AT91SAM9M10G45,SYS_USE_NANDFLASH snapper9260 arm arm926ejs - bluewater at91 snapper9260:AT91SAM9260 snapper9g20 arm arm926ejs snapper9260 bluewater at91 snapper9260:AT91SAM9G20 cpu9260 arm arm926ejs cpu9260 eukrea at91 cpu9260:CPU9260 diff --git a/include/configs/at91sam9m10g45ek.h b/include/configs/at91sam9m10g45ek.h index de74dcf..384a07c 100644 --- a/include/configs/at91sam9m10g45ek.h +++ b/include/configs/at91sam9m10g45ek.h @@ -27,48 +27,64 @@ #ifndef __CONFIG_H #define __CONFIG_H +#include <asm/hardware.h> + #define CONFIG_AT91_LEGACY +#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ /* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ -#define CONFIG_SYS_HZ 1000 - -#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */ -#ifdef CONFIG_AT91SAM9M10G45EK -#define CONFIG_AT91SAM9M10G45 1 /* It's an Atmel AT91SAM9M10G45 SoC*/ -#else -#define CONFIG_AT91SAM9G45 1 /* It's an Atmel AT91SAM9G45 SoC*/ -#endif +#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 +#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ +#define CONFIG_SYS_HZ 1000 + +#define CONFIG_AT91SAM9M10G45EK +#define CONFIG_AT91FAMILY #define CONFIG_ARCH_CPU_INIT +#define CONFIG_BOARD_EARLY_INIT_F #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG #define CONFIG_SKIP_LOWLEVEL_INIT +#define ATMEL_PIO_PORTS 5 /* 5 PIO ports. */ + /* * Hardware drivers */ -#define CONFIG_AT91_GPIO 1 -#define CONFIG_ATMEL_USART 1 +#define CONFIG_AT91_GPIO +#define CONFIG_ATMEL_USART #undef CONFIG_USART0 #undef CONFIG_USART1 #undef CONFIG_USART2 -#define CONFIG_USART3 1 /* USART 3 is DBGU */ +#define CONFIG_USART3 /* USART 3 is DBGU */ +#define CONFIG_USART_BASE 0xffffee00 /* Use the DBGU hardware. */ +#define CONFIG_USART_ID 10 + +/* + * This needs to be defined for the OHCI code to work but it is defined as + * ATMEL_ID_UHPHS in the CPU specific header files. + */ +#define ATMEL_ID_UHP ATMEL_ID_UHPHS + +/* + * Specify the clock enable bit in the PMC_SCER register. + */ +#define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP /* LCD */ -#define CONFIG_LCD 1 +#define CONFIG_LCD #define LCD_BPP LCD_COLOR8 -#define CONFIG_LCD_LOGO 1 +#define CONFIG_LCD_LOGO #undef LCD_TEST_PATTERN -#define CONFIG_LCD_INFO 1 -#define CONFIG_LCD_INFO_BELOW_LOGO 1 -#define CONFIG_SYS_WHITE_ON_BLACK 1 -#define CONFIG_ATMEL_LCD 1 -#define CONFIG_ATMEL_LCD_RGB565 1 -#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 +#define CONFIG_LCD_INFO +#define CONFIG_LCD_INFO_BELOW_LOGO +#define CONFIG_SYS_WHITE_ON_BLACK +#define CONFIG_ATMEL_LCD +#define CONFIG_ATMEL_LCD_RGB565 +#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* board specific(not enough SRAM) */ #define CONFIG_AT91SAM9G45_LCD_BASE 0x73E00000 @@ -82,10 +98,10 @@ /* * BOOTP options */ -#define CONFIG_BOOTP_BOOTFILESIZE 1 -#define CONFIG_BOOTP_BOOTPATH 1 -#define CONFIG_BOOTP_GATEWAY 1 -#define CONFIG_BOOTP_HOSTNAME 1 +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME /* * Command line configuration. @@ -98,44 +114,29 @@ #undef CONFIG_CMD_AUTOSCRIPT #undef CONFIG_CMD_LOADS -#define CONFIG_CMD_PING 1 -#define CONFIG_CMD_DHCP 1 -#define CONFIG_CMD_NAND 1 -#define CONFIG_CMD_USB 1 +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_NAND +#define CONFIG_CMD_USB /* SDRAM */ #define CONFIG_NR_DRAM_BANKS 1 -#define PHYS_SDRAM 0x70000000 -#define PHYS_SDRAM_SIZE 0x08000000 /* 128 megs */ - -/* DataFlash */ -#ifdef CONFIG_ATMEL_SPI -#define CONFIG_CMD_SF -#define CONFIG_CMD_SPI -#define CONFIG_SPI_FLASH 1 -#define CONFIG_SPI_FLASH_ATMEL 1 -#define CONFIG_SYS_MAX_DATAFLASH_BANKS 1 -#endif +#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS6 +#define CONFIG_SYS_SDRAM_SIZE 0x08000000 -/* NOR flash, if populated */ -#ifndef CONFIG_CMD_NAND -#define CONFIG_SYS_NO_FLASH 1 -#else -#define CONFIG_SYS_FLASH_CFI 1 -#define CONFIG_FLASH_CFI_DRIVER 1 -#define PHYS_FLASH_1 0x10000000 -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 -#define CONFIG_SYS_MAX_FLASH_SECT 256 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#endif +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE) + +/* No NOR flash */ +#define CONFIG_SYS_NO_FLASH /* NAND flash */ #ifdef CONFIG_CMD_NAND #define CONFIG_NAND_MAX_CHIPS 1 #define CONFIG_NAND_ATMEL #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE 0x40000000 -#define CONFIG_SYS_NAND_DBW_8 1 +#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 +#define CONFIG_SYS_NAND_DBW_8 /* our ALE is AD21 */ #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) /* our CLE is AD22 */ @@ -146,68 +147,52 @@ #endif /* Ethernet */ -#define CONFIG_MACB 1 -#define CONFIG_RMII 1 -#define CONFIG_NET_MULTI 1 +#define CONFIG_MACB +#define CONFIG_RMII +#define CONFIG_NET_MULTI #define CONFIG_NET_RETRY_COUNT 20 -#define CONFIG_RESET_PHY_R 1 +#define CONFIG_RESET_PHY_R /* USB */ #define CONFIG_USB_ATMEL -#define CONFIG_USB_OHCI_NEW 1 -#define CONFIG_DOS_PARTITION 1 -#define CONFIG_SYS_USB_OHCI_CPU_INIT 1 -#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00700000 /* AT91SAM9G45_UHP_OHCI_BASE */ -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9g45" +#define CONFIG_USB_OHCI_NEW +#define CONFIG_DOS_PARTITION +#define CONFIG_SYS_USB_OHCI_CPU_INIT +#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_BASE_HCI +#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9g45" #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 -#define CONFIG_USB_STORAGE 1 - -#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ - -#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM -#define CONFIG_SYS_MEMTEST_END 0x23e00000 +#define CONFIG_USB_STORAGE -#ifdef CONFIG_SYS_USE_DATAFLASH +#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ -/* bootstrap + u-boot + env + linux in dataflash on CS0 */ -#define CONFIG_ENV_IS_IN_SPI_FLASH 1 -#define CONFIG_SYS_MONITOR_BASE (0xC0000000 + 0x8400) -#define CONFIG_ENV_OFFSET 0x4200 -#define CONFIG_ENV_ADDR (0xC0000000 + CONFIG_ENV_OFFSET) -#define CONFIG_ENV_SIZE 0x4200 -#define CONFIG_ENV_SECT_SIZE 0x10000 -#define CONFIG_BOOTCOMMAND "cp.b 0xC0042000 0x22000000 0x210000; bootm" -#define CONFIG_BOOTARGS "console=ttyS0,115200 " \ - "root=/dev/mtdblock0 " \ - "mtdparts=atmel_nand:-(root) "\ - "rw rootfstype=jffs2" +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_MEMTEST_END 0x23e00000 -#else /* CONFIG_SYS_USE_NANDFLASH */ - -/* bootstrap + u-boot + env + linux in nandflash */ -#define CONFIG_ENV_IS_IN_NAND 1 +/* bootstrap + u-boot + env in nandflash */ +#define CONFIG_ENV_IS_IN_NAND #define CONFIG_ENV_OFFSET 0x60000 #define CONFIG_ENV_OFFSET_REDUND 0x80000 -#define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */ -#define CONFIG_BOOTCOMMAND "nand read 0x72000000 0x200000 0x200000; bootm" -#define CONFIG_BOOTARGS "console=ttyS0,115200 " \ - "root=/dev/mtdblock5 " \ - "mtdparts=atmel_nand:128k(bootstrap)ro, \ - 256k(uboot)ro,128k(env1)ro,128k(env2)ro, \ - 2M(linux),-(root) " \ - "rw rootfstype=jffs2" - -#endif - -#define CONFIG_BAUDRATE 115200 +#define CONFIG_ENV_SIZE 0x20000 + +#define CONFIG_BOOTCOMMAND "nand read 0x70000000 0x100000 0x200000;" \ + "bootm 0x70000000" +#define CONFIG_BOOTARGS \ + "console=ttyS0,115200 earlyprintk " \ + "root=/dev/mtdblock5 " \ + "mtdparts=atmel_nand:128k(bootstrap)ro," \ + "256k(uboot)ro,128k(env1)ro,128k(env2)ro," \ + "2M@1M(linux),-(root) " \ + "rw rootfstype=jffs2" + +#define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 } #define CONFIG_SYS_PROMPT "U-Boot> " #define CONFIG_SYS_CBSIZE 256 #define CONFIG_SYS_MAXARGS 16 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_LONGHELP 1 -#define CONFIG_CMDLINE_EDITING 1 +#define CONFIG_SYS_LONGHELP +#define CONFIG_CMDLINE_EDITING #define CONFIG_AUTO_COMPLETE #define CONFIG_SYS_HUSH_PARSER #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " -- 1.7.4.1 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* [U-Boot] [PATCH 2/2] atmel: Update support of board AT91SAM9M10G45-EK to new style 2011-08-04 10:10 ` [U-Boot] [PATCH 2/2] atmel: Update support of board AT91SAM9M10G45-EK " Thomas Petazzoni @ 2011-08-04 14:09 ` Reinhard Meyer 0 siblings, 0 replies; 8+ messages in thread From: Reinhard Meyer @ 2011-08-04 14:09 UTC (permalink / raw) To: u-boot Dear Thomas Petazzoni, > Based on earlier work by Alex Waterman <awaterman@dawning.com>. > > Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> > --- > Makefile | 21 --- > board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c | 121 +++++++++------- > board/atmel/at91sam9m10g45ek/led.c | 6 +- > boards.cfg | 1 + > include/configs/at91sam9m10g45ek.h | 187 +++++++++++------------ > 5 files changed, 160 insertions(+), 176 deletions(-) > First, the checkpatch complaints: WARNING: Use #include <linux/io.h> instead of <asm/io.h> #67: FILE: board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c:26: +#include <asm/io.h> --> ignore this ERROR: "(foo*)" should be "(foo *)" #284: FILE: board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c:291: + gd->ram_size = get_ram_size((void*) CONFIG_SYS_SDRAM_BASE, WARNING: externs should be avoided in .c files #303: FILE: board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c:347: +extern void at91_serial_hw_init(void); --> you need to call at91_seriald_hw_init() anyway! WARNING: Use #include <linux/io.h> instead of <asm/io.h> #322: FILE: board/atmel/at91sam9m10g45ek/led.c:26: +#include <asm/io.h> --> ignore this WARNING: please, no space for starting a line, excluding comments #498: FILE: include/configs/at91sam9m10g45ek.h:128: + (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE)$ total: 1 errors, 4 warnings, 550 lines checked U-Boot-2-2-atmel-Update-support-of-board-AT91SAM9M10G45-EK-to-new-style.patch has style problems, please review. > diff --git a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c > index f92b20f..40ee345 100644 > --- a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c > +++ b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c > @@ -23,17 +23,14 @@ > */ > > #include <common.h> > -#include <asm/sizes.h> > -#include <asm/arch/at91sam9g45.h> > -#include <asm/arch/at91sam9_matrix.h> > +#include <asm/io.h> > +#include <asm/arch/at91sam9g45_matrix.h> > #include <asm/arch/at91sam9_smc.h> > #include <asm/arch/at91_common.h> > #include <asm/arch/at91_pmc.h> > #include <asm/arch/at91_rstc.h> > -#include <asm/arch/clk.h> > #include <asm/arch/gpio.h> > -#include <asm/arch/io.h> > -#include <asm/arch/hardware.h> > +#include <asm/arch/clk.h> > #include <lcd.h> > #include <atmel_lcdc.h> > #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB) > @@ -49,35 +46,38 @@ DECLARE_GLOBAL_DATA_PTR; > */ > > #ifdef CONFIG_CMD_NAND > -static void at91sam9m10g45ek_nand_hw_init(void) > +void at91sam9m10g45ek_nand_hw_init(void) > { > + struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; > + struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; > + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; > unsigned long csa; > > /* Enable CS3 */ > - csa = at91_sys_read(AT91_MATRIX_EBICSA); > - at91_sys_write(AT91_MATRIX_EBICSA, > - csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA); > + csa = readl(&matrix->ebicsa); > + csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA; > + writel(csa, &matrix->ebicsa); > > /* Configure SMC CS3 for NAND/SmartMedia */ > - at91_sys_write(AT91_SMC_SETUP(3), > - AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) | > - AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0)); > - at91_sys_write(AT91_SMC_PULSE(3), > - AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(3) | > - AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(2)); > - at91_sys_write(AT91_SMC_CYCLE(3), > - AT91_SMC_NWECYCLE_(7) | AT91_SMC_NRDCYCLE_(4)); > - at91_sys_write(AT91_SMC_MODE(3), > - AT91_SMC_READMODE | AT91_SMC_WRITEMODE | > - AT91_SMC_EXNWMODE_DISABLE | > + writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | > + AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), > + &smc->cs[3].setup); > + writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(3) | > + AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(2), > + &smc->cs[3].pulse); > + writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(4), > + &smc->cs[3].cycle); > + writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | > + AT91_SMC_MODE_EXNW_DISABLE | > #ifdef CONFIG_SYS_NAND_DBW_16 > - AT91_SMC_DBW_16 | > + AT91_SMC_MODE_DBW_16 | > #else /* CONFIG_SYS_NAND_DBW_8 */ > - AT91_SMC_DBW_8 | > + AT91_SMC_MODE_DBW_8 | > #endif > - AT91_SMC_TDF_(3)); > + AT91_SMC_MODE_TDF_CYCLE(3), > + &smc->cs[3].mode); > > - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_PIOC); > + writel(1 << ATMEL_ID_PIOC, &pmc->pcer); > > /* Configure RDY/BSY */ > at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); > @@ -90,7 +90,9 @@ static void at91sam9m10g45ek_nand_hw_init(void) > #ifdef CONFIG_CMD_USB > static void at91sam9m10g45ek_usb_hw_init(void) > { > - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_PIODE); > + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; > + > + writel(1 << ATMEL_ID_PIODE, &pmc->pcer); > > at91_set_gpio_output(AT91_PIN_PD1, 0); > at91_set_gpio_output(AT91_PIN_PD3, 0); > @@ -100,47 +102,50 @@ static void at91sam9m10g45ek_usb_hw_init(void) > #ifdef CONFIG_MACB > static void at91sam9m10g45ek_macb_hw_init(void) > { > - unsigned long rstc; > + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; > + struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA; > + struct at91_rstc *rstc = (struct at91_rstc *)ATMEL_BASE_RSTC; > + unsigned long erstl; > > /* Enable clock */ > - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_EMAC); > + writel(1 << ATMEL_ID_EMAC, &pmc->pcer); > > /* > * Disable pull-up on: > - * RXDV (PA15) => PHY normal mode (not Test mode) > - * ERX0 (PA12) => PHY ADDR0 > - * ERX1 (PA13) => PHY ADDR1 => PHYADDR = 0x0 > + * RXDV (PA15) => PHY normal mode (not Test mode) > + * ERX0 (PA12) => PHY ADDR0 > + * ERX1 (PA13) => PHY ADDR1 => PHYADDR = 0x0 > * > * PHY has internal pull-down > */ > writel(pin_to_mask(AT91_PIN_PA15) | > pin_to_mask(AT91_PIN_PA12) | > pin_to_mask(AT91_PIN_PA13), > - pin_to_controller(AT91_PIN_PA0) + PIO_PUDR); > + &pioa->pudr); > > - rstc = at91_sys_read(AT91_RSTC_MR); > + erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK; > > /* Need to reset PHY -> 500ms reset */ > - at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY | > - (AT91_RSTC_ERSTL & (0x0D << 8)) | > - AT91_RSTC_URSTEN); > + writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(13) | > + AT91_RSTC_MR_URSTEN, &rstc->mr); > > - at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST); > + writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr); > > /* Wait for end hardware reset */ > - while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL)); > + while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL)) > + ; > > /* Restore NRST value */ > - at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY | > - (rstc) | > - AT91_RSTC_URSTEN); > + writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN, > + &rstc->mr); > > /* Re-enable pull-up */ > writel(pin_to_mask(AT91_PIN_PA15) | > pin_to_mask(AT91_PIN_PA12) | > pin_to_mask(AT91_PIN_PA13), > - pin_to_controller(AT91_PIN_PA0) + PIO_PUER); > + &pioa->puer); > > + /* And the pins. */ > at91_macb_hw_init(); > } > #endif > @@ -161,7 +166,7 @@ vidinfo_t panel_info = { > vl_vsync_len: 1, > vl_upper_margin:40, > vl_lower_margin:1, > - mmio: AT91SAM9G45_LCDC_BASE, > + mmio : ATMEL_BASE_LCDC, > }; > > > @@ -177,6 +182,8 @@ void lcd_disable(void) > > static void at91sam9m10g45ek_lcd_hw_init(void) > { > + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; > + > at91_set_A_periph(AT91_PIN_PE0, 0); /* LCDDPWR */ > at91_set_A_periph(AT91_PIN_PE2, 0); /* LCDCC */ > at91_set_A_periph(AT91_PIN_PE3, 0); /* LCDVSYNC */ > @@ -208,7 +215,7 @@ static void at91sam9m10g45ek_lcd_hw_init(void) > at91_set_A_periph(AT91_PIN_PE29, 0); /* LCDD22 */ > at91_set_A_periph(AT91_PIN_PE30, 0); /* LCDD23 */ > > - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_LCDC); > + writel(1 << ATMEL_ID_LCDC, &pmc->pcer); > > gd->fb_base = CONFIG_AT91SAM9G45_LCD_BASE; > } > @@ -227,7 +234,7 @@ void lcd_show_board_info(void) > lcd_printf ("(C) 2008 ATMEL Corp\n"); > lcd_printf ("at91support at atmel.com\n"); > lcd_printf ("%s CPU at %s MHz\n", > - CONFIG_SYS_AT91_CPU_NAME, > + ATMEL_CPU_NAME, > strmhz(temp, get_cpu_clk_rate())); > > dram_size = 0; > @@ -254,10 +261,10 @@ int board_init(void) > #elif defined CONFIG_AT91SAM9G45EKES > gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9G45EKES; > #endif > + > /* adress of boot parameters */ > - gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; > + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; > > - at91_serial_hw_init(); > #ifdef CONFIG_CMD_NAND > at91sam9m10g45ek_nand_hw_init(); > #endif > @@ -270,11 +277,9 @@ int board_init(void) > #ifdef CONFIG_ATMEL_SPI > at91_spi0_hw_init(1 << 4); > #endif > - > #ifdef CONFIG_MACB > at91sam9m10g45ek_macb_hw_init(); > #endif > - > #ifdef CONFIG_LCD > at91sam9m10g45ek_lcd_hw_init(); > #endif > @@ -283,8 +288,8 @@ int board_init(void) > > int dram_init(void) > { > - gd->bd->bi_dram[0].start = PHYS_SDRAM; > - gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; > + gd->ram_size = get_ram_size((void*) CONFIG_SYS_SDRAM_BASE, > + CONFIG_SYS_SDRAM_SIZE); > return 0; > } > > @@ -298,7 +303,7 @@ int board_eth_init(bd_t *bis) > { > int rc = 0; > #ifdef CONFIG_MACB > - rc = macb_eth_initialize(0, (void *)AT91SAM9G45_BASE_EMAC, 0x00); > + rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00); > #endif > return rc; > } > @@ -338,3 +343,15 @@ void spi_cs_deactivate(struct spi_slave *slave) > } > } > #endif /* CONFIG_ATMEL_SPI */ > + > +extern void at91_serial_hw_init(void); > +/* > + * (re)Initialize the serial hardware. > + */ > +int board_early_init_f(void) > +{ > + > + at91_serial_hw_init(); --> *seriald* > + return 0; > + > +} > diff --git a/boards.cfg b/boards.cfg > index 38ccb8c..9dd313b 100644 > --- a/boards.cfg > +++ b/boards.cfg > @@ -96,6 +96,7 @@ at91sam9rlek_dataflash arm arm926ejs at91sam9rlek atmel > at91sam9xeek_nandflash arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9XE,SYS_USE_NANDFLASH > at91sam9xeek_dataflash_cs0 arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9XE,SYS_USE_DATAFLASH_CS0 > at91sam9xeek_dataflash_cs1 arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9XE,SYS_USE_DATAFLASH_CS1 > +at91sam9m10g45ek_nandflash arm arm926ejs at91sam9m10g45ek atmel at91 at91sam9m10g45ek:AT91SAM9M10G45,SYS_USE_NANDFLASH "m" comes before "x" - and the indentation seems off by one space > snapper9260 arm arm926ejs - bluewater at91 snapper9260:AT91SAM9260 > snapper9g20 arm arm926ejs snapper9260 bluewater at91 snapper9260:AT91SAM9G20 > cpu9260 arm arm926ejs cpu9260 eukrea at91 cpu9260:CPU9260 > diff --git a/include/configs/at91sam9m10g45ek.h b/include/configs/at91sam9m10g45ek.h > index de74dcf..384a07c 100644 > --- a/include/configs/at91sam9m10g45ek.h > +++ b/include/configs/at91sam9m10g45ek.h > @@ -27,48 +27,64 @@ > #ifndef __CONFIG_H > #define __CONFIG_H > > +#include <asm/hardware.h> > + > #define CONFIG_AT91_LEGACY > +#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ > > /* ARM asynchronous clock */ > -#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ > -#define CONFIG_SYS_HZ 1000 > - > -#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */ > -#ifdef CONFIG_AT91SAM9M10G45EK > -#define CONFIG_AT91SAM9M10G45 1 /* It's an Atmel AT91SAM9M10G45 SoC*/ > -#else > -#define CONFIG_AT91SAM9G45 1 /* It's an Atmel AT91SAM9G45 SoC*/ > -#endif > +#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 > +#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ > +#define CONFIG_SYS_HZ 1000 > + > +#define CONFIG_AT91SAM9M10G45EK > +#define CONFIG_AT91FAMILY > #define CONFIG_ARCH_CPU_INIT > +#define CONFIG_BOARD_EARLY_INIT_F > #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ > > -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ > -#define CONFIG_SETUP_MEMORY_TAGS 1 > -#define CONFIG_INITRD_TAG 1 > +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ > +#define CONFIG_SETUP_MEMORY_TAGS > +#define CONFIG_INITRD_TAG > > #define CONFIG_SKIP_LOWLEVEL_INIT > > +#define ATMEL_PIO_PORTS 5 /* 5 PIO ports. */ THAT does not belong here. It should be in at91sam9m10g45.h > + > /* > * Hardware drivers > */ > -#define CONFIG_AT91_GPIO 1 > -#define CONFIG_ATMEL_USART 1 > +#define CONFIG_AT91_GPIO > +#define CONFIG_ATMEL_USART > #undef CONFIG_USART0 > #undef CONFIG_USART1 > #undef CONFIG_USART2 > -#define CONFIG_USART3 1 /* USART 3 is DBGU */ > +#define CONFIG_USART3 /* USART 3 is DBGU */ Nope. This is wrong. See other 926x boards! > +#define CONFIG_USART_BASE 0xffffee00 /* Use the DBGU hardware. */ > +#define CONFIG_USART_ID 10 OUCH. There are defines for that in at91sam9m10g45.h > + > +/* > + * This needs to be defined for the OHCI code to work but it is defined as > + * ATMEL_ID_UHPHS in the CPU specific header files. > + */ > +#define ATMEL_ID_UHP ATMEL_ID_UHPHS > + > +/* > + * Specify the clock enable bit in the PMC_SCER register. > + */ > +#define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP > > /* LCD */ > -#define CONFIG_LCD 1 > +#define CONFIG_LCD > #define LCD_BPP LCD_COLOR8 > -#define CONFIG_LCD_LOGO 1 > +#define CONFIG_LCD_LOGO > #undef LCD_TEST_PATTERN > -#define CONFIG_LCD_INFO 1 > -#define CONFIG_LCD_INFO_BELOW_LOGO 1 > -#define CONFIG_SYS_WHITE_ON_BLACK 1 > -#define CONFIG_ATMEL_LCD 1 > -#define CONFIG_ATMEL_LCD_RGB565 1 > -#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 > +#define CONFIG_LCD_INFO > +#define CONFIG_LCD_INFO_BELOW_LOGO > +#define CONFIG_SYS_WHITE_ON_BLACK > +#define CONFIG_ATMEL_LCD > +#define CONFIG_ATMEL_LCD_RGB565 > +#define CONFIG_SYS_CONSOLE_IS_IN_ENV > /* board specific(not enough SRAM) */ > #define CONFIG_AT91SAM9G45_LCD_BASE 0x73E00000 > > @@ -82,10 +98,10 @@ > /* > * BOOTP options > */ > -#define CONFIG_BOOTP_BOOTFILESIZE 1 > -#define CONFIG_BOOTP_BOOTPATH 1 > -#define CONFIG_BOOTP_GATEWAY 1 > -#define CONFIG_BOOTP_HOSTNAME 1 > +#define CONFIG_BOOTP_BOOTFILESIZE > +#define CONFIG_BOOTP_BOOTPATH > +#define CONFIG_BOOTP_GATEWAY > +#define CONFIG_BOOTP_HOSTNAME > > /* > * Command line configuration. > @@ -98,44 +114,29 @@ > #undef CONFIG_CMD_AUTOSCRIPT > #undef CONFIG_CMD_LOADS > > -#define CONFIG_CMD_PING 1 > -#define CONFIG_CMD_DHCP 1 > -#define CONFIG_CMD_NAND 1 > -#define CONFIG_CMD_USB 1 > +#define CONFIG_CMD_PING > +#define CONFIG_CMD_DHCP > +#define CONFIG_CMD_NAND > +#define CONFIG_CMD_USB > > /* SDRAM */ > #define CONFIG_NR_DRAM_BANKS 1 > -#define PHYS_SDRAM 0x70000000 > -#define PHYS_SDRAM_SIZE 0x08000000 /* 128 megs */ > - > -/* DataFlash */ > -#ifdef CONFIG_ATMEL_SPI > -#define CONFIG_CMD_SF > -#define CONFIG_CMD_SPI > -#define CONFIG_SPI_FLASH 1 > -#define CONFIG_SPI_FLASH_ATMEL 1 > -#define CONFIG_SYS_MAX_DATAFLASH_BANKS 1 > -#endif > +#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS6 > +#define CONFIG_SYS_SDRAM_SIZE 0x08000000 > > -/* NOR flash, if populated */ > -#ifndef CONFIG_CMD_NAND > -#define CONFIG_SYS_NO_FLASH 1 > -#else > -#define CONFIG_SYS_FLASH_CFI 1 > -#define CONFIG_FLASH_CFI_DRIVER 1 > -#define PHYS_FLASH_1 0x10000000 > -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 > -#define CONFIG_SYS_MAX_FLASH_SECT 256 > -#define CONFIG_SYS_MAX_FLASH_BANKS 1 > -#endif > +#define CONFIG_SYS_INIT_SP_ADDR \ > + (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE) > + > +/* No NOR flash */ > +#define CONFIG_SYS_NO_FLASH > > /* NAND flash */ > #ifdef CONFIG_CMD_NAND > #define CONFIG_NAND_MAX_CHIPS 1 > #define CONFIG_NAND_ATMEL > #define CONFIG_SYS_MAX_NAND_DEVICE 1 > -#define CONFIG_SYS_NAND_BASE 0x40000000 > -#define CONFIG_SYS_NAND_DBW_8 1 > +#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 > +#define CONFIG_SYS_NAND_DBW_8 > /* our ALE is AD21 */ > #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) > /* our CLE is AD22 */ > @@ -146,68 +147,52 @@ > #endif > > /* Ethernet */ > -#define CONFIG_MACB 1 > -#define CONFIG_RMII 1 > -#define CONFIG_NET_MULTI 1 > +#define CONFIG_MACB > +#define CONFIG_RMII > +#define CONFIG_NET_MULTI > #define CONFIG_NET_RETRY_COUNT 20 > -#define CONFIG_RESET_PHY_R 1 > +#define CONFIG_RESET_PHY_R > > /* USB */ > #define CONFIG_USB_ATMEL > -#define CONFIG_USB_OHCI_NEW 1 > -#define CONFIG_DOS_PARTITION 1 > -#define CONFIG_SYS_USB_OHCI_CPU_INIT 1 > -#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00700000 /* AT91SAM9G45_UHP_OHCI_BASE */ > -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9g45" > +#define CONFIG_USB_OHCI_NEW > +#define CONFIG_DOS_PARTITION > +#define CONFIG_SYS_USB_OHCI_CPU_INIT > +#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_BASE_HCI > +#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9g45" > #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 > -#define CONFIG_USB_STORAGE 1 > - > -#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ > - > -#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM > -#define CONFIG_SYS_MEMTEST_END 0x23e00000 > +#define CONFIG_USB_STORAGE > > -#ifdef CONFIG_SYS_USE_DATAFLASH > +#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ > > -/* bootstrap + u-boot + env + linux in dataflash on CS0 */ > -#define CONFIG_ENV_IS_IN_SPI_FLASH 1 > -#define CONFIG_SYS_MONITOR_BASE (0xC0000000 + 0x8400) > -#define CONFIG_ENV_OFFSET 0x4200 > -#define CONFIG_ENV_ADDR (0xC0000000 + CONFIG_ENV_OFFSET) > -#define CONFIG_ENV_SIZE 0x4200 > -#define CONFIG_ENV_SECT_SIZE 0x10000 > -#define CONFIG_BOOTCOMMAND "cp.b 0xC0042000 0x22000000 0x210000; bootm" > -#define CONFIG_BOOTARGS "console=ttyS0,115200 " \ > - "root=/dev/mtdblock0 " \ > - "mtdparts=atmel_nand:-(root) "\ > - "rw rootfstype=jffs2" > +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE > +#define CONFIG_SYS_MEMTEST_END 0x23e00000 > > -#else /* CONFIG_SYS_USE_NANDFLASH */ > - > -/* bootstrap + u-boot + env + linux in nandflash */ > -#define CONFIG_ENV_IS_IN_NAND 1 > +/* bootstrap + u-boot + env in nandflash */ > +#define CONFIG_ENV_IS_IN_NAND > #define CONFIG_ENV_OFFSET 0x60000 > #define CONFIG_ENV_OFFSET_REDUND 0x80000 > -#define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */ > -#define CONFIG_BOOTCOMMAND "nand read 0x72000000 0x200000 0x200000; bootm" > -#define CONFIG_BOOTARGS "console=ttyS0,115200 " \ > - "root=/dev/mtdblock5 " \ > - "mtdparts=atmel_nand:128k(bootstrap)ro, \ > - 256k(uboot)ro,128k(env1)ro,128k(env2)ro, \ > - 2M(linux),-(root) " \ > - "rw rootfstype=jffs2" > - > -#endif > - > -#define CONFIG_BAUDRATE 115200 > +#define CONFIG_ENV_SIZE 0x20000 > + > +#define CONFIG_BOOTCOMMAND "nand read 0x70000000 0x100000 0x200000;" \ > + "bootm 0x70000000" > +#define CONFIG_BOOTARGS \ > + "console=ttyS0,115200 earlyprintk " \ > + "root=/dev/mtdblock5 " \ > + "mtdparts=atmel_nand:128k(bootstrap)ro," \ > + "256k(uboot)ro,128k(env1)ro,128k(env2)ro," \ > + "2M at 1M(linux),-(root) " \ > + "rw rootfstype=jffs2" > + > +#define CONFIG_BAUDRATE 115200 > #define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 } > > #define CONFIG_SYS_PROMPT "U-Boot> " > #define CONFIG_SYS_CBSIZE 256 > #define CONFIG_SYS_MAXARGS 16 > #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) > -#define CONFIG_SYS_LONGHELP 1 > -#define CONFIG_CMDLINE_EDITING 1 > +#define CONFIG_SYS_LONGHELP > +#define CONFIG_CMDLINE_EDITING > #define CONFIG_AUTO_COMPLETE > #define CONFIG_SYS_HUSH_PARSER > #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " Best Regards, Reinhard ^ permalink raw reply [flat|nested] 8+ messages in thread
* [U-Boot] (no subject) @ 2011-08-04 18:53 Thomas Petazzoni 2011-08-04 18:53 ` [U-Boot] [PATCH 1/2] atmel: update at91sam9m10g45 SoC support to new style Thomas Petazzoni 0 siblings, 1 reply; 8+ messages in thread From: Thomas Petazzoni @ 2011-08-04 18:53 UTC (permalink / raw) To: u-boot Subject: [v2] Update at91sam9m10g45 SoC and AT91SAM9M10G45-EK board to new style Hello, These two patches update the support of the AT91SAM9M10G45 SoC and the corresponding AT91SAM9M10G45-EK evaluation platform to the next AT91 organization. For the moment, only the nandflash configuration is supported, the dataflash configuration will come later on. Note however that the AT91 Ethernet driver doesn't work in the current master, due to the D-cache being enabled by c2dd0d45540397704de9b13287417d21049d34c6. The call to dcache_enable(); in arch/arm/lib/board.c must be removed. Changes since v1: - Fixed multiple style issues - Fixed the DBGU support - Support pull-ups as done for at91sam9260 Best regards, Thomas Petazzoni -- Thomas Petazzoni, Free Electrons Kernel, drivers, real-time and embedded Linux development, consulting, training and support. http://free-electrons.com ^ permalink raw reply [flat|nested] 8+ messages in thread
* [U-Boot] [PATCH 1/2] atmel: update at91sam9m10g45 SoC support to new style 2011-08-04 18:53 [U-Boot] (no subject) Thomas Petazzoni @ 2011-08-04 18:53 ` Thomas Petazzoni 2011-08-04 20:17 ` Reinhard Meyer 0 siblings, 1 reply; 8+ messages in thread From: Thomas Petazzoni @ 2011-08-04 18:53 UTC (permalink / raw) To: u-boot Based on earlier work by Alex Waterman <awaterman@dawning.com>. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> --- .../cpu/arm926ejs/at91/at91sam9m10g45_devices.c | 114 ++++++------ arch/arm/include/asm/arch-at91/at91sam9g45.h | 12 ++ .../arm/include/asm/arch-at91/at91sam9g45_matrix.h | 194 +++++++------------- 3 files changed, 135 insertions(+), 185 deletions(-) diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9m10g45_devices.c b/arch/arm/cpu/arm926ejs/at91/at91sam9m10g45_devices.c index 4ad9b1f..5ff32e3 100644 --- a/arch/arm/cpu/arm926ejs/at91/at91sam9m10g45_devices.c +++ b/arch/arm/cpu/arm926ejs/at91/at91sam9m10g45_devices.c @@ -26,135 +26,131 @@ #include <asm/arch/at91_common.h> #include <asm/arch/at91_pmc.h> #include <asm/arch/gpio.h> -#include <asm/arch/io.h> +#include <asm/io.h> + +/* + * if CONFIG_AT91_GPIO_PULLUP ist set, keep pullups on on all + * peripheral pins. Good to have if hardware is soldered optionally + * or in case of SPI no slave is selected. Avoid lines to float + * needlessly. Use a short local PUP define. + * + * Due to errata "TXD floats when CTS is inactive" pullups are always + * on for TXD pins. + */ +#ifdef CONFIG_AT91_GPIO_PULLUP +# define PUP CONFIG_AT91_GPIO_PULLUP +#else +# define PUP 0 +#endif void at91_serial0_hw_init(void) { - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; at91_set_a_periph(AT91_PIO_PORTB, 19, 1); /* TXD0 */ - at91_set_a_periph(AT91_PIO_PORTB, 18, 0); /* RXD0 */ - writel(1 << AT91SAM9G45_ID_US0, &pmc->pcer); + at91_set_a_periph(AT91_PIO_PORTB, 18, PUP); /* RXD0 */ + writel(1 << ATMEL_ID_USART0, &pmc->pcer); } void at91_serial1_hw_init(void) { - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; at91_set_a_periph(AT91_PIO_PORTB, 4, 1); /* TXD1 */ - at91_set_a_periph(AT91_PIO_PORTB, 5, 0); /* RXD1 */ - writel(1 << AT91SAM9G45_ID_US1, &pmc->pcer); + at91_set_a_periph(AT91_PIO_PORTB, 5, PUP); /* RXD1 */ + writel(1 << ATMEL_ID_USART1, &pmc->pcer); } void at91_serial2_hw_init(void) { - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; at91_set_a_periph(AT91_PIO_PORTD, 6, 1); /* TXD2 */ - at91_set_a_periph(AT91_PIO_PORTD, 7, 0); /* RXD2 */ - writel(1 << AT91SAM9G45_ID_US2, &pmc->pcer); + at91_set_a_periph(AT91_PIO_PORTD, 7, PUP); /* RXD2 */ + writel(1 << ATMEL_ID_USART2, &pmc->pcer); } -void at91_serial3_hw_init(void) +void at91_seriald_hw_init(void) { - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; at91_set_a_periph(AT91_PIO_PORTB, 12, 0); /* DRXD */ at91_set_a_periph(AT91_PIO_PORTB, 13, 1); /* DTXD */ - writel(1 << AT91_ID_SYS, &pmc->pcer); -} - -void at91_serial_hw_init(void) -{ -#ifdef CONFIG_USART0 - at91_serial0_hw_init(); -#endif - -#ifdef CONFIG_USART1 - at91_serial1_hw_init(); -#endif - -#ifdef CONFIG_USART2 - at91_serial2_hw_init(); -#endif - -#ifdef CONFIG_USART3 /* DBGU */ - at91_serial3_hw_init(); -#endif + writel(1 << ATMEL_ID_SYS, &pmc->pcer); } -#ifdef CONFIG_ATMEL_SPI +#if defined(CONFIG_HAS_DATAFLASH) || defined(CONFIG_ATMEL_SPI) void at91_spi0_hw_init(unsigned long cs_mask) { - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; - at91_set_a_periph(AT91_PIO_PORTB, 0, 0); /* SPI0_MISO */ - at91_set_a_periph(AT91_PIO_PORTB, 1, 0); /* SPI0_MOSI */ - at91_set_a_periph(AT91_PIO_PORTB, 2, 0); /* SPI0_SPCK */ + at91_set_a_periph(AT91_PIO_PORTB, 0, PUP); /* SPI0_MISO */ + at91_set_a_periph(AT91_PIO_PORTB, 1, PUP); /* SPI0_MOSI */ + at91_set_a_periph(AT91_PIO_PORTB, 2, PUP); /* SPI0_SPCK */ /* Enable clock */ - writel(1 << AT91SAM9G45_ID_SPI0, &pmc->pcer); + writel(1 << ATMEL_ID_SPI0, &pmc->pcer); if (cs_mask & (1 << 0)) { - at91_set_a_periph(AT91_PIO_PORTB, 3, 0); + at91_set_a_periph(AT91_PIO_PORTB, 3, 1); } if (cs_mask & (1 << 1)) { - at91_set_b_periph(AT91_PIO_PORTB, 18, 0); + at91_set_b_periph(AT91_PIO_PORTB, 18, 1); } if (cs_mask & (1 << 2)) { - at91_set_b_periph(AT91_PIO_PORTB, 19, 0); + at91_set_b_periph(AT91_PIO_PORTB, 19, 1); } if (cs_mask & (1 << 3)) { - at91_set_b_periph(AT91_PIO_PORTD, 27, 0); + at91_set_b_periph(AT91_PIO_PORTD, 27, 1); } if (cs_mask & (1 << 4)) { - at91_set_pio_output(AT91_PIO_PORTB, 3, 0); + at91_set_pio_output(AT91_PIO_PORTB, 3, 1); } if (cs_mask & (1 << 5)) { - at91_set_pio_output(AT91_PIO_PORTB, 18, 0); + at91_set_pio_output(AT91_PIO_PORTB, 18, 1); } if (cs_mask & (1 << 6)) { - at91_set_pio_output(AT91_PIO_PORTB, 19, 0); + at91_set_pio_output(AT91_PIO_PORTB, 19, 1); } if (cs_mask & (1 << 7)) { - at91_set_pio_output(AT91_PIO_PORTD, 27, 0); + at91_set_pio_output(AT91_PIO_PORTD, 27, 1); } } void at91_spi1_hw_init(unsigned long cs_mask) { - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; - at91_set_a_periph(AT91_PIO_PORTB, 14, 0); /* SPI1_MISO */ - at91_set_a_periph(AT91_PIO_PORTB, 15, 0); /* SPI1_MOSI */ - at91_set_a_periph(AT91_PIO_PORTB, 16, 0); /* SPI1_SPCK */ + at91_set_a_periph(AT91_PIO_PORTB, 14, PUP); /* SPI1_MISO */ + at91_set_a_periph(AT91_PIO_PORTB, 15, PUP); /* SPI1_MOSI */ + at91_set_a_periph(AT91_PIO_PORTB, 16, PUP); /* SPI1_SPCK */ /* Enable clock */ - writel(1 << AT91SAM9G45_ID_SPI1, &pmc->pcer); + writel(1 << ATMEL_ID_SPI1, &pmc->pcer); if (cs_mask & (1 << 0)) { - at91_set_a_periph(AT91_PIO_PORTB, 17, 0); + at91_set_a_periph(AT91_PIO_PORTB, 17, 1); } if (cs_mask & (1 << 1)) { - at91_set_b_periph(AT91_PIO_PORTD, 28, 0); + at91_set_b_periph(AT91_PIO_PORTD, 28, 1); } if (cs_mask & (1 << 2)) { - at91_set_a_periph(AT91_PIO_PORTD, 18, 0); + at91_set_a_periph(AT91_PIO_PORTD, 18, 1); } if (cs_mask & (1 << 3)) { - at91_set_a_periph(AT91_PIO_PORTD, 19, 0); + at91_set_a_periph(AT91_PIO_PORTD, 19, 1); } if (cs_mask & (1 << 4)) { - at91_set_pio_output(AT91_PIO_PORTB, 17, 0); + at91_set_pio_output(AT91_PIO_PORTB, 17, 1); } if (cs_mask & (1 << 5)) { - at91_set_pio_output(AT91_PIO_PORTD, 28, 0); + at91_set_pio_output(AT91_PIO_PORTD, 28, 1); } if (cs_mask & (1 << 6)) { - at91_set_pio_output(AT91_PIO_PORTD, 18, 0); + at91_set_pio_output(AT91_PIO_PORTD, 18, 1); } if (cs_mask & (1 << 7)) { - at91_set_pio_output(AT91_PIO_PORTD, 19, 0); + at91_set_pio_output(AT91_PIO_PORTD, 19, 1); } } diff --git a/arch/arm/include/asm/arch-at91/at91sam9g45.h b/arch/arm/include/asm/arch-at91/at91sam9g45.h index 364b86c..4df6b09 100644 --- a/arch/arm/include/asm/arch-at91/at91sam9g45.h +++ b/arch/arm/include/asm/arch-at91/at91sam9g45.h @@ -129,6 +129,18 @@ #define ATMEL_BASE_VDEC 0x00900000 /* Video Decoder Controller */ /* + * External memory + */ +#define ATMEL_BASE_CS0 0x10000000 +#define ATMEL_BASE_CS1 0x20000000 +#define ATMEL_BASE_CS2 0x30000000 +#define ATMEL_BASE_CS3 0x40000000 +#define ATMEL_BASE_CS4 0x50000000 +#define ATMEL_BASE_CS5 0x60000000 +#define ATMEL_BASE_CS6 0x70000000 +#define ATMEL_BASE_CS7 0x80000000 + +/* * Other misc defines */ #define ATMEL_PIO_PORTS 5 /* this SoCs has 5 PIO */ diff --git a/arch/arm/include/asm/arch-at91/at91sam9g45_matrix.h b/arch/arm/include/asm/arch-at91/at91sam9g45_matrix.h index 1620e1b..01c9c63 100644 --- a/arch/arm/include/asm/arch-at91/at91sam9g45_matrix.h +++ b/arch/arm/include/asm/arch-at91/at91sam9g45_matrix.h @@ -15,139 +15,81 @@ #ifndef AT91SAM9G45_MATRIX_H #define AT91SAM9G45_MATRIX_H -#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */ -#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */ -#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */ -#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */ -#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */ -#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */ -#define AT91_MATRIX_MCFG6 (AT91_MATRIX + 0x18) /* Master Configuration Register 6 */ -#define AT91_MATRIX_MCFG7 (AT91_MATRIX + 0x1C) /* Master Configuration Register 7 */ -#define AT91_MATRIX_MCFG8 (AT91_MATRIX + 0x20) /* Master Configuration Register 8 */ -#define AT91_MATRIX_MCFG9 (AT91_MATRIX + 0x24) /* Master Configuration Register 9 */ -#define AT91_MATRIX_MCFG10 (AT91_MATRIX + 0x28) /* Master Configuration Register 10 */ -#define AT91_MATRIX_MCFG11 (AT91_MATRIX + 0x2C) /* Master Configuration Register 11 */ -#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */ -#define AT91_MATRIX_ULBT_INFINITE (0 << 0) -#define AT91_MATRIX_ULBT_SINGLE (1 << 0) -#define AT91_MATRIX_ULBT_FOUR (2 << 0) -#define AT91_MATRIX_ULBT_EIGHT (3 << 0) -#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0) -#define AT91_MATRIX_ULBT_THIRTYTWO (5 << 0) -#define AT91_MATRIX_ULBT_SIXTYFOUR (6 << 0) -#define AT91_MATRIX_ULBT_128 (7 << 0) +#ifndef __ASSEMBLY__ -#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */ -#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */ -#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */ -#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */ -#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */ -#define AT91_MATRIX_SCFG5 (AT91_MATRIX + 0x54) /* Slave Configuration Register 5 */ -#define AT91_MATRIX_SCFG6 (AT91_MATRIX + 0x58) /* Slave Configuration Register 6 */ -#define AT91_MATRIX_SCFG7 (AT91_MATRIX + 0x5C) /* Slave Configuration Register 7 */ -#define AT91_MATRIX_SLOT_CYCLE (0x1ff << 0) /* Maximum Number of Allowed Cycles for a Burst */ -#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */ -#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) -#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) -#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) -#define AT91_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */ +struct at91_matrix { + u32 mcfg[16]; + u32 scfg[16]; + u32 pras[16][2]; + u32 mrcr; /* 0x100 Master Remap Control */ + u32 filler[3]; + u32 tcmr; + u32 filler2; + u32 ddrmpr; + u32 filler3[3]; + u32 ebicsa; + u32 filler4[47]; + u32 wpmr; + u32 wpsr; +}; -#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */ -#define AT91_MATRIX_PRBS0 (AT91_MATRIX + 0x84) /* Priority Register B for Slave 0 */ -#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */ -#define AT91_MATRIX_PRBS1 (AT91_MATRIX + 0x8C) /* Priority Register B for Slave 1 */ -#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */ -#define AT91_MATRIX_PRBS2 (AT91_MATRIX + 0x94) /* Priority Register B for Slave 2 */ -#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */ -#define AT91_MATRIX_PRBS3 (AT91_MATRIX + 0x9C) /* Priority Register B for Slave 3 */ -#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */ -#define AT91_MATRIX_PRBS4 (AT91_MATRIX + 0xA4) /* Priority Register B for Slave 4 */ -#define AT91_MATRIX_PRAS5 (AT91_MATRIX + 0xA8) /* Priority Register A for Slave 5 */ -#define AT91_MATRIX_PRBS5 (AT91_MATRIX + 0xAC) /* Priority Register B for Slave 5 */ -#define AT91_MATRIX_PRAS6 (AT91_MATRIX + 0xB0) /* Priority Register A for Slave 6 */ -#define AT91_MATRIX_PRBS6 (AT91_MATRIX + 0xB4) /* Priority Register B for Slave 6 */ -#define AT91_MATRIX_PRAS7 (AT91_MATRIX + 0xB8) /* Priority Register A for Slave 7 */ -#define AT91_MATRIX_PRBS7 (AT91_MATRIX + 0xBC) /* Priority Register B for Slave 7 */ -#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */ -#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */ -#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */ -#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */ -#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */ -#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */ -#define AT91_MATRIX_M6PR (3 << 24) /* Master 6 Priority */ -#define AT91_MATRIX_M7PR (3 << 28) /* Master 7 Priority */ -#define AT91_MATRIX_M8PR (3 << 0) /* Master 8 Priority (in Register B) */ -#define AT91_MATRIX_M9PR (3 << 4) /* Master 9 Priority (in Register B) */ -#define AT91_MATRIX_M10PR (3 << 8) /* Master 10 Priority (in Register B) */ -#define AT91_MATRIX_M11PR (3 << 12) /* Master 11 Priority (in Register B) */ +#endif /* __ASSEMBLY__ */ -#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */ -#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ -#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ -#define AT91_MATRIX_RCB2 (1 << 2) -#define AT91_MATRIX_RCB3 (1 << 3) -#define AT91_MATRIX_RCB4 (1 << 4) -#define AT91_MATRIX_RCB5 (1 << 5) -#define AT91_MATRIX_RCB6 (1 << 6) -#define AT91_MATRIX_RCB7 (1 << 7) -#define AT91_MATRIX_RCB8 (1 << 8) -#define AT91_MATRIX_RCB9 (1 << 9) -#define AT91_MATRIX_RCB10 (1 << 10) -#define AT91_MATRIX_RCB11 (1 << 11) +#define AT91_MATRIX_ULBT_INFINITE (0 << 0) +#define AT91_MATRIX_ULBT_SINGLE (1 << 0) +#define AT91_MATRIX_ULBT_FOUR (2 << 0) +#define AT91_MATRIX_ULBT_EIGHT (3 << 0) +#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0) +#define AT91_MATRIX_ULBT_THIRTYTWO (5 << 0) +#define AT91_MATRIX_ULBT_SIXTYFOUR (6 << 0) +#define AT91_MATRIX_ULBT_128 (7 << 0) -#define AT91_MATRIX_TCMR (AT91_MATRIX + 0x110) /* TCM Configuration Register */ -#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */ -#define AT91_MATRIX_ITCM_0 (0 << 0) -#define AT91_MATRIX_ITCM_32 (6 << 0) -#define AT91_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */ -#define AT91_MATRIX_DTCM_0 (0 << 4) -#define AT91_MATRIX_DTCM_32 (6 << 4) -#define AT91_MATRIX_DTCM_64 (7 << 4) -#define AT91_MATRIX_TCM_NWS (0x1 << 11) /* Wait state TCM register */ -#define AT91_MATRIX_TCM_NO_WS (0x0 << 11) -#define AT91_MATRIX_TCM_ONE_WS (0x1 << 11) +#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) +#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) +#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) +#define AT91_MATRIX_FIXED_DEFMSTR_SHIFT 18 -#define AT91_MATRIX_VIDEO (AT91_MATRIX + 0x118) /* Video Mode Configuration Register */ -#define AT91C_VDEC_SEL (0x1 << 0) /* Video Mode Selection */ -#define AT91C_VDEC_SEL_OFF (0 << 0) -#define AT91C_VDEC_SEL_ON (1 << 0) +#define AT91_MATRIX_M0PR_SHIFT 0 +#define AT91_MATRIX_M1PR_SHIFT 4 +#define AT91_MATRIX_M2PR_SHIFT 8 +#define AT91_MATRIX_M3PR_SHIFT 12 +#define AT91_MATRIX_M4PR_SHIFT 16 +#define AT91_MATRIX_M5PR_SHIFT 20 +#define AT91_MATRIX_M6PR_SHIFT 24 +#define AT91_MATRIX_M7PR_SHIFT 28 -#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x128) /* EBI Chip Select Assignment Register */ -#define AT91_MATRIX_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */ -#define AT91_MATRIX_EBI_CS1A_SMC (0 << 1) -#define AT91_MATRIX_EBI_CS1A_SDRAMC (1 << 1) -#define AT91_MATRIX_EBI_CS3A (1 << 3) /* Chip Select 3 Assignment */ -#define AT91_MATRIX_EBI_CS3A_SMC (0 << 3) -#define AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA (1 << 3) -#define AT91_MATRIX_EBI_CS4A (1 << 4) /* Chip Select 4 Assignment */ -#define AT91_MATRIX_EBI_CS4A_SMC (0 << 4) -#define AT91_MATRIX_EBI_CS4A_SMC_CF0 (1 << 4) -#define AT91_MATRIX_EBI_CS5A (1 << 5) /* Chip Select 5 Assignment */ -#define AT91_MATRIX_EBI_CS5A_SMC (0 << 5) -#define AT91_MATRIX_EBI_CS5A_SMC_CF1 (1 << 5) -#define AT91_MATRIX_EBI_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ -#define AT91_MATRIX_EBI_DBPU_ON (0 << 8) -#define AT91_MATRIX_EBI_DBPU_OFF (1 << 8) -#define AT91_MATRIX_EBI_VDDIOMSEL (1 << 16) /* Memory voltage selection */ -#define AT91_MATRIX_EBI_VDDIOMSEL_1_8V (0 << 16) -#define AT91_MATRIX_EBI_VDDIOMSEL_3_3V (1 << 16) -#define AT91_MATRIX_EBI_EBI_IOSR (1 << 17) /* EBI I/O slew rate selection */ -#define AT91_MATRIX_EBI_EBI_IOSR_REDUCED (0 << 17) -#define AT91_MATRIX_EBI_EBI_IOSR_NORMAL (1 << 17) -#define AT91_MATRIX_EBI_DDR_IOSR (1 << 18) /* DDR2 dedicated port I/O slew rate selection */ -#define AT91_MATRIX_EBI_DDR_IOSR_REDUCED (0 << 18) -#define AT91_MATRIX_EBI_DDR_IOSR_NORMAL (1 << 18) +#define AT91_MATRIX_M8PR_SHIFT 0 /* register B */ +#define AT91_MATRIX_M9PR_SHIFT 4 /* register B */ +#define AT91_MATRIX_M10PR_SHIFT 8 /* register B */ +#define AT91_MATRIX_M11PR_SHIFT 12 /* register B */ -#define AT91_MATRIX_WPMR (AT91_MATRIX + 0x1E4) /* Write Protect Mode Register */ -#define AT91_MATRIX_WPMR_WPEN (1 << 0) /* Write Protect ENable */ -#define AT91_MATRIX_WPMR_WP_WPDIS (0 << 0) -#define AT91_MATRIX_WPMR_WP_WPEN (1 << 0) -#define AT91_MATRIX_WPMR_WPKEY (0xFFFFFF << 8) /* Write Protect KEY */ +#define AT91_MATRIX_RCB0 (1 << 0) +#define AT91_MATRIX_RCB1 (1 << 1) +#define AT91_MATRIX_RCB2 (1 << 2) +#define AT91_MATRIX_RCB3 (1 << 3) +#define AT91_MATRIX_RCB4 (1 << 4) +#define AT91_MATRIX_RCB5 (1 << 5) +#define AT91_MATRIX_RCB6 (1 << 6) +#define AT91_MATRIX_RCB7 (1 << 7) +#define AT91_MATRIX_RCB8 (1 << 8) +#define AT91_MATRIX_RCB9 (1 << 9) +#define AT91_MATRIX_RCB10 (1 << 10) -#define AT91_MATRIX_WPSR (AT91_MATRIX + 0x1E8) /* Write Protect Status Register */ -#define AT91_MATRIX_WPSR_WPVS (1 << 0) /* Write Protect Violation Status */ -#define AT91_MATRIX_WPSR_NO_WPV (0 << 0) -#define AT91_MATRIX_WPSR_WPV (1 << 0) -#define AT91_MATRIX_WPSR_WPVSRC (0xFFFF << 8) /* Write Protect Violation Source */ +#define AT91_MATRIX_EBI_CS1A_SMC (0 << 1) +#define AT91_MATRIX_EBI_CS1A_SDRAMC (1 << 1) +#define AT91_MATRIX_EBI_CS3A_SMC (0 << 3) +#define AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA (1 << 3) +#define AT91_MATRIX_EBI_CS4A_SMC (0 << 4) +#define AT91_MATRIX_EBI_CS4A_SMC_CF0 (1 << 4) +#define AT91_MATRIX_EBI_CS5A_SMC (0 << 5) +#define AT91_MATRIX_EBI_CS5A_SMC_CF1 (1 << 5) +#define AT91_MATRIX_EBI_DBPU_ON (0 << 8) +#define AT91_MATRIX_EBI_DBPU_OFF (1 << 8) +#define AT91_MATRIX_EBI_VDDIOMSEL_1_8V (0 << 16) +#define AT91_MATRIX_EBI_VDDIOMSEL_3_3V (1 << 16) +#define AT91_MATRIX_EBI_EBI_IOSR_REDUCED (0 << 17) +#define AT91_MATRIX_EBI_EBI_IOSR_NORMAL (1 << 17) +#define AT91_MATRIX_EBI_DDR_IOSR_REDUCED (0 << 18) +#define AT91_MATRIX_EBI_DDR_IOSR_NORMAL (1 << 18) #endif -- 1.7.4.1 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* [U-Boot] [PATCH 1/2] atmel: update at91sam9m10g45 SoC support to new style 2011-08-04 18:53 ` [U-Boot] [PATCH 1/2] atmel: update at91sam9m10g45 SoC support to new style Thomas Petazzoni @ 2011-08-04 20:17 ` Reinhard Meyer 0 siblings, 0 replies; 8+ messages in thread From: Reinhard Meyer @ 2011-08-04 20:17 UTC (permalink / raw) To: u-boot Dear Thomas Petazzoni, > Based on earlier work by Alex Waterman <awaterman@dawning.com>. > > Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> > --- > .../cpu/arm926ejs/at91/at91sam9m10g45_devices.c | 114 ++++++------ > arch/arm/include/asm/arch-at91/at91sam9g45.h | 12 ++ > .../arm/include/asm/arch-at91/at91sam9g45_matrix.h | 194 +++++++------------- > 3 files changed, 135 insertions(+), 185 deletions(-) > Applied to u-boot-atmel/master, Thanks, Reinhard ^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2011-08-04 20:17 UTC | newest] Thread overview: 8+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2011-08-04 10:10 [U-Boot] Update at91sam9m10g45 SoC and AT91SAM9M10G45-EK board to new style Thomas Petazzoni 2011-08-04 10:10 ` [U-Boot] [PATCH 1/2] atmel: update at91sam9m10g45 SoC support " Thomas Petazzoni 2011-08-04 13:59 ` Reinhard Meyer 2011-08-04 18:54 ` Thomas Petazzoni 2011-08-04 10:10 ` [U-Boot] [PATCH 2/2] atmel: Update support of board AT91SAM9M10G45-EK " Thomas Petazzoni 2011-08-04 14:09 ` Reinhard Meyer -- strict thread matches above, loose matches on Subject: below -- 2011-08-04 18:53 [U-Boot] (no subject) Thomas Petazzoni 2011-08-04 18:53 ` [U-Boot] [PATCH 1/2] atmel: update at91sam9m10g45 SoC support to new style Thomas Petazzoni 2011-08-04 20:17 ` Reinhard Meyer
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