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From: Aneesh V <aneesh@ti.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH v3 4/4] armv7: cache: remove flush on un-aligned invalidate
Date: Thu, 11 Aug 2011 20:05:45 +0530	[thread overview]
Message-ID: <1313073345-29773-5-git-send-email-aneesh@ti.com> (raw)
In-Reply-To: <1312197486-31712-2-git-send-email-aneesh@ti.com>

Remove the flush of boundary cache-lines done as part
of invalidate on a non cache-line boundary aligned
buffer

Also, print a warning when this situation is recognized.

Signed-off-by: Aneesh V <aneesh@ti.com>
---
V2:
* New in V2
V3:
* error notification instead of warning on un-aligned invalidate
---
 arch/arm/cpu/armv7/cache_v7.c |   14 ++++++++------
 arch/arm/lib/cache-pl310.c    |   15 +++++++++------
 2 files changed, 17 insertions(+), 12 deletions(-)

diff --git a/arch/arm/cpu/armv7/cache_v7.c b/arch/arm/cpu/armv7/cache_v7.c
index 665f025..1b4e808 100644
--- a/arch/arm/cpu/armv7/cache_v7.c
+++ b/arch/arm/cpu/armv7/cache_v7.c
@@ -181,21 +181,23 @@ static void v7_dcache_inval_range(u32 start, u32 stop, u32 line_len)
 	u32 mva;
 
 	/*
-	 * If start address is not aligned to cache-line flush the first
-	 * line to prevent affecting somebody else's buffer
+	 * If start address is not aligned to cache-line do not
+	 * invalidate the first cache-line
 	 */
 	if (start & (line_len - 1)) {
-		v7_dcache_clean_inval_range(start, start + 1, line_len);
+		printf("ERROR: %s - start address is not aligned - 0x%08x\n",
+			__func__, start);
 		/* move to next cache line */
 		start = (start + line_len - 1) & ~(line_len - 1);
 	}
 
 	/*
-	 * If stop address is not aligned to cache-line flush the last
-	 * line to prevent affecting somebody else's buffer
+	 * If stop address is not aligned to cache-line do not
+	 * invalidate the last cache-line
 	 */
 	if (stop & (line_len - 1)) {
-		v7_dcache_clean_inval_range(stop, stop + 1, line_len);
+		printf("ERROR: %s - stop address is not aligned - 0x%08x\n",
+			__func__, stop);
 		/* align to the beginning of this cache line */
 		stop &= ~(line_len - 1);
 	}
diff --git a/arch/arm/lib/cache-pl310.c b/arch/arm/lib/cache-pl310.c
index 36c629c..21d13f7 100644
--- a/arch/arm/lib/cache-pl310.c
+++ b/arch/arm/lib/cache-pl310.c
@@ -26,6 +26,7 @@
 #include <asm/armv7.h>
 #include <asm/pl310.h>
 #include <config.h>
+#include <common.h>
 
 struct pl310_regs *const pl310 = (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
 
@@ -89,21 +90,23 @@ void v7_outer_cache_inval_range(u32 start, u32 stop)
 	u32 pa, line_size = 32;
 
 	/*
-	 * If start address is not aligned to cache-line flush the first
-	 * line to prevent affecting somebody else's buffer
+	 * If start address is not aligned to cache-line do not
+	 * invalidate the first cache-line
 	 */
 	if (start & (line_size - 1)) {
-		v7_outer_cache_flush_range(start, start + 1);
+		printf("ERROR: %s - start address is not aligned - 0x%08x\n",
+			__func__, start);
 		/* move to next cache line */
 		start = (start + line_size - 1) & ~(line_size - 1);
 	}
 
 	/*
-	 * If stop address is not aligned to cache-line flush the last
-	 * line to prevent affecting somebody else's buffer
+	 * If stop address is not aligned to cache-line do not
+	 * invalidate the last cache-line
 	 */
 	if (stop & (line_size - 1)) {
-		v7_outer_cache_flush_range(stop, stop + 1);
+		printf("ERROR: %s - stop address is not aligned - 0x%08x\n",
+			__func__, stop);
 		/* align to the beginning of this cache line */
 		stop &= ~(line_size - 1);
 	}
-- 
1.7.0.4

  parent reply	other threads:[~2011-08-11 14:35 UTC|newest]

Thread overview: 48+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2011-08-01 11:18 [U-Boot] [PATCH v 0/3] arm: changes in cache handling Aneesh V
2011-08-01 11:18 ` [U-Boot] [PATCH v 1/3] arm: do not force d-cache enable on all boards Aneesh V
2011-08-01 16:33   ` Jason Liu
2011-08-01 16:46     ` Jason Liu
2011-08-01 19:45       ` Wolfgang Denk
2011-08-01 19:53     ` Albert ARIBAUD
2011-08-02 14:35       ` Jason Liu
2011-08-02 15:58         ` Albert ARIBAUD
2011-08-05 15:07   ` Aneesh V
2011-08-07  6:20     ` Albert ARIBAUD
2011-08-09 11:10   ` [U-Boot] [PATCH 0/4] arm: changes in cache handling Aneesh V
2011-08-09 11:25     ` Aneesh V
2011-08-09 11:10   ` [U-Boot] [PATCH 1/4] arm: do not force d-cache enable on all boards Aneesh V
2011-08-09 11:10   ` [U-Boot] [PATCH 2/4] omap: enable caches at system start-up Aneesh V
2011-08-09 11:10   ` [U-Boot] [PATCH 3/4] armv7: stronger barrier for cache-maintenance operations Aneesh V
2011-08-09 11:10   ` [U-Boot] [PATCH 4/4] armv7: cache: remove flush on un-aligned invalidate Aneesh V
2011-08-09 16:39     ` Anton Staaf
2011-08-10  6:29       ` Albert ARIBAUD
2011-08-10  6:48       ` Aneesh V
2011-08-10 18:11         ` Anton Staaf
2011-08-11  6:29           ` Aneesh V
2011-08-09 11:34   ` [U-Boot] [PATCH v2 0/4] arm: changes in cache handling Aneesh V
2011-08-09 11:34   ` [U-Boot] [PATCH v2 1/4] arm: do not force d-cache enable on all boards Aneesh V
2011-08-09 14:41     ` [U-Boot] d-cache enable Lukasz Majewski
2011-08-12 10:59       ` Aneesh V
2011-08-12 11:41         ` Lukasz Majewski
2011-08-12 12:16           ` Aneesh V
2011-08-12 12:21           ` Albert ARIBAUD
2011-08-12 12:32             ` Reinhard Meyer
2011-08-12 12:36               ` Albert ARIBAUD
2011-08-12 13:08             ` Lukasz Majewski
2011-08-12 13:19               ` Albert ARIBAUD
2011-08-09 11:34   ` [U-Boot] [PATCH v2 2/4] omap: enable caches at system start-up Aneesh V
2011-08-09 11:34   ` [U-Boot] [PATCH v2 3/4] armv7: stronger barrier for cache-maintenance operations Aneesh V
2011-08-09 11:34   ` [U-Boot] [PATCH v2 4/4] armv7: cache: remove flush on un-aligned invalidate Aneesh V
2011-08-11 14:35   ` [U-Boot] [PATCH v3 0/4] arm: changes in cache handling Aneesh V
2011-08-13 10:09     ` Albert ARIBAUD
2011-08-15  7:40       ` V, Aneesh
2011-08-11 14:35   ` [U-Boot] [PATCH v3 1/4] arm: do not force d-cache enable on all boards Aneesh V
2011-08-14 11:09     ` Simon Guinot
2011-08-15  7:34       ` V, Aneesh
2011-08-16 14:33     ` [U-Boot] [PATCH v4 " Aneesh V
2011-08-11 14:35   ` [U-Boot] [PATCH v3 2/4] omap: enable caches at system start-up Aneesh V
2011-08-11 14:35   ` [U-Boot] [PATCH v3 3/4] armv7: stronger barrier for cache-maintenance operations Aneesh V
2011-08-11 14:35   ` Aneesh V [this message]
2011-08-01 11:18 ` [U-Boot] [PATCH v 2/3] omap: enable caches at system start-up Aneesh V
2011-08-01 11:18 ` [U-Boot] [PATCH v 3/3] armv7: stronger barrier for cache-maintenance operations Aneesh V
2011-08-05 10:29 ` [U-Boot] [PATCH v 0/3] arm: changes in cache handling Aneesh V

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