From mboxrd@z Thu Jan 1 00:00:00 1970 From: =?utf-8?Q?Beno=C3=AEt_Th=C3=A9baudeau?= Date: Mon, 18 Feb 2013 21:16:34 +0100 (CET) Subject: [U-Boot] [PATCH v7 13/19] Makefile: u-boot-with-spl.bin: Fix SPL padding In-Reply-To: <1361217990.14186.21@snotra> References: <1361216249.14186.19@snotra> <1651663875.1556800.1361217130492.JavaMail.root@advansee.com> <1361216848.14186.20@snotra> <1706943354.1556877.1361217719655.JavaMail.root@advansee.com> <1361217990.14186.21@snotra> Message-ID: <1322952300.1556921.1361218594823.JavaMail.root@advansee.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On Monday, February 18, 2013 9:06:30 PM, Scott Wood wrote: > On 02/18/2013 02:01:59 PM, Beno?t Th?baudeau wrote: > > On Monday, February 18, 2013 8:47:28 PM, Scott Wood wrote: > > > On 02/18/2013 01:52:10 PM, Beno?t Th?baudeau wrote: > > > > On Monday, February 18, 2013 8:37:29 PM, Scott Wood wrote: > > > > > On 02/17/2013 10:16:49 AM, Beno?t Th?baudeau wrote: > > > > > > all the more none of the > > > > > > various values defined for CONFIG_SYS_TEXT_BASE relatively to > > > > > > CONFIG_SPL_TEXT_BASE would be compatible with an image built > > by > > > > > > appending U-Boot > > > > > > to the generic SPL. Can you confirm? > > > > > > > > > > I don't follow. CONFIG_SYS_TEXT_BASE is for where the payload > > gets > > > > > loaded to, and has nothing to do with its position in the > > SPL-concat > > > > > image, nor with the address that the SPL starts running at. > > > > > > > > Right, sorry, I meant CONFIG_SYS_NAND_U_BOOT_OFFS. It is 0, which > > is > > > > not > > > > compatible with the payload being appended to the SPL in the > > > > programmed image. > > > > > > That just means we load the whole thing, including SPL, so that > > we're > > > always loading from the start of the block. Note the difference > > > between CONFIG_SYS_NAND_U_BOOT_DST and CONFIG_SYS_NAND_U_BOOT_START. > > > > OK. Hmm, this difference is CONFIG_SPL_MAX_SIZE, but > > CONFIG_SPL_PAD_TO is not > > defined, so the payload is right after the SPL in the image and the > > SPL jumps to > > somewhere in the middle of the payload? > > It jumps to the beginning of the payload. As mentioned elsewhere in > the thread, mpc85xx NAND SPL is always fixed size (done in the linker > script) because the reset vector comes at the end. Thus, max size > equals actual size without needing --pad-to. OK, clear. Beno?t