[U-Boot] [PATCH] mx31: Setup AIPS registers

[Fabio Estevam <festevam@gmail.com>]

Setup mx31 AIPS registers.

It was verified on a mx31pdk that without the AIPS settings it is not possible
to run audio playback.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
---
 arch/arm/cpu/arm1136/mx31/generic.c       |   40 +++++++++++++++++++++++++++++
 arch/arm/include/asm/arch-mx31/imx-regs.h |   13 +++++++++
 2 files changed, 53 insertions(+), 0 deletions(-)

diff --git a/arch/arm/cpu/arm1136/mx31/generic.c b/arch/arm/cpu/arm1136/mx31/generic.c
index d60afc9..cc2e3d5 100644
--- a/arch/arm/cpu/arm1136/mx31/generic.c
+++ b/arch/arm/cpu/arm1136/mx31/generic.c
@@ -228,3 +228,43 @@ int print_cpuinfo(void)
 	return 0;
 }
 #endif
+
+void init_aips(void)
+{
+	struct aipstz_regs *aips1, *aips2;
+
+	aips1 = (struct aipstz_regs *)MX31_AIPS1_BASE_ADDR;
+	aips2 = (struct aipstz_regs *)MX31_AIPS2_BASE_ADDR;
+
+	/*
+	 * Set all MPROTx to be non-bufferable, trusted for R/W,
+	 * not forced to user-mode.
+	 */
+	writel(0x77777777, &aips1->mprot0);
+	writel(0x77777777, &aips1->mprot1);
+	writel(0x77777777, &aips2->mprot0);
+	writel(0x77777777, &aips2->mprot1);
+
+	/*
+	 * Set all OPACRx to be non-bufferable, not require
+	 * supervisor privilege level for access,allow for
+	 * write access and untrusted master access.
+	 */
+	writel(0x00000000, &aips1->opacr0);
+	writel(0x00000000, &aips1->opacr1);
+	writel(0x00000000, &aips1->opacr2);
+	writel(0x00000000, &aips1->opacr3);
+	writel(0x00000000, &aips1->opacr4);
+	writel(0x00000000, &aips2->opacr0);
+	writel(0x00000000, &aips2->opacr1);
+	writel(0x00000000, &aips2->opacr2);
+	writel(0x00000000, &aips2->opacr3);
+	writel(0x00000000, &aips2->opacr4);
+}
+
+int arch_cpu_init(void)
+{
+	init_aips();
+
+	return 0;
+}
diff --git a/arch/arm/include/asm/arch-mx31/imx-regs.h b/arch/arm/include/asm/arch-mx31/imx-regs.h
index 6454acb..11069af 100644
--- a/arch/arm/include/asm/arch-mx31/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx31/imx-regs.h
@@ -539,6 +539,18 @@ struct esdc_regs {
 	u32 dlyl;
 };
 
+/* AIPS registers */
+struct aipstz_regs {
+	u32	mprot0;
+	u32	mprot1;
+	u32	rsvd[0xe];
+	u32	opacr0;
+	u32	opacr1;
+	u32	opacr2;
+	u32	opacr3;
+	u32	opacr4;
+};
+
 #endif
 
 #define __REG(x)     (*((volatile u32 *)(x)))
@@ -873,6 +885,7 @@ struct esdc_regs {
 #define IRAM_SIZE	(16 * 1024)
 
 #define MX31_AIPS1_BASE_ADDR	0x43f00000
+#define MX31_AIPS2_BASE_ADDR	0x53f00000
 #define IMX_USB_BASE		(MX31_AIPS1_BASE_ADDR + 0x88000)
 
 /* USB portsc */
-- 
1.7.1