From mboxrd@z Thu Jan 1 00:00:00 1970 From: R Sricharan Date: Thu, 1 Mar 2012 20:08:33 +0530 Subject: [U-Boot] [PATCH V2 08/18] OMAP5: SRAM: Change the SRAM base address. In-Reply-To: <1330612723-11328-1-git-send-email-r.sricharan@ti.com> References: <1330612723-11328-1-git-send-email-r.sricharan@ti.com> Message-ID: <1330612723-11328-9-git-send-email-r.sricharan@ti.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de The full internal SRAM of size 128kb is public in the case of OMAP5 soc. So change the base address accordingly. Signed-off-by: R Sricharan --- arch/arm/include/asm/arch-omap5/omap.h | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h index 07546c9..10a973c 100644 --- a/arch/arm/include/asm/arch-omap5/omap.h +++ b/arch/arm/include/asm/arch-omap5/omap.h @@ -249,7 +249,7 @@ struct omap5_sys_ctrl_regs { * Non-secure RAM starts at 0x40300000 for GP devices. But we keep SRAM_BASE * at 0x40304000(EMU base) so that our code works for both EMU and GP */ -#define NON_SECURE_SRAM_START 0x40304000 +#define NON_SECURE_SRAM_START 0x40300000 #define NON_SECURE_SRAM_END 0x40320000 /* Not inclusive */ /* base address for indirect vectors (internal boot mode) */ #define SRAM_ROM_VECT_BASE 0x4031F000 -- 1.7.1