[U-Boot] [PATCH] arm: enable unaligned access on ARMv7

Lucas Stach
2012-06-05T17:47:31Z

Recent toolchains default to using the hardware feature for unaligned access on
ARM v7, rather than doing the software fallback. According to ARM this is safe
as all v7 implementations have to support this feature.
(http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0471c/BABJFFAE.html)

To avoid CPU hangs when doing unaligned memory access, we have to turn off
alignment checking in our CPU initialisation code.
(http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0491c/CIHCGCFD.html)

Signed-off-by: Lucas Stach <dev@lynxeye.de>
CC: Albert ARIBAUD <albert.u.boot@aribaud.net>
---
arch/arm/cpu/armv7/start.S | 2 +-
1 Datei ge?ndert, 1 Zeile hinzugef?gt(+), 1 Zeile entfernt(-)

diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index 261835b..52f7f6e 100644
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -316,7 +316,7 @@ ENTRY(cpu_init_cp15)
mrc p15, 0, r0, c1, c0, 0
bic r0, r0, #0x00002000 @ clear bits 13 (--V-)
bic r0, r0, #0x00000007 @ clear bits 2:0 (-CAM)
- orr r0, r0, #0x00000002 @ set bit 1 (--A-) Align
+ bic r0, r0, #0x00000002 @ clear bit 1 (--A-) Align
orr r0, r0, #0x00000800 @ set bit 11 (Z---) BTB
#ifdef CONFIG_SYS_ICACHE_OFF
bic r0, r0, #0x00001000 @ clear bit 12 (I) I-cache
--
1.7.10.2