From mboxrd@z Thu Jan 1 00:00:00 1970 From: =?utf-8?Q?Beno=C3=AEt_Th=C3=A9baudeau?= Date: Tue, 14 Aug 2012 22:33:06 +0200 (CEST) Subject: [U-Boot] [PATCH 4/7] mx35: Add definitions for clock gate values In-Reply-To: <2048761165.2411430.1344976340969.JavaMail.root@advansee.com> Message-ID: <1343120129.2411443.1344976386905.JavaMail.root@advansee.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Signed-off-by: Beno?t Th?baudeau Cc: Stefano Babic --- .../arch/arm/include/asm/arch-mx35/crm_regs.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git u-boot-4d3c95f.orig/arch/arm/include/asm/arch-mx35/crm_regs.h u-boot-4d3c95f/arch/arm/include/asm/arch-mx35/crm_regs.h index e903cf1..66bc1ba 100644 --- u-boot-4d3c95f.orig/arch/arm/include/asm/arch-mx35/crm_regs.h +++ u-boot-4d3c95f/arch/arm/include/asm/arch-mx35/crm_regs.h @@ -144,6 +144,12 @@ #define MXC_CCM_ACMR_SSI2_CLK_SEL_MASK (0xF << 0) /* Bit definitions for Clock gating Register*/ +#define MXC_CCM_CGR_CG_MASK 0x3 +#define MXC_CCM_CGR_CG_OFF 0x0 +#define MXC_CCM_CGR_CG_RUN_ON 0x1 +#define MXC_CCM_CGR_CG_RUN_WAIT_ON 0x2 +#define MXC_CCM_CGR_CG_ON 0x3 + #define MXC_CCM_CGR0_ASRC_OFFSET 0 #define MXC_CCM_CGR0_ASRC_MASK (0x3 << 0) #define MXC_CCM_CGR0_ATA_OFFSET 2