* [U-Boot] [PATCH v2 01/22] serial/ns16550: don't build serial_ns16550 with MIN_FUNCTIONS
2012-10-30 2:04 ` [U-Boot] [PATCH v2 00/22] " Scott Wood
@ 2012-10-30 2:04 ` Scott Wood
2012-10-30 2:04 ` [U-Boot] [PATCH v2 02/22] serial/ns16550: wait for TEMT before initializing Scott Wood
` (21 subsequent siblings)
22 siblings, 0 replies; 81+ messages in thread
From: Scott Wood @ 2012-10-30 2:04 UTC (permalink / raw)
To: u-boot
CONFIG_NS16550_MIN_FUNCTIONS is used by small SPLs to gain access to basic
ns16550 output code without pulling in things not needed by the SPL.
This previously only worked with non-MULTI configs. Recently MULTI was
made mandatory, and MIN_FUNCTIONS fails like this:
drivers/serial/libserial.o: In function `calc_divisor.clone.0':
serial_ns16550.c:(.text.calc_divisor.clone.0+0x24): undefined reference to `get_bus_freq'
drivers/serial/libserial.o: In function `_serial_getc':
(.text._serial_getc+0x30): undefined reference to `NS16550_getc'
drivers/serial/libserial.o: In function `_serial_tstc':
(.text._serial_tstc+0x30): undefined reference to `NS16550_tstc'
drivers/serial/libserial.o: In function `_serial_setbrg':
(.text._serial_setbrg+0x3c): undefined reference to `NS16550_reinit'
make[1]: *** [/tmp/u-boot/spl/u-boot-spl] Error 1
make: *** [/tmp/u-boot/spl/u-boot-spl.bin] Error 2
With MIN_FUNCTIONS we don't need anything from this file, so don't build
it. The conditional needs to be in the file itself rather than the
makefile, because the config symbols are only imported to the makefiles
once, not separately for the SPL phase of the build.
Signed-off-by: Scott Wood <scottwood@freescale.com>
---
drivers/serial/serial_ns16550.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/serial/serial_ns16550.c b/drivers/serial/serial_ns16550.c
index 4176e25..6e374f2 100644
--- a/drivers/serial/serial_ns16550.c
+++ b/drivers/serial/serial_ns16550.c
@@ -31,6 +31,8 @@
#include <serial.h>
+#ifndef CONFIG_NS16550_MIN_FUNCTIONS
+
DECLARE_GLOBAL_DATA_PTR;
#if !defined(CONFIG_CONS_INDEX)
@@ -262,3 +264,5 @@ void ns16550_serial_initialize(void)
serial_register(&eserial4_device);
#endif
}
+
+#endif /* !CONFIG_NS16550_MIN_FUNCTIONS */
--
1.7.9.5
^ permalink raw reply related [flat|nested] 81+ messages in thread* [U-Boot] [PATCH v2 02/22] serial/ns16550: wait for TEMT before initializing
2012-10-30 2:04 ` [U-Boot] [PATCH v2 00/22] " Scott Wood
2012-10-30 2:04 ` [U-Boot] [PATCH v2 01/22] serial/ns16550: don't build serial_ns16550 with MIN_FUNCTIONS Scott Wood
@ 2012-10-30 2:04 ` Scott Wood
2012-10-30 2:04 ` [U-Boot] [PATCH v2 03/22] powerpc/mpc85xx: move debug tlb entry after TLB is in known state Scott Wood
` (20 subsequent siblings)
22 siblings, 0 replies; 81+ messages in thread
From: Scott Wood @ 2012-10-30 2:04 UTC (permalink / raw)
To: u-boot
TEMT is set when the transmitter is totally empty and all output has
finished.
This prevents output problems (including a loss of synchronization
observed on p2020 that persisted for quite a while) if SPL has output
still on its way out.
Signed-off-by: Scott Wood <scottwood@freescale.com>
--
v2: fixed typo in subject, and explained what the bit does in the changelog
---
drivers/serial/ns16550.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
index 9027781..bbd91ca 100644
--- a/drivers/serial/ns16550.c
+++ b/drivers/serial/ns16550.c
@@ -36,6 +36,9 @@
void NS16550_init(NS16550_t com_port, int baud_divisor)
{
+ while (!(serial_in(&com_port->lsr) & UART_LSR_TEMT))
+ ;
+
serial_out(CONFIG_SYS_NS16550_IER, &com_port->ier);
#if (defined(CONFIG_OMAP) && !defined(CONFIG_OMAP3_ZOOM2)) || \
defined(CONFIG_AM33XX)
--
1.7.9.5
^ permalink raw reply related [flat|nested] 81+ messages in thread* [U-Boot] [PATCH v2 03/22] powerpc/mpc85xx: move debug tlb entry after TLB is in known state
2012-10-30 2:04 ` [U-Boot] [PATCH v2 00/22] " Scott Wood
2012-10-30 2:04 ` [U-Boot] [PATCH v2 01/22] serial/ns16550: don't build serial_ns16550 with MIN_FUNCTIONS Scott Wood
2012-10-30 2:04 ` [U-Boot] [PATCH v2 02/22] serial/ns16550: wait for TEMT before initializing Scott Wood
@ 2012-10-30 2:04 ` Scott Wood
2012-10-30 9:26 ` Prabhakar Kushwaha
` (2 more replies)
2012-10-30 2:04 ` [U-Boot] [PATCH v2 04/22] powerpc/mpc85xx: add comma before "already enabled" Scott Wood
` (19 subsequent siblings)
22 siblings, 3 replies; 81+ messages in thread
From: Scott Wood @ 2012-10-30 2:04 UTC (permalink / raw)
To: u-boot
Previously, in many if not all configs we were creating overlapping TLB entries
which is illegal. This caused a crash during boot when moving p2020rdb NAND SPL
into L2 SRAM.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Cc: Prabhakar Kushwaha <prabhakar@freescale.com>
Cc: Andy Fleming <afleming@freescale.com>
--
Prabhakar, please test that debug still works.
---
arch/powerpc/cpu/mpc85xx/start.S | 84 ++++++++++++++++++--------------------
1 file changed, 40 insertions(+), 44 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index ac17f9d..7912a4b 100644
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -282,46 +282,6 @@ l2_disabled:
isync
.endm
-#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(CONFIG_NAND_SPL)
-/*
- * TLB entry for debuggging in AS1
- * Create temporary TLB entry in AS0 to handle debug exception
- * As on debug exception MSR is cleared i.e. Address space is changed
- * to 0. A TLB entry (in AS0) is required to handle debug exception generated
- * in AS1.
- */
-
-#if !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SECURE_BOOT)
-/*
- * TLB entry is created for IVPR + IVOR15 to map on valid OP code address
- * bacause flash's virtual address maps to 0xff800000 - 0xffffffff.
- * and this window is outside of 4K boot window.
- */
- create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \
- 0, BOOKE_PAGESZ_4M, \
- CONFIG_SYS_MONITOR_BASE & 0xffc00000, MAS2_I|MAS2_G, \
- 0xffc00000, MAS3_SX|MAS3_SW|MAS3_SR, \
- 0, r6
-
-#elif !defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT)
- create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \
- 0, BOOKE_PAGESZ_1M, \
- CONFIG_SYS_MONITOR_BASE, MAS2_I|MAS2_G, \
- CONFIG_SYS_PBI_FLASH_WINDOW, MAS3_SX|MAS3_SW|MAS3_SR, \
- 0, r6
-#else
-/*
- * TLB entry is created for IVPR + IVOR15 to map on valid OP code address
- * because "nexti" will resize TLB to 4K
- */
- create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \
- 0, BOOKE_PAGESZ_256K, \
- CONFIG_SYS_MONITOR_BASE, MAS2_I, \
- CONFIG_SYS_MONITOR_BASE, MAS3_SX|MAS3_SW|MAS3_SR, \
- 0, r6
-#endif
-#endif
-
/*
* Ne need to setup interrupt vector for NAND SPL
* because NAND SPL never compiles it.
@@ -534,10 +494,6 @@ nexti: mflr r1 /* R1 = our PC */
li r3, 0
mtspr MAS1, r3
1: cmpw r3, r14
-#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(CONFIG_NAND_SPL)
- cmpwi cr1, r3, CONFIG_SYS_PPC_E500_DEBUG_TLB
- cror cr0*4+eq, cr0*4+eq, cr1*4+eq
-#endif
rlwinm r5, r3, 16, MAS0_ESEL_MSK
addi r3, r3, 1
beq 2f /* skip the entry we're executing from */
@@ -553,6 +509,46 @@ nexti: mflr r1 /* R1 = our PC */
2: cmpw r3, r4
blt 1b
+#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(MINIMAL_SPL)
+/*
+ * TLB entry for debuggging in AS1
+ * Create temporary TLB entry in AS0 to handle debug exception
+ * As on debug exception MSR is cleared i.e. Address space is changed
+ * to 0. A TLB entry (in AS0) is required to handle debug exception generated
+ * in AS1.
+ */
+
+#if !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SECURE_BOOT)
+/*
+ * TLB entry is created for IVPR + IVOR15 to map on valid OP code address
+ * bacause flash's virtual address maps to 0xff800000 - 0xffffffff.
+ * and this window is outside of 4K boot window.
+ */
+ create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \
+ 0, BOOKE_PAGESZ_4M, \
+ CONFIG_SYS_MONITOR_BASE & 0xffc00000, MAS2_I|MAS2_G, \
+ 0xffc00000, MAS3_SX|MAS3_SW|MAS3_SR, \
+ 0, r6
+
+#elif !defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT)
+ create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \
+ 0, BOOKE_PAGESZ_1M, \
+ CONFIG_SYS_MONITOR_BASE, MAS2_I|MAS2_G, \
+ CONFIG_SYS_PBI_FLASH_WINDOW, MAS3_SX|MAS3_SW|MAS3_SR, \
+ 0, r6
+#else
+/*
+ * TLB entry is created for IVPR + IVOR15 to map on valid OP code address
+ * because "nexti" will resize TLB to 4K
+ */
+ create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \
+ 0, BOOKE_PAGESZ_256K, \
+ CONFIG_SYS_MONITOR_BASE & 0xfffc0000, MAS2_I, \
+ CONFIG_SYS_MONITOR_BASE & 0xfffc0000, MAS3_SX|MAS3_SW|MAS3_SR, \
+ 0, r6
+#endif
+#endif
+
/*
* Relocate CCSR, if necessary. We relocate CCSR if (obviously) the default
* location is not where we want it. This typically happens on a 36-bit
--
1.7.9.5
^ permalink raw reply related [flat|nested] 81+ messages in thread* [U-Boot] [PATCH v2 03/22] powerpc/mpc85xx: move debug tlb entry after TLB is in known state
2012-10-30 2:04 ` [U-Boot] [PATCH v2 03/22] powerpc/mpc85xx: move debug tlb entry after TLB is in known state Scott Wood
@ 2012-10-30 9:26 ` Prabhakar Kushwaha
2012-10-30 21:07 ` Scott Wood
2012-11-16 2:12 ` Scott Wood
2012-11-26 20:53 ` Andy Fleming
2 siblings, 1 reply; 81+ messages in thread
From: Prabhakar Kushwaha @ 2012-10-30 9:26 UTC (permalink / raw)
To: u-boot
On 10/30/2012 07:34 AM, Scott Wood wrote:
> Previously, in many if not all configs we were creating overlapping TLB entries
> which is illegal. This caused a crash during boot when moving p2020rdb NAND SPL
> into L2 SRAM.
>
> Signed-off-by: Scott Wood <scottwood@freescale.com>
> Cc: Prabhakar Kushwaha <prabhakar@freescale.com>
> Cc: Andy Fleming <afleming@freescale.com>
> --
> Prabhakar, please test that debug still works.
>
During RAMBOOT, both "temporary debug TLB entry" and "execution TLB
entry" is same. So moving "temporary debug TLB entry" creation after
"execution TLB entry resizing" will make sure of debugging during NAND
ramboot, SPI and SD boot.
But for NOR & NAND SPL there is a problem because boot-up TLB as
0xfffff000 and temporary debug TLB as 0xEFF80000. So we require to
create temporary TLB entry to support early debugging.
I will suggest to split the CONFIG_SYS_PPC_E500_DEBUG_TLB define into 2
parts.
1) For NOR , NAND spl debugging
2) For RAMBoot: After resizing of execution TLB
I made following changes in the patch and tested across P1010RDB for
NOR, NAND-SPL, NAND Ramboot and SPI boot debugging.
Please note I used only this patch after replacing MINIMAL_SPL with
CONFIG_NAND_SPL.
diff --git a/arch/powerpc/cpu/mpc85xx/start.S
b/arch/powerpc/cpu/mpc85xx/start.S
index ac17f9d..c00db4a 100644
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -282,7 +282,7 @@ l2_disabled:
isync
.endm
-#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(CONFIG_NAND_SPL)
+#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(MINIMAL_SPL)
/*
* TLB entry for debuggging in AS1
* Create temporary TLB entry in AS0 to handle debug exception
@@ -309,16 +309,6 @@ l2_disabled:
CONFIG_SYS_MONITOR_BASE, MAS2_I|MAS2_G, \
CONFIG_SYS_PBI_FLASH_WINDOW, MAS3_SX|MAS3_SW|MAS3_SR, \
0, r6
-#else
-/*
- * TLB entry is created for IVPR + IVOR15 to map on valid OP code address
- * because "nexti" will resize TLB to 4K
- */
- create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \
- 0, BOOKE_PAGESZ_256K, \
- CONFIG_SYS_MONITOR_BASE, MAS2_I, \
- CONFIG_SYS_MONITOR_BASE, MAS3_SX|MAS3_SW|MAS3_SR, \
- 0, r6
#endif
#endif
@@ -520,6 +510,24 @@ nexti: mflr r1 /* R1 = our PC */
msync
tlbwe
+#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(MINIMAL_SPL)\
+ && defined(CONFIG_SYS_RAMBOOT)
+/*
+ * TLB entry for debuggging in AS1
+ * Create temporary TLB entry in AS0 to handle debug exception
+ * As on debug exception MSR is cleared i.e. Address space is changed
+ * to 0. A TLB entry (in AS0) is required to handle debug exception
generated
+ * in AS1.
+ * TLB entry is created for IVPR + IVOR15 to map on valid OP code address
+ * because "nexti" has resized execution TLB entry to 4K
+ */
+ create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \
+ 0, BOOKE_PAGESZ_256K, \
+ CONFIG_SYS_MONITOR_BASE & 0xfffc0000, MAS2_I, \
+ CONFIG_SYS_MONITOR_BASE & 0xfffc0000,
MAS3_SX|MAS3_SW|MAS3_SR, \
+ 0, r6
+#endif
+
/*
* Clear out any other TLB entries that may exist, to avoid conflicts.
* Our TLB entry is in r14.
@@ -534,7 +542,7 @@ nexti: mflr r1 /* R1 = our PC */
li r3, 0
mtspr MAS1, r3
1: cmpw r3, r14
-#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(CONFIG_NAND_SPL)
+#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(MINIMAL_SPL)
cmpwi cr1, r3, CONFIG_SYS_PPC_E500_DEBUG_TLB
cror cr0*4+eq, cr0*4+eq, cr1*4+eq
#endif
Regards,
Prabhakar
^ permalink raw reply related [flat|nested] 81+ messages in thread* [U-Boot] [PATCH v2 03/22] powerpc/mpc85xx: move debug tlb entry after TLB is in known state
2012-10-30 9:26 ` Prabhakar Kushwaha
@ 2012-10-30 21:07 ` Scott Wood
2012-10-31 6:17 ` Prabhakar Kushwaha
0 siblings, 1 reply; 81+ messages in thread
From: Scott Wood @ 2012-10-30 21:07 UTC (permalink / raw)
To: u-boot
On 10/30/2012 04:26:16 AM, Prabhakar Kushwaha wrote:
> On 10/30/2012 07:34 AM, Scott Wood wrote:
>> Previously, in many if not all configs we were creating overlapping
>> TLB entries
>> which is illegal. This caused a crash during boot when moving
>> p2020rdb NAND SPL
>> into L2 SRAM.
>>
>> Signed-off-by: Scott Wood <scottwood@freescale.com>
>> Cc: Prabhakar Kushwaha <prabhakar@freescale.com>
>> Cc: Andy Fleming <afleming@freescale.com>
>> --
>> Prabhakar, please test that debug still works.
>>
>
> During RAMBOOT, both "temporary debug TLB entry" and "execution TLB
> entry" is same. So moving "temporary debug TLB entry" creation after
> "execution TLB entry resizing" will make sure of debugging during
> NAND ramboot, SPI and SD boot.
>
> But for NOR & NAND SPL there is a problem because boot-up TLB as
> 0xfffff000 and temporary debug TLB as 0xEFF80000. So we require to
> create temporary TLB entry to support early debugging.
>
> I will suggest to split the CONFIG_SYS_PPC_E500_DEBUG_TLB define into
> 2 parts.
> 1) For NOR , NAND spl debugging
> 2) For RAMBoot: After resizing of execution TLB
I'd rather not see this split this up. This file is too much of a
complicated ifdef mess already.
The window during which you won't be able to use breakpoints is not
that large. There are other debugging techniques that can be used.
Meanwhile, I wasted time debugging the problems that this extra TLB
entry caused -- and every time I try to reason about what's going on in
this file, I now have one more thing to consider (which is really
several more things due to all the different scenarios). Not exactly
the desired outcome of something meant to help debugging.
Also, we should not be creating this entry at any time during the SPL.
> I made following changes in the patch and tested across P1010RDB for
> NOR, NAND-SPL, NAND Ramboot and SPI boot debugging.
>
> Please note I used only this patch after replacing MINIMAL_SPL with
> CONFIG_NAND_SPL.
>
> diff --git a/arch/powerpc/cpu/mpc85xx/start.S
> b/arch/powerpc/cpu/mpc85xx/start.S
> index ac17f9d..c00db4a 100644
> --- a/arch/powerpc/cpu/mpc85xx/start.S
> +++ b/arch/powerpc/cpu/mpc85xx/start.S
> @@ -282,7 +282,7 @@ l2_disabled:
> isync
> .endm
>
> -#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) &&
> !defined(CONFIG_NAND_SPL)
> +#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(MINIMAL_SPL)
> /*
> * TLB entry for debuggging in AS1
> * Create temporary TLB entry in AS0 to handle debug exception
> @@ -309,16 +309,6 @@ l2_disabled:
> CONFIG_SYS_MONITOR_BASE, MAS2_I|MAS2_G, \
> CONFIG_SYS_PBI_FLASH_WINDOW, MAS3_SX|MAS3_SW|MAS3_SR,
> \
> 0, r6
> -#else
> -/*
> - * TLB entry is created for IVPR + IVOR15 to map on valid OP code
> address
> - * because "nexti" will resize TLB to 4K
> - */
> - create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \
> - 0, BOOKE_PAGESZ_256K, \
> - CONFIG_SYS_MONITOR_BASE, MAS2_I, \
> - CONFIG_SYS_MONITOR_BASE, MAS3_SX|MAS3_SW|MAS3_SR, \
> - 0, r6
> #endif
> #endif
>
> @@ -520,6 +510,24 @@ nexti: mflr r1 /* R1 = our
> PC */
> msync
> tlbwe
>
> +#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(MINIMAL_SPL)\
> + && defined(CONFIG_SYS_RAMBOOT)
Get rid of that CONFIG_SYS_RAMBOOT. We don't set it anymore for SPL as
of this patchset. And the SPL payload is precisely when I saw problems
with this!
> +/*
> + * TLB entry for debuggging in AS1
> + * Create temporary TLB entry in AS0 to handle debug exception
> + * As on debug exception MSR is cleared i.e. Address space is changed
> + * to 0. A TLB entry (in AS0) is required to handle debug exception
> generated
> + * in AS1.
> + * TLB entry is created for IVPR + IVOR15 to map on valid OP code
> address
> + * because "nexti" has resized execution TLB entry to 4K
> + */
> + create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \
> + 0, BOOKE_PAGESZ_256K, \
> + CONFIG_SYS_MONITOR_BASE & 0xfffc0000, MAS2_I, \
> + CONFIG_SYS_MONITOR_BASE & 0xfffc0000,
> MAS3_SX|MAS3_SW|MAS3_SR, \
> + 0, r6
> +#endif
> +
> /*
> * Clear out any other TLB entries that may exist, to avoid
> conflicts.
> * Our TLB entry is in r14.
You *cannot* put this entry into the TLB until we've cleared out the
unknown previous contents of the TLB.
-Scott
^ permalink raw reply [flat|nested] 81+ messages in thread
* [U-Boot] [PATCH v2 03/22] powerpc/mpc85xx: move debug tlb entry after TLB is in known state
2012-10-30 21:07 ` Scott Wood
@ 2012-10-31 6:17 ` Prabhakar Kushwaha
2012-10-31 22:08 ` Scott Wood
0 siblings, 1 reply; 81+ messages in thread
From: Prabhakar Kushwaha @ 2012-10-31 6:17 UTC (permalink / raw)
To: u-boot
On 10/31/2012 02:37 AM, Scott Wood wrote:
> On 10/30/2012 04:26:16 AM, Prabhakar Kushwaha wrote:
>> On 10/30/2012 07:34 AM, Scott Wood wrote:
>>> Previously, in many if not all configs we were creating overlapping
>>> TLB entries
>>> which is illegal. This caused a crash during boot when moving
>>> p2020rdb NAND SPL
>>> into L2 SRAM.
>>>
>>> Signed-off-by: Scott Wood <scottwood@freescale.com>
>>> Cc: Prabhakar Kushwaha <prabhakar@freescale.com>
>>> Cc: Andy Fleming <afleming@freescale.com>
>>> --
>>> Prabhakar, please test that debug still works.
>>>
>>
>> During RAMBOOT, both "temporary debug TLB entry" and "execution TLB
>> entry" is same. So moving "temporary debug TLB entry" creation after
>> "execution TLB entry resizing" will make sure of debugging during
>> NAND ramboot, SPI and SD boot.
>>
>> But for NOR & NAND SPL there is a problem because boot-up TLB as
>> 0xfffff000 and temporary debug TLB as 0xEFF80000. So we require to
>> create temporary TLB entry to support early debugging.
>>
>> I will suggest to split the CONFIG_SYS_PPC_E500_DEBUG_TLB define into
>> 2 parts.
>> 1) For NOR , NAND spl debugging
>> 2) For RAMBoot: After resizing of execution TLB
>
> I'd rather not see this split this up. This file is too much of a
> complicated ifdef mess already.
>
> The window during which you won't be able to use breakpoints is not
> that large.
> There are other debugging techniques that can be used.
Can you please share the other techniques. It will help us in future.
> Meanwhile, I wasted time debugging the problems that this extra TLB
> entry caused -- and every time I try to reason about what's going on
> in this file, I now have one more thing to consider (which is really
> several more things due to all the different scenarios). Not exactly
> the desired outcome of something meant to help debugging.
>
Debugger is present to help in these scenario for faster and effective
debugging.
My effort is to make as much as possible u-boot code to be debbug-able.
From now on, we have to take care of extra temporary debug TLB entry.
But this should not mean, no new TLB entries can be created depending
upon requirement. This TLB entry is required for debugging in AS1
execution space.
if everything is perfect, debugging is even not required. but if
something broken in AS1, debugger is best/shortest way to debug.
> Also, we should not be creating this entry at any time during the SPL.
I believe it should not be required as NAND SPL never required. But
still need to check once this framework is pushed for mpx85xx platforms
>
>> I made following changes in the patch and tested across P1010RDB for
>> NOR, NAND-SPL, NAND Ramboot and SPI boot debugging.
>>
>> Please note I used only this patch after replacing MINIMAL_SPL with
>> CONFIG_NAND_SPL.
>>
>> diff --git a/arch/powerpc/cpu/mpc85xx/start.S
>> b/arch/powerpc/cpu/mpc85xx/start.S
>> index ac17f9d..c00db4a 100644
>> --- a/arch/powerpc/cpu/mpc85xx/start.S
>> +++ b/arch/powerpc/cpu/mpc85xx/start.S
>> @@ -282,7 +282,7 @@ l2_disabled:
>> isync
>> .endm
>>
>> -#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(CONFIG_NAND_SPL)
>> +#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(MINIMAL_SPL)
>> /*
>> * TLB entry for debuggging in AS1
>> * Create temporary TLB entry in AS0 to handle debug exception
>> @@ -309,16 +309,6 @@ l2_disabled:
>> CONFIG_SYS_MONITOR_BASE, MAS2_I|MAS2_G, \
>> CONFIG_SYS_PBI_FLASH_WINDOW, MAS3_SX|MAS3_SW|MAS3_SR, \
>> 0, r6
>> -#else
>> -/*
>> - * TLB entry is created for IVPR + IVOR15 to map on valid OP code
>> address
>> - * because "nexti" will resize TLB to 4K
>> - */
>> - create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \
>> - 0, BOOKE_PAGESZ_256K, \
>> - CONFIG_SYS_MONITOR_BASE, MAS2_I, \
>> - CONFIG_SYS_MONITOR_BASE, MAS3_SX|MAS3_SW|MAS3_SR, \
>> - 0, r6
>> #endif
>> #endif
>>
>> @@ -520,6 +510,24 @@ nexti: mflr r1 /* R1 = our
>> PC */
>> msync
>> tlbwe
>>
>> +#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(MINIMAL_SPL)\
>> + && defined(CONFIG_SYS_RAMBOOT)
>
> Get rid of that CONFIG_SYS_RAMBOOT. We don't set it anymore for SPL
> as of this patchset. And the SPL payload is precisely when I saw
> problems with this!
>
I paste this just for reference. It should be updated in v2 version of
this SPL patch series.
>> +/*
>> + * TLB entry for debuggging in AS1
>> + * Create temporary TLB entry in AS0 to handle debug exception
>> + * As on debug exception MSR is cleared i.e. Address space is changed
>> + * to 0. A TLB entry (in AS0) is required to handle debug exception
>> generated
>> + * in AS1.
>> + * TLB entry is created for IVPR + IVOR15 to map on valid OP code
>> address
>> + * because "nexti" has resized execution TLB entry to 4K
>> + */
>> + create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \
>> + 0, BOOKE_PAGESZ_256K, \
>> + CONFIG_SYS_MONITOR_BASE & 0xfffc0000, MAS2_I, \
>> + CONFIG_SYS_MONITOR_BASE & 0xfffc0000,
>> MAS3_SX|MAS3_SW|MAS3_SR, \
>> + 0, r6
>> +#endif
>> +
>> /*
>> * Clear out any other TLB entries that may exist, to avoid conflicts.
>> * Our TLB entry is in r14.
>
> You *cannot* put this entry into the TLB until we've cleared out the
> unknown previous contents of the TLB.
>
OK. We can put it just after clearing TLB entries.
Regards,
Prabhakar
^ permalink raw reply [flat|nested] 81+ messages in thread
* [U-Boot] [PATCH v2 03/22] powerpc/mpc85xx: move debug tlb entry after TLB is in known state
2012-10-31 6:17 ` Prabhakar Kushwaha
@ 2012-10-31 22:08 ` Scott Wood
2012-10-31 22:44 ` McClintock Matthew-B29882
[not found] ` <CAEsOVNeZAyH1nxfgnjPYUG4=7yxjF9rjsRWrpa=WYW8edfiM3Q@mail.gmail.com>
0 siblings, 2 replies; 81+ messages in thread
From: Scott Wood @ 2012-10-31 22:08 UTC (permalink / raw)
To: u-boot
On 10/31/2012 01:17:31 AM, Prabhakar Kushwaha wrote:
> On 10/31/2012 02:37 AM, Scott Wood wrote:
>> On 10/30/2012 04:26:16 AM, Prabhakar Kushwaha wrote:
>> I'd rather not see this split this up. This file is too much of a
>> complicated ifdef mess already.
>>
>> The window during which you won't be able to use breakpoints is not
>> that large.
>> There are other debugging techniques that can be used.
>
> Can you please share the other techniques. It will help us in future.
For debugging early boot hangs I usually put a branch-to-self somewhere
in the sequence, and use CCS to see if we're spinning there or if we
went off to some exception or other badness. Then I do a binary
search, moving the branch to self around, to determine where things
went wrong.
-Scott
^ permalink raw reply [flat|nested] 81+ messages in thread* [U-Boot] [PATCH v2 03/22] powerpc/mpc85xx: move debug tlb entry after TLB is in known state
2012-10-31 22:08 ` Scott Wood
@ 2012-10-31 22:44 ` McClintock Matthew-B29882
[not found] ` <CAEsOVNeZAyH1nxfgnjPYUG4=7yxjF9rjsRWrpa=WYW8edfiM3Q@mail.gmail.com>
1 sibling, 0 replies; 81+ messages in thread
From: McClintock Matthew-B29882 @ 2012-10-31 22:44 UTC (permalink / raw)
To: u-boot
On Wed, Oct 31, 2012 at 5:08 PM, Scott Wood <scottwood@freescale.com> wrote:
> On 10/31/2012 01:17:31 AM, Prabhakar Kushwaha wrote:
>>
>> On 10/31/2012 02:37 AM, Scott Wood wrote:
>>>
>>> On 10/30/2012 04:26:16 AM, Prabhakar Kushwaha wrote:
>>> I'd rather not see this split this up. This file is too much of a
>>> complicated ifdef mess already.
>>>
>>> The window during which you won't be able to use breakpoints is not that
>>> large.
>>> There are other debugging techniques that can be used.
>>
>>
>> Can you please share the other techniques. It will help us in future.
>
>
> For debugging early boot hangs I usually put a branch-to-self somewhere in
> the sequence, and use CCS to see if we're spinning there or if we went off
> to some exception or other badness. Then I do a binary search, moving the
> branch to self around, to determine where things went wrong.
LR can be handy to look at too to see what the calling function / branch was.
-M
^ permalink raw reply [flat|nested] 81+ messages in thread[parent not found: <CAEsOVNeZAyH1nxfgnjPYUG4=7yxjF9rjsRWrpa=WYW8edfiM3Q@mail.gmail.com>]
* [U-Boot] [PATCH v2 03/22] powerpc/mpc85xx: move debug tlb entry after TLB is in known state
[not found] ` <CAEsOVNeZAyH1nxfgnjPYUG4=7yxjF9rjsRWrpa=WYW8edfiM3Q@mail.gmail.com>
@ 2012-10-31 22:45 ` McClintock Matthew-B29882
2012-10-31 22:51 ` Scott Wood
0 siblings, 1 reply; 81+ messages in thread
From: McClintock Matthew-B29882 @ 2012-10-31 22:45 UTC (permalink / raw)
To: u-boot
On Wed, Oct 31, 2012 at 5:43 PM, Matthew McClintock <msm@freescale.com> wrote:
> On Wed, Oct 31, 2012 at 5:08 PM, Scott Wood <scottwood@freescale.com> wrote:
>> On 10/31/2012 01:17:31 AM, Prabhakar Kushwaha wrote:
>>>
>>> On 10/31/2012 02:37 AM, Scott Wood wrote:
>>>>
>>>> On 10/30/2012 04:26:16 AM, Prabhakar Kushwaha wrote:
>>>> I'd rather not see this split this up. This file is too much of a
>>>> complicated ifdef mess already.
>>>>
>>>> The window during which you won't be able to use breakpoints is not that
>>>> large.
>>>> There are other debugging techniques that can be used.
>>>
>>>
>>> Can you please share the other techniques. It will help us in future.
>>
>>
>> For debugging early boot hangs I usually put a branch-to-self somewhere in
>> the sequence, and use CCS to see if we're spinning there or if we went off
>> to some exception or other badness. Then I do a binary search, moving the
>> branch to self around, to determine where things went wrong.
>
> LR can be handy to look at too to see what the calling function / branch was.
And to add more... It's even more helpful when you did not instrument
your code with a branch to self yet, since sometimes you can find out
a good starting point for placing the branch to self in the first
place.
-M
^ permalink raw reply [flat|nested] 81+ messages in thread* [U-Boot] [PATCH v2 03/22] powerpc/mpc85xx: move debug tlb entry after TLB is in known state
2012-10-31 22:45 ` McClintock Matthew-B29882
@ 2012-10-31 22:51 ` Scott Wood
0 siblings, 0 replies; 81+ messages in thread
From: Scott Wood @ 2012-10-31 22:51 UTC (permalink / raw)
To: u-boot
On 10/31/2012 05:45:00 PM, McClintock Matthew-B29882 wrote:
> On Wed, Oct 31, 2012 at 5:43 PM, Matthew McClintock
> <msm@freescale.com> wrote:
> > On Wed, Oct 31, 2012 at 5:08 PM, Scott Wood
> <scottwood@freescale.com> wrote:
> >> On 10/31/2012 01:17:31 AM, Prabhakar Kushwaha wrote:
> >>>
> >>> On 10/31/2012 02:37 AM, Scott Wood wrote:
> >>>>
> >>>> On 10/30/2012 04:26:16 AM, Prabhakar Kushwaha wrote:
> >>>> I'd rather not see this split this up. This file is too much of
> a
> >>>> complicated ifdef mess already.
> >>>>
> >>>> The window during which you won't be able to use breakpoints is
> not that
> >>>> large.
> >>>> There are other debugging techniques that can be used.
> >>>
> >>>
> >>> Can you please share the other techniques. It will help us in
> future.
> >>
> >>
> >> For debugging early boot hangs I usually put a branch-to-self
> somewhere in
> >> the sequence, and use CCS to see if we're spinning there or if we
> went off
> >> to some exception or other badness. Then I do a binary search,
> moving the
> >> branch to self around, to determine where things went wrong.
> >
> > LR can be handy to look at too to see what the calling function /
> branch was.
>
> And to add more... It's even more helpful when you did not instrument
> your code with a branch to self yet, since sometimes you can find out
> a good starting point for placing the branch to self in the first
> place.
Sure, what I wrote was meant for situations where the register dump
after you get in a bad state is not very useful, as was often the case
when debugging this code (infrequent use of LR, stuck in an exception
handler that repeatedly raises itself, obliterating the original
SRR0). Sometimes I've seen the chip get stuck so hard that you can't
even get register info out.
-Scott
^ permalink raw reply [flat|nested] 81+ messages in thread
* [U-Boot] [PATCH v2 03/22] powerpc/mpc85xx: move debug tlb entry after TLB is in known state
2012-10-30 2:04 ` [U-Boot] [PATCH v2 03/22] powerpc/mpc85xx: move debug tlb entry after TLB is in known state Scott Wood
2012-10-30 9:26 ` Prabhakar Kushwaha
@ 2012-11-16 2:12 ` Scott Wood
2012-11-26 20:53 ` Andy Fleming
2 siblings, 0 replies; 81+ messages in thread
From: Scott Wood @ 2012-11-16 2:12 UTC (permalink / raw)
To: u-boot
On 10/29/2012 09:04:51 PM, Scott Wood wrote:
> Previously, in many if not all configs we were creating overlapping
> TLB entries
> which is illegal. This caused a crash during boot when moving
> p2020rdb NAND SPL
> into L2 SRAM.
>
> Signed-off-by: Scott Wood <scottwood@freescale.com>
> Cc: Prabhakar Kushwaha <prabhakar@freescale.com>
> Cc: Andy Fleming <afleming@freescale.com>
> --
> Prabhakar, please test that debug still works.
> ---
> arch/powerpc/cpu/mpc85xx/start.S | 84
> ++++++++++++++++++--------------------
> 1 file changed, 40 insertions(+), 44 deletions(-)
Andy, could you ack (or nack) this and the other 85xx patches to go via
the NAND tree?
-Scott
^ permalink raw reply [flat|nested] 81+ messages in thread
* [U-Boot] [PATCH v2 03/22] powerpc/mpc85xx: move debug tlb entry after TLB is in known state
2012-10-30 2:04 ` [U-Boot] [PATCH v2 03/22] powerpc/mpc85xx: move debug tlb entry after TLB is in known state Scott Wood
2012-10-30 9:26 ` Prabhakar Kushwaha
2012-11-16 2:12 ` Scott Wood
@ 2012-11-26 20:53 ` Andy Fleming
2 siblings, 0 replies; 81+ messages in thread
From: Andy Fleming @ 2012-11-26 20:53 UTC (permalink / raw)
To: u-boot
On Mon, Oct 29, 2012 at 9:04 PM, Scott Wood <scottwood@freescale.com> wrote:
> Previously, in many if not all configs we were creating overlapping TLB
> entries
> which is illegal. This caused a crash during boot when moving p2020rdb
> NAND SPL
> into L2 SRAM.
>
> Signed-off-by: Scott Wood <scottwood@freescale.com>
> Cc: Prabhakar Kushwaha <prabhakar@freescale.com>
> Cc: Andy Fleming <afleming@freescale.com>
>
Acked-by: Andy Fleming <afleming@freescale.com>
Prabhakar, we can discuss whether to modify this code in the future to
support earlier debug. I'm inclined to agree with Scott's argument, but
with the right solution, we might be able to make it work.
Andy
^ permalink raw reply [flat|nested] 81+ messages in thread
* [U-Boot] [PATCH v2 04/22] powerpc/mpc85xx: add comma before "already enabled"
2012-10-30 2:04 ` [U-Boot] [PATCH v2 00/22] " Scott Wood
` (2 preceding siblings ...)
2012-10-30 2:04 ` [U-Boot] [PATCH v2 03/22] powerpc/mpc85xx: move debug tlb entry after TLB is in known state Scott Wood
@ 2012-10-30 2:04 ` Scott Wood
2012-10-30 2:04 ` [U-Boot] [PATCH v2 05/22] Add u-boot-pad.bin target to the Makefile Scott Wood
` (18 subsequent siblings)
22 siblings, 0 replies; 81+ messages in thread
From: Scott Wood @ 2012-10-30 2:04 UTC (permalink / raw)
To: u-boot
Now outputs like this:
L2: 512 KB already enabled, moving to 0xf8f80000
rather than this:
L2: 512 KB already enabledmoving to 0xf8f80000
Signed-off-by: Scott Wood <scottwood@freescale.com>
Cc: Andy Fleming <afleming@gmail.com>
---
arch/powerpc/cpu/mpc85xx/cpu_init.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 736293c..c34738e 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -470,7 +470,7 @@ int cpu_init_r(void)
&& l2srbar >= CONFIG_SYS_FLASH_BASE) {
l2srbar = CONFIG_SYS_INIT_L2_ADDR;
l2cache->l2srbar0 = l2srbar;
- printf("moving to 0x%08x", CONFIG_SYS_INIT_L2_ADDR);
+ printf(", moving to 0x%08x", CONFIG_SYS_INIT_L2_ADDR);
}
#endif /* CONFIG_SYS_INIT_L2_ADDR */
puts("\n");
--
1.7.9.5
^ permalink raw reply related [flat|nested] 81+ messages in thread* [U-Boot] [PATCH v2 05/22] Add u-boot-pad.bin target to the Makefile
2012-10-30 2:04 ` [U-Boot] [PATCH v2 00/22] " Scott Wood
` (3 preceding siblings ...)
2012-10-30 2:04 ` [U-Boot] [PATCH v2 04/22] powerpc/mpc85xx: add comma before "already enabled" Scott Wood
@ 2012-10-30 2:04 ` Scott Wood
2012-10-30 2:04 ` [U-Boot] [PATCH v2 06/22] spl: rename u-boot-pad.bin to u-boot-with-spl.bin Scott Wood
` (17 subsequent siblings)
22 siblings, 0 replies; 81+ messages in thread
From: Scott Wood @ 2012-10-30 2:04 UTC (permalink / raw)
To: u-boot
From: Jos? Miguel Gon?alves <jose.goncalves@inov.pt>
Samsung's S3C24XX SoCs need this in order to generate a binary image
with a padded SPL concatenated with U-Boot.
Signed-off-by: Jos? Miguel Gon?alves <jose.goncalves@inov.pt>
[scottwood at freescale.com: fixed prereq of u-boot.ubl]
Signed-off-by: Scott Wood <scottwood@freescale.com>
--
v2: Removed spl/ prefix from u-boot.ubl prerequisite.
---
Makefile | 11 ++++++-----
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/Makefile b/Makefile
index d385467..366096f 100644
--- a/Makefile
+++ b/Makefile
@@ -470,14 +470,15 @@ $(obj)u-boot.sha1: $(obj)u-boot.bin
$(obj)u-boot.dis: $(obj)u-boot
$(OBJDUMP) -d $< > $@
-$(obj)u-boot.ubl: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin
+$(obj)u-boot-pad.bin: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin
$(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $(obj)spl/u-boot-spl $(obj)spl/u-boot-spl-pad.bin
- cat $(obj)spl/u-boot-spl-pad.bin $(obj)u-boot.bin > $(obj)u-boot-ubl.bin
- $(obj)tools/mkimage -n $(UBL_CONFIG) -T ublimage \
- -e $(CONFIG_SYS_TEXT_BASE) -d $(obj)u-boot-ubl.bin $(obj)u-boot.ubl
- rm $(obj)u-boot-ubl.bin
+ cat $(obj)spl/u-boot-spl-pad.bin $(obj)u-boot.bin > $(obj)u-boot-pad.bin
rm $(obj)spl/u-boot-spl-pad.bin
+$(obj)u-boot.ubl: $(obj)u-boot-pad.bin
+ $(obj)tools/mkimage -n $(UBL_CONFIG) -T ublimage \
+ -e $(CONFIG_SYS_TEXT_BASE) -d $(obj)u-boot-pad.bin $(obj)u-boot.ubl
+
$(obj)u-boot.ais: $(obj)spl/u-boot-spl.bin $(obj)u-boot.img
$(obj)tools/mkimage -s -n $(if $(CONFIG_AIS_CONFIG_FILE),$(CONFIG_AIS_CONFIG_FILE),"/dev/null") \
-T aisimage \
--
1.7.9.5
^ permalink raw reply related [flat|nested] 81+ messages in thread* [U-Boot] [PATCH v2 06/22] spl: rename u-boot-pad.bin to u-boot-with-spl.bin
2012-10-30 2:04 ` [U-Boot] [PATCH v2 00/22] " Scott Wood
` (4 preceding siblings ...)
2012-10-30 2:04 ` [U-Boot] [PATCH v2 05/22] Add u-boot-pad.bin target to the Makefile Scott Wood
@ 2012-10-30 2:04 ` Scott Wood
2012-10-30 2:04 ` [U-Boot] [PATCH v2 07/22] spl: introduce CONFIG_SPL_TARGET Scott Wood
` (16 subsequent siblings)
22 siblings, 0 replies; 81+ messages in thread
From: Scott Wood @ 2012-10-30 2:04 UTC (permalink / raw)
To: u-boot
Signed-off-by: Scott Wood <scottwood@freescale.com>
---
Makefile | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/Makefile b/Makefile
index 366096f..61f4d69 100644
--- a/Makefile
+++ b/Makefile
@@ -470,14 +470,14 @@ $(obj)u-boot.sha1: $(obj)u-boot.bin
$(obj)u-boot.dis: $(obj)u-boot
$(OBJDUMP) -d $< > $@
-$(obj)u-boot-pad.bin: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin
+$(obj)u-boot-with-spl.bin: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin
$(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $(obj)spl/u-boot-spl $(obj)spl/u-boot-spl-pad.bin
- cat $(obj)spl/u-boot-spl-pad.bin $(obj)u-boot.bin > $(obj)u-boot-pad.bin
+ cat $(obj)spl/u-boot-spl-pad.bin $(obj)u-boot.bin > $@
rm $(obj)spl/u-boot-spl-pad.bin
-$(obj)u-boot.ubl: $(obj)u-boot-pad.bin
+$(obj)u-boot.ubl: $(obj)u-boot-with-spl.bin
$(obj)tools/mkimage -n $(UBL_CONFIG) -T ublimage \
- -e $(CONFIG_SYS_TEXT_BASE) -d $(obj)u-boot-pad.bin $(obj)u-boot.ubl
+ -e $(CONFIG_SYS_TEXT_BASE) -d $< $(obj)u-boot.ubl
$(obj)u-boot.ais: $(obj)spl/u-boot-spl.bin $(obj)u-boot.img
$(obj)tools/mkimage -s -n $(if $(CONFIG_AIS_CONFIG_FILE),$(CONFIG_AIS_CONFIG_FILE),"/dev/null") \
--
1.7.9.5
^ permalink raw reply related [flat|nested] 81+ messages in thread* [U-Boot] [PATCH v2 07/22] spl: introduce CONFIG_SPL_TARGET
2012-10-30 2:04 ` [U-Boot] [PATCH v2 00/22] " Scott Wood
` (5 preceding siblings ...)
2012-10-30 2:04 ` [U-Boot] [PATCH v2 06/22] spl: rename u-boot-pad.bin to u-boot-with-spl.bin Scott Wood
@ 2012-10-30 2:04 ` Scott Wood
2012-10-30 2:04 ` [U-Boot] [PATCH v2 08/22] powerpc: change .fixup test to a GCC version test Scott Wood
` (15 subsequent siblings)
22 siblings, 0 replies; 81+ messages in thread
From: Scott Wood @ 2012-10-30 2:04 UTC (permalink / raw)
To: u-boot
Currently the SPL target is specified in a CPU-specific makefile
fragment. While some targets may need something more complicated than a
simple target name, targets which don't need this shouldn't have to provide a makefile fragment just for this.
Signed-off-by: Scott Wood <scottwood@freescale.com>
---
v2: Removed default target as it's been pointed out to me how existing platforms
cause the SPL to be built.
---
Makefile | 1 +
README | 5 +++++
2 files changed, 6 insertions(+)
diff --git a/Makefile b/Makefile
index 61f4d69..7630ce9 100644
--- a/Makefile
+++ b/Makefile
@@ -403,6 +403,7 @@ ALL-y += $(obj)u-boot.srec $(obj)u-boot.bin $(obj)System.map
ALL-$(CONFIG_NAND_U_BOOT) += $(obj)u-boot-nand.bin
ALL-$(CONFIG_ONENAND_U_BOOT) += $(obj)u-boot-onenand.bin
ALL-$(CONFIG_SPL) += $(obj)spl/u-boot-spl.bin
+ALL-$(CONFIG_SPL) += $(obj)$(subst ",,$(CONFIG_SPL_TARGET))
ALL-$(CONFIG_OF_SEPARATE) += $(obj)u-boot.dtb $(obj)u-boot-dtb.bin
# enable combined SPL/u-boot/dtb rules for tegra
diff --git a/README b/README
index 4f16240..4294c2e 100644
--- a/README
+++ b/README
@@ -2726,6 +2726,11 @@ FIT uImage format:
CONFIG_SPL_LIBGENERIC_SUPPORT
Support for lib/libgeneric.o in SPL binary
+ CONFIG_SPL_TARGET
+ Final target image containing SPL and payload. Some SPLs
+ use an arch-specific makefile fragment instead, for
+ example if more than one image needs to be produced.
+
Modem Support:
--------------
--
1.7.9.5
^ permalink raw reply related [flat|nested] 81+ messages in thread* [U-Boot] [PATCH v2 08/22] powerpc: change .fixup test to a GCC version test
2012-10-30 2:04 ` [U-Boot] [PATCH v2 00/22] " Scott Wood
` (6 preceding siblings ...)
2012-10-30 2:04 ` [U-Boot] [PATCH v2 07/22] spl: introduce CONFIG_SPL_TARGET Scott Wood
@ 2012-10-30 2:04 ` Scott Wood
2012-10-30 2:04 ` [U-Boot] [PATCH v2 09/22] powerpc/mpc85xx: fix TLB alignment Scott Wood
` (14 subsequent siblings)
22 siblings, 0 replies; 81+ messages in thread
From: Scott Wood @ 2012-10-30 2:04 UTC (permalink / raw)
To: u-boot
This was introduced by commit 244615197469dd6fe75ae082f38424b97c79aeaf, but it
fails in a minimal SPL build where the only thing in arch/powerpc/lib is
cache.c, which apparently doesn't generate any fixup records.
The problem is reported to occur with GCC 3.x, so insist on GCC 4.0 or newer.
Patterned after checkthumb as suggested by Tom Rini.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Cc: Peter Tyser <ptyser@xes-inc.com>
Cc: Tom Rini <trini@ti.com>
--
v2: test gcc version instead of testing nothing
---
Makefile | 10 ++++++++++
arch/powerpc/config.mk | 5 +++++
arch/powerpc/lib/Makefile | 6 ------
3 files changed, 15 insertions(+), 6 deletions(-)
diff --git a/Makefile b/Makefile
index 7630ce9..751179c 100644
--- a/Makefile
+++ b/Makefile
@@ -638,6 +638,16 @@ checkthumb:
echo '*** Your board is configured for THUMB mode.'; \
false; \
fi
+
+# GCC 3.x is reported to have problems generating the type of relocation
+# that U-Boot wants.
+# See http://lists.denx.de/pipermail/u-boot/2012-September/135156.html
+checkgcc4:
+ @if test $(call cc-version) -lt 0400; then \
+ echo -n '*** Your GCC is too old, please upgrade to GCC 4.x or newer'; \
+ false; \
+ fi
+
#
# Auto-generate the autoconf.mk file (which is included by all makefiles)
#
diff --git a/arch/powerpc/config.mk b/arch/powerpc/config.mk
index a307154..b706281 100644
--- a/arch/powerpc/config.mk
+++ b/arch/powerpc/config.mk
@@ -42,3 +42,8 @@ endif
ifeq ($(CROSS_COMPILE),powerpc-openbsd-)
PLATFORM_CPPFLAGS+= -D__PPC__
endif
+
+# Only test once
+ifneq ($(CONFIG_SPL_BUILD),y)
+ALL-y += checkgcc4
+endif
diff --git a/arch/powerpc/lib/Makefile b/arch/powerpc/lib/Makefile
index 808021c..4a41635 100644
--- a/arch/powerpc/lib/Makefile
+++ b/arch/powerpc/lib/Makefile
@@ -75,12 +75,6 @@ TARGETS += $(LIB)
all: $(TARGETS)
$(LIB): $(obj).depend $(OBJS)
- @if ! $(CROSS_COMPILE)readelf -S $(OBJS) | grep -q '\.fixup.*PROGBITS';\
- then \
- echo "ERROR: Your compiler doesn't generate .fixup sections!";\
- echo " Upgrade to a recent toolchain."; \
- exit 1; \
- fi;
$(call cmd_link_o_target, $(OBJS))
$(LIBGCC): $(obj).depend $(LGOBJS)
--
1.7.9.5
^ permalink raw reply related [flat|nested] 81+ messages in thread* [U-Boot] [PATCH v2 09/22] powerpc/mpc85xx: fix TLB alignment
2012-10-30 2:04 ` [U-Boot] [PATCH v2 00/22] " Scott Wood
` (7 preceding siblings ...)
2012-10-30 2:04 ` [U-Boot] [PATCH v2 08/22] powerpc: change .fixup test to a GCC version test Scott Wood
@ 2012-10-30 2:04 ` Scott Wood
2012-10-30 2:04 ` [U-Boot] [PATCH v2 10/22] powerpc/mpc8xxx: move LAW code into arch/powerpc/cpu/mpc8xxx Scott Wood
` (13 subsequent siblings)
22 siblings, 0 replies; 81+ messages in thread
From: Scott Wood @ 2012-10-30 2:04 UTC (permalink / raw)
To: u-boot
In the RAMBOOT/SPL case we were creating a TLB entry starting at
CONFIG_SYS_MONITOR_BASE, and just hoping that the base was properly
aligned for the TLB entry size. This turned out to not be the case
with NAND SPL because the main U-Boot starts at an offset into the image
in order to skip the SPL itself.
Fix the TLB entry to always start at a proper alignment. We still assume that
CONFIG_SYS_MONITOR_BASE doesn't start immediately before a large-page boundary
thus requiring multiple TLB entries.
Signed-off-by: Scott Wood <scottwood@frescale.com>
Cc: Andy Fleming <afleming@freescale.com>
---
arch/powerpc/cpu/mpc85xx/start.S | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index 7912a4b..577d687 100644
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -1046,8 +1046,8 @@ create_init_ram_area:
*/
create_tlb1_entry 15, \
1, BOOKE_PAGESZ_1M, \
- CONFIG_SYS_MONITOR_BASE, MAS2_I|MAS2_G, \
- CONFIG_SYS_PBI_FLASH_WINDOW, MAS3_SX|MAS3_SW|MAS3_SR, \
+ CONFIG_SYS_MONITOR_BASE & 0xfff00000, MAS2_I|MAS2_G, \
+ CONFIG_SYS_PBI_FLASH_WINDOW & 0xfff00000, MAS3_SX|MAS3_SW|MAS3_SR, \
0, r6
#else
/*
@@ -1056,8 +1056,8 @@ create_init_ram_area:
*/
create_tlb1_entry 15, \
1, BOOKE_PAGESZ_1M, \
- CONFIG_SYS_MONITOR_BASE, MAS2_I|MAS2_G, \
- CONFIG_SYS_MONITOR_BASE, MAS3_SX|MAS3_SW|MAS3_SR, \
+ CONFIG_SYS_MONITOR_BASE & 0xfff00000, MAS2_I|MAS2_G, \
+ CONFIG_SYS_MONITOR_BASE & 0xfff00000, MAS3_SX|MAS3_SW|MAS3_SR, \
0, r6
#endif
--
1.7.9.5
^ permalink raw reply related [flat|nested] 81+ messages in thread* [U-Boot] [PATCH v2 10/22] powerpc/mpc8xxx: move LAW code into arch/powerpc/cpu/mpc8xxx
2012-10-30 2:04 ` [U-Boot] [PATCH v2 00/22] " Scott Wood
` (8 preceding siblings ...)
2012-10-30 2:04 ` [U-Boot] [PATCH v2 09/22] powerpc/mpc85xx: fix TLB alignment Scott Wood
@ 2012-10-30 2:04 ` Scott Wood
2012-10-30 2:04 ` [U-Boot] [PATCH v2 11/22] spl/mpc85xx: move udelay to cpu code Scott Wood
` (12 subsequent siblings)
22 siblings, 0 replies; 81+ messages in thread
From: Scott Wood @ 2012-10-30 2:04 UTC (permalink / raw)
To: u-boot
It's arch code and not a driver, so move it where it belongs. When it
originally went into drivers/misc there was no 8xxx CPU directory.
This will make new-SPL support a little easier since we can keep the CPU
stuff together and not need to pull stuff in from drivers/misc.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Cc: Andy Fleming <afleming@freescale.com>
---
arch/powerpc/cpu/mpc8xxx/Makefile | 1 +
arch/powerpc/cpu/mpc8xxx/law.c | 333 ++++++++++++++++++++++++
drivers/misc/Makefile | 1 -
drivers/misc/fsl_law.c | 333 ------------------------
nand_spl/board/freescale/mpc8536ds/Makefile | 2 +-
nand_spl/board/freescale/mpc8569mds/Makefile | 2 +-
nand_spl/board/freescale/mpc8572ds/Makefile | 2 +-
nand_spl/board/freescale/p1010rdb/Makefile | 2 +-
nand_spl/board/freescale/p1023rds/Makefile | 2 +-
nand_spl/board/freescale/p1_p2_rdb/Makefile | 2 +-
nand_spl/board/freescale/p1_p2_rdb_pc/Makefile | 2 +-
11 files changed, 341 insertions(+), 341 deletions(-)
create mode 100644 arch/powerpc/cpu/mpc8xxx/law.c
delete mode 100644 drivers/misc/fsl_law.c
diff --git a/arch/powerpc/cpu/mpc8xxx/Makefile b/arch/powerpc/cpu/mpc8xxx/Makefile
index 4ae26e4..86344a7 100644
--- a/arch/powerpc/cpu/mpc8xxx/Makefile
+++ b/arch/powerpc/cpu/mpc8xxx/Makefile
@@ -18,6 +18,7 @@ COBJS-$(CONFIG_OF_LIBFDT) += fdt.o
COBJS-$(CONFIG_FSL_IFC) += fsl_ifc.o
COBJS-$(CONFIG_FSL_LBC) += fsl_lbc.o
COBJS-$(CONFIG_SYS_SRIO) += srio.o
+COBJS-$(CONFIG_FSL_LAW) += law.o
SRCS := $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
diff --git a/arch/powerpc/cpu/mpc8xxx/law.c b/arch/powerpc/cpu/mpc8xxx/law.c
new file mode 100644
index 0000000..223cd5d
--- /dev/null
+++ b/arch/powerpc/cpu/mpc8xxx/law.c
@@ -0,0 +1,333 @@
+/*
+ * Copyright 2008-2011 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <linux/compiler.h>
+#include <asm/fsl_law.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define FSL_HW_NUM_LAWS CONFIG_SYS_FSL_NUM_LAWS
+
+#ifdef CONFIG_FSL_CORENET
+#define LAW_BASE (CONFIG_SYS_FSL_CORENET_CCM_ADDR)
+#define LAWAR_ADDR(x) (&((ccsr_local_t *)LAW_BASE)->law[x].lawar)
+#define LAWBARH_ADDR(x) (&((ccsr_local_t *)LAW_BASE)->law[x].lawbarh)
+#define LAWBARL_ADDR(x) (&((ccsr_local_t *)LAW_BASE)->law[x].lawbarl)
+#define LAWBAR_SHIFT 0
+#else
+#define LAW_BASE (CONFIG_SYS_IMMR + 0xc08)
+#define LAWAR_ADDR(x) ((u32 *)LAW_BASE + 8 * x + 2)
+#define LAWBAR_ADDR(x) ((u32 *)LAW_BASE + 8 * x)
+#define LAWBAR_SHIFT 12
+#endif
+
+
+static inline phys_addr_t get_law_base_addr(int idx)
+{
+#ifdef CONFIG_FSL_CORENET
+ return (phys_addr_t)
+ ((u64)in_be32(LAWBARH_ADDR(idx)) << 32) |
+ in_be32(LAWBARL_ADDR(idx));
+#else
+ return (phys_addr_t)in_be32(LAWBAR_ADDR(idx)) << LAWBAR_SHIFT;
+#endif
+}
+
+static inline void set_law_base_addr(int idx, phys_addr_t addr)
+{
+#ifdef CONFIG_FSL_CORENET
+ out_be32(LAWBARL_ADDR(idx), addr & 0xffffffff);
+ out_be32(LAWBARH_ADDR(idx), (u64)addr >> 32);
+#else
+ out_be32(LAWBAR_ADDR(idx), addr >> LAWBAR_SHIFT);
+#endif
+}
+
+void set_law(u8 idx, phys_addr_t addr, enum law_size sz, enum law_trgt_if id)
+{
+ gd->used_laws |= (1 << idx);
+
+ out_be32(LAWAR_ADDR(idx), 0);
+ set_law_base_addr(idx, addr);
+ out_be32(LAWAR_ADDR(idx), LAW_EN | ((u32)id << 20) | (u32)sz);
+
+ /* Read back so that we sync the writes */
+ in_be32(LAWAR_ADDR(idx));
+}
+
+void disable_law(u8 idx)
+{
+ gd->used_laws &= ~(1 << idx);
+
+ out_be32(LAWAR_ADDR(idx), 0);
+ set_law_base_addr(idx, 0);
+
+ /* Read back so that we sync the writes */
+ in_be32(LAWAR_ADDR(idx));
+
+ return;
+}
+
+#ifndef CONFIG_NAND_SPL
+static int get_law_entry(u8 i, struct law_entry *e)
+{
+ u32 lawar;
+
+ lawar = in_be32(LAWAR_ADDR(i));
+
+ if (!(lawar & LAW_EN))
+ return 0;
+
+ e->addr = get_law_base_addr(i);
+ e->size = lawar & 0x3f;
+ e->trgt_id = (lawar >> 20) & 0xff;
+
+ return 1;
+}
+#endif
+
+int set_next_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id)
+{
+ u32 idx = ffz(gd->used_laws);
+
+ if (idx >= FSL_HW_NUM_LAWS)
+ return -1;
+
+ set_law(idx, addr, sz, id);
+
+ return idx;
+}
+
+#ifndef CONFIG_NAND_SPL
+int set_last_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id)
+{
+ u32 idx;
+
+ /* we have no LAWs free */
+ if (gd->used_laws == -1)
+ return -1;
+
+ /* grab the last free law */
+ idx = __ilog2(~(gd->used_laws));
+
+ if (idx >= FSL_HW_NUM_LAWS)
+ return -1;
+
+ set_law(idx, addr, sz, id);
+
+ return idx;
+}
+
+struct law_entry find_law(phys_addr_t addr)
+{
+ struct law_entry entry;
+ int i;
+
+ entry.index = -1;
+ entry.addr = 0;
+ entry.size = 0;
+ entry.trgt_id = 0;
+
+ for (i = 0; i < FSL_HW_NUM_LAWS; i++) {
+ u64 upper;
+
+ if (!get_law_entry(i, &entry))
+ continue;
+
+ upper = entry.addr + (2ull << entry.size);
+ if ((addr >= entry.addr) && (addr < upper)) {
+ entry.index = i;
+ break;
+ }
+ }
+
+ return entry;
+}
+
+void print_laws(void)
+{
+ int i;
+ u32 lawar;
+
+ printf("\nLocal Access Window Configuration\n");
+ for (i = 0; i < FSL_HW_NUM_LAWS; i++) {
+ lawar = in_be32(LAWAR_ADDR(i));
+#ifdef CONFIG_FSL_CORENET
+ printf("LAWBARH%02d: 0x%08x LAWBARL%02d: 0x%08x",
+ i, in_be32(LAWBARH_ADDR(i)),
+ i, in_be32(LAWBARL_ADDR(i)));
+#else
+ printf("LAWBAR%02d: 0x%08x", i, in_be32(LAWBAR_ADDR(i)));
+#endif
+ printf(" LAWAR%02d: 0x%08x\n", i, lawar);
+ printf("\t(EN: %d TGT: 0x%02x SIZE: ",
+ (lawar & LAW_EN) ? 1 : 0, (lawar >> 20) & 0xff);
+ print_size(lawar_size(lawar), ")\n");
+ }
+
+ return;
+}
+
+/* use up to 2 LAWs for DDR, used the last available LAWs */
+int set_ddr_laws(u64 start, u64 sz, enum law_trgt_if id)
+{
+ u64 start_align, law_sz;
+ int law_sz_enc;
+
+ if (start == 0)
+ start_align = 1ull << (LAW_SIZE_32G + 1);
+ else
+ start_align = 1ull << (ffs64(start) - 1);
+ law_sz = min(start_align, sz);
+ law_sz_enc = __ilog2_u64(law_sz) - 1;
+
+ if (set_last_law(start, law_sz_enc, id) < 0)
+ return -1;
+
+ /* recalculate size based on what was actually covered by the law */
+ law_sz = 1ull << __ilog2_u64(law_sz);
+
+ /* do we still have anything to map */
+ sz = sz - law_sz;
+ if (sz) {
+ start += law_sz;
+
+ start_align = 1ull << (ffs64(start) - 1);
+ law_sz = min(start_align, sz);
+ law_sz_enc = __ilog2_u64(law_sz) - 1;
+
+ if (set_last_law(start, law_sz_enc, id) < 0)
+ return -1;
+ } else {
+ return 0;
+ }
+
+ /* do we still have anything to map */
+ sz = sz - law_sz;
+ if (sz)
+ return 1;
+
+ return 0;
+}
+#endif
+
+void init_laws(void)
+{
+ int i;
+
+#if FSL_HW_NUM_LAWS < 32
+ gd->used_laws = ~((1 << FSL_HW_NUM_LAWS) - 1);
+#elif FSL_HW_NUM_LAWS == 32
+ gd->used_laws = 0;
+#else
+#error FSL_HW_NUM_LAWS can not be greater than 32 w/o code changes
+#endif
+
+ /*
+ * Any LAWs that were set up before we booted assume they are meant to
+ * be around and mark them used.
+ */
+ for (i = 0; i < FSL_HW_NUM_LAWS; i++) {
+ u32 lawar = in_be32(LAWAR_ADDR(i));
+
+ if (lawar & LAW_EN)
+ gd->used_laws |= (1 << i);
+ }
+
+#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
+ /*
+ * in NAND boot we've already parsed the law_table and setup those LAWs
+ * so don't do it again.
+ */
+ return;
+#endif
+
+ for (i = 0; i < num_law_entries; i++) {
+ if (law_table[i].index == -1)
+ set_next_law(law_table[i].addr, law_table[i].size,
+ law_table[i].trgt_id);
+ else
+ set_law(law_table[i].index, law_table[i].addr,
+ law_table[i].size, law_table[i].trgt_id);
+ }
+
+#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
+ /* check RCW to get which port is used for boot */
+ ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+ u32 bootloc = in_be32(&gur->rcwsr[6]);
+ /*
+ * in SRIO or PCIE boot we need to set specail LAWs for
+ * SRIO or PCIE interfaces.
+ */
+ switch ((bootloc & FSL_CORENET_RCWSR6_BOOT_LOC) >> 23) {
+ case 0x0: /* boot from PCIE1 */
+ set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
+ LAW_SIZE_1M,
+ LAW_TRGT_IF_PCIE_1);
+ set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
+ LAW_SIZE_1M,
+ LAW_TRGT_IF_PCIE_1);
+ break;
+ case 0x1: /* boot from PCIE2 */
+ set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
+ LAW_SIZE_1M,
+ LAW_TRGT_IF_PCIE_2);
+ set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
+ LAW_SIZE_1M,
+ LAW_TRGT_IF_PCIE_2);
+ break;
+ case 0x2: /* boot from PCIE3 */
+ set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
+ LAW_SIZE_1M,
+ LAW_TRGT_IF_PCIE_3);
+ set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
+ LAW_SIZE_1M,
+ LAW_TRGT_IF_PCIE_3);
+ break;
+ case 0x8: /* boot from SRIO1 */
+ set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
+ LAW_SIZE_1M,
+ LAW_TRGT_IF_RIO_1);
+ set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
+ LAW_SIZE_1M,
+ LAW_TRGT_IF_RIO_1);
+ break;
+ case 0x9: /* boot from SRIO2 */
+ set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
+ LAW_SIZE_1M,
+ LAW_TRGT_IF_RIO_2);
+ set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
+ LAW_SIZE_1M,
+ LAW_TRGT_IF_RIO_2);
+ break;
+ default:
+ break;
+ }
+#endif
+
+ return ;
+}
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index 271463c..3b19e5f 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -27,7 +27,6 @@ LIB := $(obj)libmisc.o
COBJS-$(CONFIG_ALI152X) += ali512x.o
COBJS-$(CONFIG_DS4510) += ds4510.o
-COBJS-$(CONFIG_FSL_LAW) += fsl_law.o
COBJS-$(CONFIG_GPIO_LED) += gpio_led.o
COBJS-$(CONFIG_FSL_MC9SDZ60) += mc9sdz60.o
COBJS-$(CONFIG_NS87308) += ns87308.o
diff --git a/drivers/misc/fsl_law.c b/drivers/misc/fsl_law.c
deleted file mode 100644
index 223cd5d..0000000
--- a/drivers/misc/fsl_law.c
+++ /dev/null
@@ -1,333 +0,0 @@
-/*
- * Copyright 2008-2011 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <linux/compiler.h>
-#include <asm/fsl_law.h>
-#include <asm/io.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define FSL_HW_NUM_LAWS CONFIG_SYS_FSL_NUM_LAWS
-
-#ifdef CONFIG_FSL_CORENET
-#define LAW_BASE (CONFIG_SYS_FSL_CORENET_CCM_ADDR)
-#define LAWAR_ADDR(x) (&((ccsr_local_t *)LAW_BASE)->law[x].lawar)
-#define LAWBARH_ADDR(x) (&((ccsr_local_t *)LAW_BASE)->law[x].lawbarh)
-#define LAWBARL_ADDR(x) (&((ccsr_local_t *)LAW_BASE)->law[x].lawbarl)
-#define LAWBAR_SHIFT 0
-#else
-#define LAW_BASE (CONFIG_SYS_IMMR + 0xc08)
-#define LAWAR_ADDR(x) ((u32 *)LAW_BASE + 8 * x + 2)
-#define LAWBAR_ADDR(x) ((u32 *)LAW_BASE + 8 * x)
-#define LAWBAR_SHIFT 12
-#endif
-
-
-static inline phys_addr_t get_law_base_addr(int idx)
-{
-#ifdef CONFIG_FSL_CORENET
- return (phys_addr_t)
- ((u64)in_be32(LAWBARH_ADDR(idx)) << 32) |
- in_be32(LAWBARL_ADDR(idx));
-#else
- return (phys_addr_t)in_be32(LAWBAR_ADDR(idx)) << LAWBAR_SHIFT;
-#endif
-}
-
-static inline void set_law_base_addr(int idx, phys_addr_t addr)
-{
-#ifdef CONFIG_FSL_CORENET
- out_be32(LAWBARL_ADDR(idx), addr & 0xffffffff);
- out_be32(LAWBARH_ADDR(idx), (u64)addr >> 32);
-#else
- out_be32(LAWBAR_ADDR(idx), addr >> LAWBAR_SHIFT);
-#endif
-}
-
-void set_law(u8 idx, phys_addr_t addr, enum law_size sz, enum law_trgt_if id)
-{
- gd->used_laws |= (1 << idx);
-
- out_be32(LAWAR_ADDR(idx), 0);
- set_law_base_addr(idx, addr);
- out_be32(LAWAR_ADDR(idx), LAW_EN | ((u32)id << 20) | (u32)sz);
-
- /* Read back so that we sync the writes */
- in_be32(LAWAR_ADDR(idx));
-}
-
-void disable_law(u8 idx)
-{
- gd->used_laws &= ~(1 << idx);
-
- out_be32(LAWAR_ADDR(idx), 0);
- set_law_base_addr(idx, 0);
-
- /* Read back so that we sync the writes */
- in_be32(LAWAR_ADDR(idx));
-
- return;
-}
-
-#ifndef CONFIG_NAND_SPL
-static int get_law_entry(u8 i, struct law_entry *e)
-{
- u32 lawar;
-
- lawar = in_be32(LAWAR_ADDR(i));
-
- if (!(lawar & LAW_EN))
- return 0;
-
- e->addr = get_law_base_addr(i);
- e->size = lawar & 0x3f;
- e->trgt_id = (lawar >> 20) & 0xff;
-
- return 1;
-}
-#endif
-
-int set_next_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id)
-{
- u32 idx = ffz(gd->used_laws);
-
- if (idx >= FSL_HW_NUM_LAWS)
- return -1;
-
- set_law(idx, addr, sz, id);
-
- return idx;
-}
-
-#ifndef CONFIG_NAND_SPL
-int set_last_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id)
-{
- u32 idx;
-
- /* we have no LAWs free */
- if (gd->used_laws == -1)
- return -1;
-
- /* grab the last free law */
- idx = __ilog2(~(gd->used_laws));
-
- if (idx >= FSL_HW_NUM_LAWS)
- return -1;
-
- set_law(idx, addr, sz, id);
-
- return idx;
-}
-
-struct law_entry find_law(phys_addr_t addr)
-{
- struct law_entry entry;
- int i;
-
- entry.index = -1;
- entry.addr = 0;
- entry.size = 0;
- entry.trgt_id = 0;
-
- for (i = 0; i < FSL_HW_NUM_LAWS; i++) {
- u64 upper;
-
- if (!get_law_entry(i, &entry))
- continue;
-
- upper = entry.addr + (2ull << entry.size);
- if ((addr >= entry.addr) && (addr < upper)) {
- entry.index = i;
- break;
- }
- }
-
- return entry;
-}
-
-void print_laws(void)
-{
- int i;
- u32 lawar;
-
- printf("\nLocal Access Window Configuration\n");
- for (i = 0; i < FSL_HW_NUM_LAWS; i++) {
- lawar = in_be32(LAWAR_ADDR(i));
-#ifdef CONFIG_FSL_CORENET
- printf("LAWBARH%02d: 0x%08x LAWBARL%02d: 0x%08x",
- i, in_be32(LAWBARH_ADDR(i)),
- i, in_be32(LAWBARL_ADDR(i)));
-#else
- printf("LAWBAR%02d: 0x%08x", i, in_be32(LAWBAR_ADDR(i)));
-#endif
- printf(" LAWAR%02d: 0x%08x\n", i, lawar);
- printf("\t(EN: %d TGT: 0x%02x SIZE: ",
- (lawar & LAW_EN) ? 1 : 0, (lawar >> 20) & 0xff);
- print_size(lawar_size(lawar), ")\n");
- }
-
- return;
-}
-
-/* use up to 2 LAWs for DDR, used the last available LAWs */
-int set_ddr_laws(u64 start, u64 sz, enum law_trgt_if id)
-{
- u64 start_align, law_sz;
- int law_sz_enc;
-
- if (start == 0)
- start_align = 1ull << (LAW_SIZE_32G + 1);
- else
- start_align = 1ull << (ffs64(start) - 1);
- law_sz = min(start_align, sz);
- law_sz_enc = __ilog2_u64(law_sz) - 1;
-
- if (set_last_law(start, law_sz_enc, id) < 0)
- return -1;
-
- /* recalculate size based on what was actually covered by the law */
- law_sz = 1ull << __ilog2_u64(law_sz);
-
- /* do we still have anything to map */
- sz = sz - law_sz;
- if (sz) {
- start += law_sz;
-
- start_align = 1ull << (ffs64(start) - 1);
- law_sz = min(start_align, sz);
- law_sz_enc = __ilog2_u64(law_sz) - 1;
-
- if (set_last_law(start, law_sz_enc, id) < 0)
- return -1;
- } else {
- return 0;
- }
-
- /* do we still have anything to map */
- sz = sz - law_sz;
- if (sz)
- return 1;
-
- return 0;
-}
-#endif
-
-void init_laws(void)
-{
- int i;
-
-#if FSL_HW_NUM_LAWS < 32
- gd->used_laws = ~((1 << FSL_HW_NUM_LAWS) - 1);
-#elif FSL_HW_NUM_LAWS == 32
- gd->used_laws = 0;
-#else
-#error FSL_HW_NUM_LAWS can not be greater than 32 w/o code changes
-#endif
-
- /*
- * Any LAWs that were set up before we booted assume they are meant to
- * be around and mark them used.
- */
- for (i = 0; i < FSL_HW_NUM_LAWS; i++) {
- u32 lawar = in_be32(LAWAR_ADDR(i));
-
- if (lawar & LAW_EN)
- gd->used_laws |= (1 << i);
- }
-
-#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
- /*
- * in NAND boot we've already parsed the law_table and setup those LAWs
- * so don't do it again.
- */
- return;
-#endif
-
- for (i = 0; i < num_law_entries; i++) {
- if (law_table[i].index == -1)
- set_next_law(law_table[i].addr, law_table[i].size,
- law_table[i].trgt_id);
- else
- set_law(law_table[i].index, law_table[i].addr,
- law_table[i].size, law_table[i].trgt_id);
- }
-
-#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
- /* check RCW to get which port is used for boot */
- ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
- u32 bootloc = in_be32(&gur->rcwsr[6]);
- /*
- * in SRIO or PCIE boot we need to set specail LAWs for
- * SRIO or PCIE interfaces.
- */
- switch ((bootloc & FSL_CORENET_RCWSR6_BOOT_LOC) >> 23) {
- case 0x0: /* boot from PCIE1 */
- set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
- LAW_SIZE_1M,
- LAW_TRGT_IF_PCIE_1);
- set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
- LAW_SIZE_1M,
- LAW_TRGT_IF_PCIE_1);
- break;
- case 0x1: /* boot from PCIE2 */
- set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
- LAW_SIZE_1M,
- LAW_TRGT_IF_PCIE_2);
- set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
- LAW_SIZE_1M,
- LAW_TRGT_IF_PCIE_2);
- break;
- case 0x2: /* boot from PCIE3 */
- set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
- LAW_SIZE_1M,
- LAW_TRGT_IF_PCIE_3);
- set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
- LAW_SIZE_1M,
- LAW_TRGT_IF_PCIE_3);
- break;
- case 0x8: /* boot from SRIO1 */
- set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
- LAW_SIZE_1M,
- LAW_TRGT_IF_RIO_1);
- set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
- LAW_SIZE_1M,
- LAW_TRGT_IF_RIO_1);
- break;
- case 0x9: /* boot from SRIO2 */
- set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
- LAW_SIZE_1M,
- LAW_TRGT_IF_RIO_2);
- set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
- LAW_SIZE_1M,
- LAW_TRGT_IF_RIO_2);
- break;
- default:
- break;
- }
-#endif
-
- return ;
-}
diff --git a/nand_spl/board/freescale/mpc8536ds/Makefile b/nand_spl/board/freescale/mpc8536ds/Makefile
index e5388d8..707273b 100644
--- a/nand_spl/board/freescale/mpc8536ds/Makefile
+++ b/nand_spl/board/freescale/mpc8536ds/Makefile
@@ -85,7 +85,7 @@ $(obj)cpu_init_nand.c:
$(obj)fsl_law.c:
@rm -f $(obj)fsl_law.c
- ln -sf $(SRCTREE)/drivers/misc/fsl_law.c $(obj)fsl_law.c
+ ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc8xxx/law.c $(obj)fsl_law.c
$(obj)law.c:
@rm -f $(obj)law.c
diff --git a/nand_spl/board/freescale/mpc8569mds/Makefile b/nand_spl/board/freescale/mpc8569mds/Makefile
index e5388d8..707273b 100644
--- a/nand_spl/board/freescale/mpc8569mds/Makefile
+++ b/nand_spl/board/freescale/mpc8569mds/Makefile
@@ -85,7 +85,7 @@ $(obj)cpu_init_nand.c:
$(obj)fsl_law.c:
@rm -f $(obj)fsl_law.c
- ln -sf $(SRCTREE)/drivers/misc/fsl_law.c $(obj)fsl_law.c
+ ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc8xxx/law.c $(obj)fsl_law.c
$(obj)law.c:
@rm -f $(obj)law.c
diff --git a/nand_spl/board/freescale/mpc8572ds/Makefile b/nand_spl/board/freescale/mpc8572ds/Makefile
index e5388d8..707273b 100644
--- a/nand_spl/board/freescale/mpc8572ds/Makefile
+++ b/nand_spl/board/freescale/mpc8572ds/Makefile
@@ -85,7 +85,7 @@ $(obj)cpu_init_nand.c:
$(obj)fsl_law.c:
@rm -f $(obj)fsl_law.c
- ln -sf $(SRCTREE)/drivers/misc/fsl_law.c $(obj)fsl_law.c
+ ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc8xxx/law.c $(obj)fsl_law.c
$(obj)law.c:
@rm -f $(obj)law.c
diff --git a/nand_spl/board/freescale/p1010rdb/Makefile b/nand_spl/board/freescale/p1010rdb/Makefile
index f270faa..bbf73c5 100644
--- a/nand_spl/board/freescale/p1010rdb/Makefile
+++ b/nand_spl/board/freescale/p1010rdb/Makefile
@@ -86,7 +86,7 @@ $(obj)cpu_init_nand.c:
$(obj)fsl_law.c:
@rm -f $(obj)fsl_law.c
- ln -sf $(SRCTREE)/drivers/misc/fsl_law.c $(obj)fsl_law.c
+ ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc8xxx/law.c $(obj)fsl_law.c
$(obj)law.c:
@rm -f $(obj)law.c
diff --git a/nand_spl/board/freescale/p1023rds/Makefile b/nand_spl/board/freescale/p1023rds/Makefile
index b2882844..d7e95df 100644
--- a/nand_spl/board/freescale/p1023rds/Makefile
+++ b/nand_spl/board/freescale/p1023rds/Makefile
@@ -81,7 +81,7 @@ $(obj)cpu_init_nand.c:
$(obj)fsl_law.c:
@rm -f $(obj)fsl_law.c
- ln -sf $(SRCTREE)/drivers/misc/fsl_law.c $(obj)fsl_law.c
+ ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc8xxx/law.c $(obj)fsl_law.c
$(obj)law.c:
@rm -f $(obj)law.c
diff --git a/nand_spl/board/freescale/p1_p2_rdb/Makefile b/nand_spl/board/freescale/p1_p2_rdb/Makefile
index e5388d8..707273b 100644
--- a/nand_spl/board/freescale/p1_p2_rdb/Makefile
+++ b/nand_spl/board/freescale/p1_p2_rdb/Makefile
@@ -85,7 +85,7 @@ $(obj)cpu_init_nand.c:
$(obj)fsl_law.c:
@rm -f $(obj)fsl_law.c
- ln -sf $(SRCTREE)/drivers/misc/fsl_law.c $(obj)fsl_law.c
+ ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc8xxx/law.c $(obj)fsl_law.c
$(obj)law.c:
@rm -f $(obj)law.c
diff --git a/nand_spl/board/freescale/p1_p2_rdb_pc/Makefile b/nand_spl/board/freescale/p1_p2_rdb_pc/Makefile
index 7146d16..481d1d9 100644
--- a/nand_spl/board/freescale/p1_p2_rdb_pc/Makefile
+++ b/nand_spl/board/freescale/p1_p2_rdb_pc/Makefile
@@ -86,7 +86,7 @@ $(obj)cpu_init_nand.c:
$(obj)fsl_law.c:
@rm -f $(obj)fsl_law.c
- ln -sf $(SRCTREE)/drivers/misc/fsl_law.c $(obj)fsl_law.c
+ ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc8xxx/law.c $(obj)fsl_law.c
$(obj)law.c:
@rm -f $(obj)law.c
--
1.7.9.5
^ permalink raw reply related [flat|nested] 81+ messages in thread* [U-Boot] [PATCH v2 11/22] spl/mpc85xx: move udelay to cpu code
2012-10-30 2:04 ` [U-Boot] [PATCH v2 00/22] " Scott Wood
` (9 preceding siblings ...)
2012-10-30 2:04 ` [U-Boot] [PATCH v2 10/22] powerpc/mpc8xxx: move LAW code into arch/powerpc/cpu/mpc8xxx Scott Wood
@ 2012-10-30 2:04 ` Scott Wood
2012-10-30 2:05 ` [U-Boot] [PATCH v2 12/22] spl: include resetvec and lib8xxx Scott Wood
` (11 subsequent siblings)
22 siblings, 0 replies; 81+ messages in thread
From: Scott Wood @ 2012-10-30 2:04 UTC (permalink / raw)
To: u-boot
It applies to non-Freescale 85xx boards as well as Freescale boards,
so it doesn't belong in board/freescale. Plus, it needs to come out
of nand_spl if it's to be used by the new SPL.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Cc: Andy Fleming <afleming@freescale.com>
---
arch/powerpc/cpu/mpc85xx/cpu_init_nand.c | 17 ++++++++++
nand_spl/board/freescale/common.c | 40 ------------------------
nand_spl/board/freescale/p1010rdb/Makefile | 6 +---
nand_spl/board/freescale/p1023rds/Makefile | 6 +---
nand_spl/board/freescale/p1_p2_rdb_pc/Makefile | 6 +---
5 files changed, 20 insertions(+), 55 deletions(-)
delete mode 100644 nand_spl/board/freescale/common.c
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c b/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c
index bf7a6f6..0589497 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c
@@ -21,9 +21,13 @@
*/
#include <common.h>
+#include <asm/processor.h>
+#include <asm/global_data.h>
#include <asm/fsl_ifc.h>
#include <asm/io.h>
+DECLARE_GLOBAL_DATA_PTR;
+
void cpu_init_f(void)
{
#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
@@ -40,3 +44,16 @@ void cpu_init_f(void)
(MPC85xx_L2CTL_L2E | MPC85xx_L2CTL_L2SRAM_ENTIRE));
#endif
}
+
+#ifndef CONFIG_SYS_FSL_TBCLK_DIV
+#define CONFIG_SYS_FSL_TBCLK_DIV 8
+#endif
+
+void udelay(unsigned long usec)
+{
+ u32 ticks_per_usec = gd->bus_clk / (CONFIG_SYS_FSL_TBCLK_DIV * 1000000);
+ u32 ticks = ticks_per_usec * usec;
+ u32 s = mfspr(SPRN_TBRL);
+
+ while ((mfspr(SPRN_TBRL) - s) < ticks);
+}
diff --git a/nand_spl/board/freescale/common.c b/nand_spl/board/freescale/common.c
deleted file mode 100644
index 0e099bc..0000000
--- a/nand_spl/board/freescale/common.c
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * Copyright 2012 Freescale Semiconductor, Inc.
- * Author: Matthew McClintock <msm@freescale.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- *
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- */
-
-#include <common.h>
-#include <asm/processor.h>
-#include <asm/global_data.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifndef CONFIG_SYS_FSL_TBCLK_DIV
-#define CONFIG_SYS_FSL_TBCLK_DIV 8
-#endif
-
-void udelay(unsigned long usec)
-{
- u32 ticks_per_usec = gd->bus_clk / (CONFIG_SYS_FSL_TBCLK_DIV * 1000000);
- u32 ticks = ticks_per_usec * usec;
- u32 s = mfspr(SPRN_TBRL);
-
- while ((mfspr(SPRN_TBRL) - s) < ticks);
-}
diff --git a/nand_spl/board/freescale/p1010rdb/Makefile b/nand_spl/board/freescale/p1010rdb/Makefile
index bbf73c5..187ff4e 100644
--- a/nand_spl/board/freescale/p1010rdb/Makefile
+++ b/nand_spl/board/freescale/p1010rdb/Makefile
@@ -40,8 +40,7 @@ CFLAGS += -DCONFIG_NAND_SPL
SOBJS = start.o resetvec.o ticks.o
COBJS = cache.o cpu_init_early.o cpu_init_nand.o fsl_law.o law.o \
- nand_boot.o nand_boot_fsl_ifc.o ns16550.o tlb.o tlb_table.o \
- ../common.o
+ nand_boot.o nand_boot_fsl_ifc.o ns16550.o tlb.o tlb_table.o
SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
@@ -129,9 +128,6 @@ ifneq ($(OBJTREE), $(SRCTREE))
$(obj)nand_boot.c:
@rm -f $(obj)nand_boot.c
ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $(obj)nand_boot.c
-$(obj)../common.c:
- @rm -f $(obj)../common.c
- ln -s $(SRCTREE)/nand_spl/board/freescale/common.c $(obj)../common.c
endif
#########################################################################
diff --git a/nand_spl/board/freescale/p1023rds/Makefile b/nand_spl/board/freescale/p1023rds/Makefile
index d7e95df..60fdd90 100644
--- a/nand_spl/board/freescale/p1023rds/Makefile
+++ b/nand_spl/board/freescale/p1023rds/Makefile
@@ -35,8 +35,7 @@ CFLAGS += -DCONFIG_NAND_SPL
SOBJS = start.o resetvec.o
COBJS = cache.o cpu_init_early.o cpu_init_nand.o fsl_law.o law.o \
- nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o \
- ../common.o
+ nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o
SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
@@ -120,9 +119,6 @@ ifneq ($(OBJTREE), $(SRCTREE))
$(obj)nand_boot.c:
@rm -f $(obj)nand_boot.c
ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $(obj)nand_boot.c
-$(obj)../common.c:
- @rm -f $(obj)../common.c
- ln -s $(SRCTREE)/nand_spl/board/freescale/common.c $(obj)../common.c
endif
#########################################################################
diff --git a/nand_spl/board/freescale/p1_p2_rdb_pc/Makefile b/nand_spl/board/freescale/p1_p2_rdb_pc/Makefile
index 481d1d9..98d3ad0 100644
--- a/nand_spl/board/freescale/p1_p2_rdb_pc/Makefile
+++ b/nand_spl/board/freescale/p1_p2_rdb_pc/Makefile
@@ -40,8 +40,7 @@ CFLAGS += -DCONFIG_NAND_SPL
SOBJS = start.o resetvec.o
COBJS = cache.o cpu_init_early.o cpu_init_nand.o fsl_law.o law.o \
- nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o \
- ../common.o
+ nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o
SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
@@ -125,9 +124,6 @@ ifneq ($(OBJTREE), $(SRCTREE))
$(obj)nand_boot.c:
@rm -f $(obj)nand_boot.c
ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $(obj)nand_boot.c
-$(obj)../common.c:
- @rm -f $(obj)../common.c
- ln -s $(SRCTREE)/nand_spl/board/freescale/common.c $(obj)../common.c
endif
#########################################################################
--
1.7.9.5
^ permalink raw reply related [flat|nested] 81+ messages in thread* [U-Boot] [PATCH v2 12/22] spl: include resetvec and lib8xxx
2012-10-30 2:04 ` [U-Boot] [PATCH v2 00/22] " Scott Wood
` (10 preceding siblings ...)
2012-10-30 2:04 ` [U-Boot] [PATCH v2 11/22] spl/mpc85xx: move udelay to cpu code Scott Wood
@ 2012-10-30 2:05 ` Scott Wood
2012-10-30 2:05 ` [U-Boot] [PATCH v2 13/22] spl/mpc85xx: rename cpu_init_nand.c to spl_minimal.c Scott Wood
` (10 subsequent siblings)
22 siblings, 0 replies; 81+ messages in thread
From: Scott Wood @ 2012-10-30 2:05 UTC (permalink / raw)
To: u-boot
The toplevel makefile hardcodes this stuff, so spl/Makefile needs to as well.
Signed-off-by: Scott Wood <scottwood@freescale.com>
---
spl/Makefile | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/spl/Makefile b/spl/Makefile
index 3195390..eacf4a2 100644
--- a/spl/Makefile
+++ b/spl/Makefile
@@ -32,9 +32,30 @@ START_PATH := $(CPUDIR)
endif
START := $(START_PATH)/start.o
+ifeq ($(CPU),x86)
+START += $(START_PATH)/start16.o
+START += $(START_PATH)/resetvec.o
+endif
+ifeq ($(CPU),ppc4xx)
+START += $(START_PATH)/resetvec.o
+endif
+ifeq ($(CPU),mpc85xx)
+START += $(START_PATH)/resetvec.o
+endif
LIBS-y += arch/$(ARCH)/lib/lib$(ARCH).o
+
LIBS-y += $(CPUDIR)/lib$(CPU).o
+ifeq ($(CPU),mpc83xx)
+LIBS-y += arch/powerpc/cpu/mpc8xxx/lib8xxx.o
+endif
+ifeq ($(CPU),mpc85xx)
+LIBS-y += arch/powerpc/cpu/mpc8xxx/lib8xxx.o
+endif
+ifeq ($(CPU),mpc86xx)
+LIBS-y += arch/powerpc/cpu/mpc8xxx/lib8xxx.o
+endif
+
ifdef SOC
LIBS-y += $(CPUDIR)/$(SOC)/lib$(SOC).o
endif
--
1.7.9.5
^ permalink raw reply related [flat|nested] 81+ messages in thread* [U-Boot] [PATCH v2 13/22] spl/mpc85xx: rename cpu_init_nand.c to spl_minimal.c
2012-10-30 2:04 ` [U-Boot] [PATCH v2 00/22] " Scott Wood
` (11 preceding siblings ...)
2012-10-30 2:05 ` [U-Boot] [PATCH v2 12/22] spl: include resetvec and lib8xxx Scott Wood
@ 2012-10-30 2:05 ` Scott Wood
2012-10-30 2:05 ` [U-Boot] [PATCH v2 14/22] powerpc/mpc85xx: consistently use COBJS-y Scott Wood
` (9 subsequent siblings)
22 siblings, 0 replies; 81+ messages in thread
From: Scott Wood @ 2012-10-30 2:05 UTC (permalink / raw)
To: u-boot
There is nothing really NAND-specific about this file.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Cc: Andy Fleming <afleming@freescale.com>
---
arch/powerpc/cpu/mpc85xx/cpu_init_nand.c | 59 ------------------------
arch/powerpc/cpu/mpc85xx/spl_minimal.c | 59 ++++++++++++++++++++++++
nand_spl/board/freescale/mpc8536ds/Makefile | 8 ++--
nand_spl/board/freescale/mpc8569mds/Makefile | 8 ++--
nand_spl/board/freescale/mpc8572ds/Makefile | 8 ++--
nand_spl/board/freescale/p1010rdb/Makefile | 8 ++--
nand_spl/board/freescale/p1023rds/Makefile | 8 ++--
nand_spl/board/freescale/p1_p2_rdb/Makefile | 8 ++--
nand_spl/board/freescale/p1_p2_rdb_pc/Makefile | 8 ++--
9 files changed, 87 insertions(+), 87 deletions(-)
delete mode 100644 arch/powerpc/cpu/mpc85xx/cpu_init_nand.c
create mode 100644 arch/powerpc/cpu/mpc85xx/spl_minimal.c
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c b/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c
deleted file mode 100644
index 0589497..0000000
--- a/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * Copyright 2009 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/processor.h>
-#include <asm/global_data.h>
-#include <asm/fsl_ifc.h>
-#include <asm/io.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void cpu_init_f(void)
-{
-#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
- ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
-
- out_be32(&l2cache->l2srbar0, CONFIG_SYS_INIT_L2_ADDR);
-
- /* set MBECCDIS=1, SBECCDIS=1 */
- out_be32(&l2cache->l2errdis,
- (MPC85xx_L2ERRDIS_MBECC | MPC85xx_L2ERRDIS_SBECC));
-
- /* set L2E=1 & L2SRAM=001 */
- out_be32(&l2cache->l2ctl,
- (MPC85xx_L2CTL_L2E | MPC85xx_L2CTL_L2SRAM_ENTIRE));
-#endif
-}
-
-#ifndef CONFIG_SYS_FSL_TBCLK_DIV
-#define CONFIG_SYS_FSL_TBCLK_DIV 8
-#endif
-
-void udelay(unsigned long usec)
-{
- u32 ticks_per_usec = gd->bus_clk / (CONFIG_SYS_FSL_TBCLK_DIV * 1000000);
- u32 ticks = ticks_per_usec * usec;
- u32 s = mfspr(SPRN_TBRL);
-
- while ((mfspr(SPRN_TBRL) - s) < ticks);
-}
diff --git a/arch/powerpc/cpu/mpc85xx/spl_minimal.c b/arch/powerpc/cpu/mpc85xx/spl_minimal.c
new file mode 100644
index 0000000..0589497
--- /dev/null
+++ b/arch/powerpc/cpu/mpc85xx/spl_minimal.c
@@ -0,0 +1,59 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/global_data.h>
+#include <asm/fsl_ifc.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void cpu_init_f(void)
+{
+#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
+ ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
+
+ out_be32(&l2cache->l2srbar0, CONFIG_SYS_INIT_L2_ADDR);
+
+ /* set MBECCDIS=1, SBECCDIS=1 */
+ out_be32(&l2cache->l2errdis,
+ (MPC85xx_L2ERRDIS_MBECC | MPC85xx_L2ERRDIS_SBECC));
+
+ /* set L2E=1 & L2SRAM=001 */
+ out_be32(&l2cache->l2ctl,
+ (MPC85xx_L2CTL_L2E | MPC85xx_L2CTL_L2SRAM_ENTIRE));
+#endif
+}
+
+#ifndef CONFIG_SYS_FSL_TBCLK_DIV
+#define CONFIG_SYS_FSL_TBCLK_DIV 8
+#endif
+
+void udelay(unsigned long usec)
+{
+ u32 ticks_per_usec = gd->bus_clk / (CONFIG_SYS_FSL_TBCLK_DIV * 1000000);
+ u32 ticks = ticks_per_usec * usec;
+ u32 s = mfspr(SPRN_TBRL);
+
+ while ((mfspr(SPRN_TBRL) - s) < ticks);
+}
diff --git a/nand_spl/board/freescale/mpc8536ds/Makefile b/nand_spl/board/freescale/mpc8536ds/Makefile
index 707273b..c923557 100644
--- a/nand_spl/board/freescale/mpc8536ds/Makefile
+++ b/nand_spl/board/freescale/mpc8536ds/Makefile
@@ -39,7 +39,7 @@ AFLAGS += -DCONFIG_NAND_SPL
CFLAGS += -DCONFIG_NAND_SPL
SOBJS = start.o resetvec.o
-COBJS = cache.o cpu_init_early.o cpu_init_nand.o fsl_law.o law.o \
+COBJS = cache.o cpu_init_early.o spl_minimal.o fsl_law.o law.o \
nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o
SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
@@ -79,9 +79,9 @@ $(obj)cpu_init_early.c:
@rm -f $(obj)cpu_init_early.c
ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/cpu_init_early.c $(obj)cpu_init_early.c
-$(obj)cpu_init_nand.c:
- @rm -f $(obj)cpu_init_nand.c
- ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c $(obj)cpu_init_nand.c
+$(obj)spl_minimal.c:
+ @rm -f $(obj)spl_minimal.c
+ ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/spl_minimal.c $(obj)spl_minimal.c
$(obj)fsl_law.c:
@rm -f $(obj)fsl_law.c
diff --git a/nand_spl/board/freescale/mpc8569mds/Makefile b/nand_spl/board/freescale/mpc8569mds/Makefile
index 707273b..c923557 100644
--- a/nand_spl/board/freescale/mpc8569mds/Makefile
+++ b/nand_spl/board/freescale/mpc8569mds/Makefile
@@ -39,7 +39,7 @@ AFLAGS += -DCONFIG_NAND_SPL
CFLAGS += -DCONFIG_NAND_SPL
SOBJS = start.o resetvec.o
-COBJS = cache.o cpu_init_early.o cpu_init_nand.o fsl_law.o law.o \
+COBJS = cache.o cpu_init_early.o spl_minimal.o fsl_law.o law.o \
nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o
SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
@@ -79,9 +79,9 @@ $(obj)cpu_init_early.c:
@rm -f $(obj)cpu_init_early.c
ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/cpu_init_early.c $(obj)cpu_init_early.c
-$(obj)cpu_init_nand.c:
- @rm -f $(obj)cpu_init_nand.c
- ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c $(obj)cpu_init_nand.c
+$(obj)spl_minimal.c:
+ @rm -f $(obj)spl_minimal.c
+ ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/spl_minimal.c $(obj)spl_minimal.c
$(obj)fsl_law.c:
@rm -f $(obj)fsl_law.c
diff --git a/nand_spl/board/freescale/mpc8572ds/Makefile b/nand_spl/board/freescale/mpc8572ds/Makefile
index 707273b..c923557 100644
--- a/nand_spl/board/freescale/mpc8572ds/Makefile
+++ b/nand_spl/board/freescale/mpc8572ds/Makefile
@@ -39,7 +39,7 @@ AFLAGS += -DCONFIG_NAND_SPL
CFLAGS += -DCONFIG_NAND_SPL
SOBJS = start.o resetvec.o
-COBJS = cache.o cpu_init_early.o cpu_init_nand.o fsl_law.o law.o \
+COBJS = cache.o cpu_init_early.o spl_minimal.o fsl_law.o law.o \
nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o
SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
@@ -79,9 +79,9 @@ $(obj)cpu_init_early.c:
@rm -f $(obj)cpu_init_early.c
ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/cpu_init_early.c $(obj)cpu_init_early.c
-$(obj)cpu_init_nand.c:
- @rm -f $(obj)cpu_init_nand.c
- ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c $(obj)cpu_init_nand.c
+$(obj)spl_minimal.c:
+ @rm -f $(obj)spl_minimal.c
+ ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/spl_minimal.c $(obj)spl_minimal.c
$(obj)fsl_law.c:
@rm -f $(obj)fsl_law.c
diff --git a/nand_spl/board/freescale/p1010rdb/Makefile b/nand_spl/board/freescale/p1010rdb/Makefile
index 187ff4e..ccff1c7 100644
--- a/nand_spl/board/freescale/p1010rdb/Makefile
+++ b/nand_spl/board/freescale/p1010rdb/Makefile
@@ -39,7 +39,7 @@ AFLAGS += -DCONFIG_NAND_SPL
CFLAGS += -DCONFIG_NAND_SPL
SOBJS = start.o resetvec.o ticks.o
-COBJS = cache.o cpu_init_early.o cpu_init_nand.o fsl_law.o law.o \
+COBJS = cache.o cpu_init_early.o spl_minimal.o fsl_law.o law.o \
nand_boot.o nand_boot_fsl_ifc.o ns16550.o tlb.o tlb_table.o
SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
@@ -79,9 +79,9 @@ $(obj)cpu_init_early.c:
@rm -f $(obj)cpu_init_early.c
ln -sf $(SRCTREE)/$(CPUDIR)/cpu_init_early.c $(obj)cpu_init_early.c
-$(obj)cpu_init_nand.c:
- @rm -f $(obj)cpu_init_nand.c
- ln -sf $(SRCTREE)/$(CPUDIR)/cpu_init_nand.c $(obj)cpu_init_nand.c
+$(obj)spl_minimal.c:
+ @rm -f $(obj)spl_minimal.c
+ ln -sf $(SRCTREE)/$(CPUDIR)/spl_minimal.c $(obj)spl_minimal.c
$(obj)fsl_law.c:
@rm -f $(obj)fsl_law.c
diff --git a/nand_spl/board/freescale/p1023rds/Makefile b/nand_spl/board/freescale/p1023rds/Makefile
index 60fdd90..ffe29c8 100644
--- a/nand_spl/board/freescale/p1023rds/Makefile
+++ b/nand_spl/board/freescale/p1023rds/Makefile
@@ -34,7 +34,7 @@ AFLAGS += -DCONFIG_NAND_SPL
CFLAGS += -DCONFIG_NAND_SPL
SOBJS = start.o resetvec.o
-COBJS = cache.o cpu_init_early.o cpu_init_nand.o fsl_law.o law.o \
+COBJS = cache.o cpu_init_early.o spl_minimal.o fsl_law.o law.o \
nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o
SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
@@ -74,9 +74,9 @@ $(obj)cpu_init_early.c:
@rm -f $(obj)cpu_init_early.c
ln -sf $(SRCTREE)/$(CPUDIR)/cpu_init_early.c $(obj)cpu_init_early.c
-$(obj)cpu_init_nand.c:
- @rm -f $(obj)cpu_init_nand.c
- ln -sf $(SRCTREE)/$(CPUDIR)/cpu_init_nand.c $(obj)cpu_init_nand.c
+$(obj)spl_minimal.c:
+ @rm -f $(obj)spl_minimal.c
+ ln -sf $(SRCTREE)/$(CPUDIR)/spl_minimal.c $(obj)spl_minimal.c
$(obj)fsl_law.c:
@rm -f $(obj)fsl_law.c
diff --git a/nand_spl/board/freescale/p1_p2_rdb/Makefile b/nand_spl/board/freescale/p1_p2_rdb/Makefile
index 707273b..c923557 100644
--- a/nand_spl/board/freescale/p1_p2_rdb/Makefile
+++ b/nand_spl/board/freescale/p1_p2_rdb/Makefile
@@ -39,7 +39,7 @@ AFLAGS += -DCONFIG_NAND_SPL
CFLAGS += -DCONFIG_NAND_SPL
SOBJS = start.o resetvec.o
-COBJS = cache.o cpu_init_early.o cpu_init_nand.o fsl_law.o law.o \
+COBJS = cache.o cpu_init_early.o spl_minimal.o fsl_law.o law.o \
nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o
SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
@@ -79,9 +79,9 @@ $(obj)cpu_init_early.c:
@rm -f $(obj)cpu_init_early.c
ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/cpu_init_early.c $(obj)cpu_init_early.c
-$(obj)cpu_init_nand.c:
- @rm -f $(obj)cpu_init_nand.c
- ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c $(obj)cpu_init_nand.c
+$(obj)spl_minimal.c:
+ @rm -f $(obj)spl_minimal.c
+ ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/spl_minimal.c $(obj)spl_minimal.c
$(obj)fsl_law.c:
@rm -f $(obj)fsl_law.c
diff --git a/nand_spl/board/freescale/p1_p2_rdb_pc/Makefile b/nand_spl/board/freescale/p1_p2_rdb_pc/Makefile
index 98d3ad0..797a800 100644
--- a/nand_spl/board/freescale/p1_p2_rdb_pc/Makefile
+++ b/nand_spl/board/freescale/p1_p2_rdb_pc/Makefile
@@ -39,7 +39,7 @@ AFLAGS += -DCONFIG_NAND_SPL
CFLAGS += -DCONFIG_NAND_SPL
SOBJS = start.o resetvec.o
-COBJS = cache.o cpu_init_early.o cpu_init_nand.o fsl_law.o law.o \
+COBJS = cache.o cpu_init_early.o spl_minimal.o fsl_law.o law.o \
nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o
SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
@@ -79,9 +79,9 @@ $(obj)cpu_init_early.c:
@rm -f $(obj)cpu_init_early.c
ln -sf $(SRCTREE)/$(CPUDIR)/cpu_init_early.c $(obj)cpu_init_early.c
-$(obj)cpu_init_nand.c:
- @rm -f $(obj)cpu_init_nand.c
- ln -sf $(SRCTREE)/$(CPUDIR)/cpu_init_nand.c $(obj)cpu_init_nand.c
+$(obj)spl_minimal.c:
+ @rm -f $(obj)spl_minimal.c
+ ln -sf $(SRCTREE)/$(CPUDIR)/spl_minimal.c $(obj)spl_minimal.c
$(obj)fsl_law.c:
@rm -f $(obj)fsl_law.c
--
1.7.9.5
^ permalink raw reply related [flat|nested] 81+ messages in thread* [U-Boot] [PATCH v2 14/22] powerpc/mpc85xx: consistently use COBJS-y
2012-10-30 2:04 ` [U-Boot] [PATCH v2 00/22] " Scott Wood
` (12 preceding siblings ...)
2012-10-30 2:05 ` [U-Boot] [PATCH v2 13/22] spl/mpc85xx: rename cpu_init_nand.c to spl_minimal.c Scott Wood
@ 2012-10-30 2:05 ` Scott Wood
2012-10-30 2:05 ` [U-Boot] [PATCH v2 15/22] spl/powerpc: introduce CONFIG_SPL_INIT_MINIMAL Scott Wood
` (8 subsequent siblings)
22 siblings, 0 replies; 81+ messages in thread
From: Scott Wood @ 2012-10-30 2:05 UTC (permalink / raw)
To: u-boot
A subsequent patch will conditionalize some of the files that are
currently unconditional.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Cc: Andy Fleming <afleming@freescale.com>
---
arch/powerpc/cpu/mpc85xx/Makefile | 19 ++++++++++---------
1 file changed, 10 insertions(+), 9 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile
index 78c412d..a7dbfa7 100644
--- a/arch/powerpc/cpu/mpc85xx/Makefile
+++ b/arch/powerpc/cpu/mpc85xx/Makefile
@@ -121,17 +121,18 @@ COBJS-$(CONFIG_PPC_P5040) += p5040_serdes.o
COBJS-$(CONFIG_PPC_T4240) += t4240_serdes.o
COBJS-$(CONFIG_PPC_B4860) += b4860_serdes.o
-COBJS = $(COBJS-y)
-COBJS += cpu.o
-COBJS += cpu_init.o
-COBJS += cpu_init_early.o
-COBJS += interrupts.o
-COBJS += speed.o
-COBJS += tlb.o
-COBJS += traps.o
+COBJS-y += cpu.o
+COBJS-y += cpu_init.o
+COBJS-y += cpu_init_early.o
+COBJS-y += interrupts.o
+COBJS-y += speed.o
+COBJS-y += tlb.o
+COBJS-y += traps.o
# Stub implementations of cache management functions for USB
-COBJS += cache.o
+COBJS-y += cache.o
+
+COBJS = $(COBJS-y)
SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
--
1.7.9.5
^ permalink raw reply related [flat|nested] 81+ messages in thread* [U-Boot] [PATCH v2 15/22] spl/powerpc: introduce CONFIG_SPL_INIT_MINIMAL
2012-10-30 2:04 ` [U-Boot] [PATCH v2 00/22] " Scott Wood
` (13 preceding siblings ...)
2012-10-30 2:05 ` [U-Boot] [PATCH v2 14/22] powerpc/mpc85xx: consistently use COBJS-y Scott Wood
@ 2012-10-30 2:05 ` Scott Wood
2012-10-30 2:05 ` [U-Boot] [PATCH v2 16/22] spl/85xx: new SPL support Scott Wood
` (7 subsequent siblings)
22 siblings, 0 replies; 81+ messages in thread
From: Scott Wood @ 2012-10-30 2:05 UTC (permalink / raw)
To: u-boot
cpu_init_nand.c is renamed to spl_minimal.c as it is not really NAND-specific.
Signed-off-by: Scott Wood <scottwood@freescale.com>
---
v2: factor out START, and change cpu_init_nand.c to spl_minimal.c
Cc: Andy Fleming <afleming@freescale.com>
---
README | 3 +++
arch/powerpc/cpu/mpc85xx/Makefile | 19 ++++++++++++++++++-
arch/powerpc/cpu/mpc85xx/start.S | 33 ++++++++++++++++++++-------------
arch/powerpc/cpu/mpc8xxx/Makefile | 16 ++++++++++++++++
arch/powerpc/lib/Makefile | 17 ++++++++++++++++-
5 files changed, 73 insertions(+), 15 deletions(-)
diff --git a/README b/README
index 4294c2e..cf83c47 100644
--- a/README
+++ b/README
@@ -2657,6 +2657,9 @@ FIT uImage format:
For ARM, enable an optional function to print more information
about the running system.
+ CONFIG_SPL_INIT_MINIMAL
+ Arch init code should be built for a very small image
+
CONFIG_SPL_LIBCOMMON_SUPPORT
Support for common/libcommon.o in SPL binary
diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile
index a7dbfa7..4c2b104 100644
--- a/arch/powerpc/cpu/mpc85xx/Makefile
+++ b/arch/powerpc/cpu/mpc85xx/Makefile
@@ -28,7 +28,22 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(CPU).o
-START = start.o resetvec.o
+MINIMAL=
+
+ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_SPL_INIT_MINIMAL
+MINIMAL=y
+endif
+endif
+
+START = start.o resetvec.o
+
+ifdef MINIMAL
+
+COBJS-y += cpu_init_early.o tlb.o spl_minimal.o
+
+else
+
SOBJS-$(CONFIG_MP) += release.o
SOBJS = $(SOBJS-y)
@@ -132,6 +147,8 @@ COBJS-y += traps.o
# Stub implementations of cache management functions for USB
COBJS-y += cache.o
+endif # not minimal
+
COBJS = $(COBJS-y)
SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index 577d687..bb0dc1a 100644
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -44,6 +44,15 @@
#undef MSR_KERNEL
#define MSR_KERNEL ( MSR_ME ) /* Machine Check */
+#if defined(CONFIG_NAND_SPL) || \
+ (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL))
+#define MINIMAL_SPL
+#endif
+
+#if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SECURE_BOOT)
+#define NOR_BOOT
+#endif
+
/*
* Set up GOT: Global Offset Table
*
@@ -53,7 +62,7 @@
GOT_ENTRY(_GOT2_TABLE_)
GOT_ENTRY(_FIXUP_TABLE_)
-#ifndef CONFIG_NAND_SPL
+#ifndef MINIMAL_SPL
GOT_ENTRY(_start)
GOT_ENTRY(_start_of_vectors)
GOT_ENTRY(_end_of_vectors)
@@ -282,11 +291,8 @@ l2_disabled:
isync
.endm
-/*
- * Ne need to setup interrupt vector for NAND SPL
- * because NAND SPL never compiles it.
- */
-#if !defined(CONFIG_NAND_SPL)
+/* Interrupt vectors do not fit in minimal SPL. */
+#if !defined(MINIMAL_SPL)
/* Setup interrupt vectors */
lis r1,CONFIG_SYS_MONITOR_BASE at h
mtspr IVPR,r1
@@ -518,7 +524,7 @@ nexti: mflr r1 /* R1 = our PC */
* in AS1.
*/
-#if !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SECURE_BOOT)
+#ifdef NOR_BOOT
/*
* TLB entry is created for IVPR + IVOR15 to map on valid OP code address
* bacause flash's virtual address maps to 0xff800000 - 0xffffffff.
@@ -1032,7 +1038,7 @@ create_init_ram_area:
lis r6,FSL_BOOKE_MAS0(1, 15, 0)@h
ori r6,r6,FSL_BOOKE_MAS0(1, 15, 0)@l
-#if !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SECURE_BOOT)
+#ifdef NOR_BOOT
/* create a temp mapping in AS=1 to the 4M boot window */
create_tlb1_entry 15, \
1, BOOKE_PAGESZ_4M, \
@@ -1107,7 +1113,8 @@ switch_as:
bdnz 1b
/* Jump out the last 4K page and continue to 'normal' start */
-#ifdef CONFIG_SYS_RAMBOOT
+#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)
+ /* We assume that we're already running at the address we're linked at */
b _start_cont
#else
/* Calculate absolute address in FLASH and jump there */
@@ -1153,7 +1160,7 @@ _start_cont:
/* NOTREACHED - board_init_f() does not return */
-#ifndef CONFIG_NAND_SPL
+#ifndef MINIMAL_SPL
. = EXC_OFF_SYS_RESET
.globl _start_of_vectors
_start_of_vectors:
@@ -1597,7 +1604,7 @@ in32:
in32r:
lwbrx r3,r0,r3
blr
-#endif /* !CONFIG_NAND_SPL */
+#endif /* !MINIMAL_SPL */
/*------------------------------------------------------------------------------*/
@@ -1794,7 +1801,7 @@ clear_bss:
mr r4,r10 /* Destination Address */
bl board_init_r
-#ifndef CONFIG_NAND_SPL
+#ifndef MINIMAL_SPL
/*
* Copy exception vector code to low memory
*
@@ -1967,4 +1974,4 @@ setup_ivors:
#include "fixed_ivor.S"
blr
-#endif /* !CONFIG_NAND_SPL */
+#endif /* !MINIMAL_SPL */
diff --git a/arch/powerpc/cpu/mpc8xxx/Makefile b/arch/powerpc/cpu/mpc8xxx/Makefile
index 86344a7..3dc8e05 100644
--- a/arch/powerpc/cpu/mpc8xxx/Makefile
+++ b/arch/powerpc/cpu/mpc8xxx/Makefile
@@ -10,6 +10,20 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib8xxx.o
+MINIMAL=
+
+ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_SPL_INIT_MINIMAL
+MINIMAL=y
+endif
+endif
+
+ifdef MINIMAL
+
+COBJS-$(CONFIG_FSL_LAW) += law.o
+
+else
+
ifneq ($(CPU),mpc83xx)
COBJS-y += cpu.o
endif
@@ -20,6 +34,8 @@ COBJS-$(CONFIG_FSL_LBC) += fsl_lbc.o
COBJS-$(CONFIG_SYS_SRIO) += srio.o
COBJS-$(CONFIG_FSL_LAW) += law.o
+endif
+
SRCS := $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
diff --git a/arch/powerpc/lib/Makefile b/arch/powerpc/lib/Makefile
index 4a41635..20c5c38 100644
--- a/arch/powerpc/lib/Makefile
+++ b/arch/powerpc/lib/Makefile
@@ -38,8 +38,21 @@ endif
LIB = $(obj)lib$(ARCH).o
-SOBJS-y += ppccache.o
+MINIMAL=
+
+ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_SPL_INIT_MINIMAL
+MINIMAL=y
+endif
+endif
+
+ifdef MINIMAL
+COBJS-y += cache.o
+else
+
SOBJS-y += ppcstring.o
+
+SOBJS-y += ppccache.o
SOBJS-y += ticks.o
SOBJS-y += reloc.o
@@ -64,6 +77,8 @@ $(obj)ppcstring.o: AFLAGS += -Dmemcpy=__memcpy
COBJS-y += memcpy_mpc5200.o
endif
+endif # not minimal
+
COBJS += $(sort $(COBJS-y))
SRCS := $(GLSOBJS:.o=.S) $(GLCOBJS:.o=.c) \
--
1.7.9.5
^ permalink raw reply related [flat|nested] 81+ messages in thread* [U-Boot] [PATCH v2 16/22] spl/85xx: new SPL support
2012-10-30 2:04 ` [U-Boot] [PATCH v2 00/22] " Scott Wood
` (14 preceding siblings ...)
2012-10-30 2:05 ` [U-Boot] [PATCH v2 15/22] spl/powerpc: introduce CONFIG_SPL_INIT_MINIMAL Scott Wood
@ 2012-10-30 2:05 ` Scott Wood
2012-10-30 2:05 ` [U-Boot] [PATCH v2 17/22] powerpc/mpc85xx/p1_p2_rdb_pc: " Scott Wood
` (6 subsequent siblings)
22 siblings, 0 replies; 81+ messages in thread
From: Scott Wood @ 2012-10-30 2:05 UTC (permalink / raw)
To: u-boot
Update CONFIG_RAMBOOT and CONFIG_NAND_SPL references to accept CONFIG_SPL
and CONFIG_SPL_BUILD, respectively. CONFIG_NAND_SPL can be removed once
the last mpc85xx nand_spl target is gone.
CONFIG_RAMBOOT will need to remain for other use cases, but it doesn't
seem right to overload it for meaning SPL as well as nand_spl does. Even
if it's somewhat appropriate for the main u-boot, the SPL itself isn't
(necessarily) ramboot, and we don't have separate configs for SPL and
main u-boot. It was also inconsistent, as other platforms such as
mpc83xx didn't use CONFIG_RAMBOOT in this way.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Cc: Andy Fleming <afleming@freescale.com>
---
arch/powerpc/cpu/mpc85xx/cpu.c | 3 +-
arch/powerpc/cpu/mpc85xx/spl_minimal.c | 2 +-
arch/powerpc/cpu/mpc85xx/tlb.c | 4 +-
arch/powerpc/cpu/mpc85xx/u-boot-spl.lds | 87 +++++++++++++++++++++++++++++++
arch/powerpc/cpu/mpc8xxx/law.c | 11 ++--
doc/README.mpc85xx | 2 +-
6 files changed, 99 insertions(+), 10 deletions(-)
create mode 100644 arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index db232e6..78486aa 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -332,7 +332,8 @@ void mpc85xx_reginfo(void)
/* Common ddr init for non-corenet fsl 85xx platforms */
#ifndef CONFIG_FSL_CORENET
-#if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SYS_INIT_L2_ADDR)
+#if (defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)) && \
+ !defined(CONFIG_SYS_INIT_L2_ADDR)
phys_size_t initdram(int board_type)
{
#if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD)
diff --git a/arch/powerpc/cpu/mpc85xx/spl_minimal.c b/arch/powerpc/cpu/mpc85xx/spl_minimal.c
index 0589497..c6b9cd0 100644
--- a/arch/powerpc/cpu/mpc85xx/spl_minimal.c
+++ b/arch/powerpc/cpu/mpc85xx/spl_minimal.c
@@ -30,7 +30,7 @@ DECLARE_GLOBAL_DATA_PTR;
void cpu_init_f(void)
{
-#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
+#ifdef CONFIG_SYS_INIT_L2_ADDR
ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
out_be32(&l2cache->l2srbar0, CONFIG_SYS_INIT_L2_ADDR);
diff --git a/arch/powerpc/cpu/mpc85xx/tlb.c b/arch/powerpc/cpu/mpc85xx/tlb.c
index a548dec..f44fadc 100644
--- a/arch/powerpc/cpu/mpc85xx/tlb.c
+++ b/arch/powerpc/cpu/mpc85xx/tlb.c
@@ -55,7 +55,7 @@ void init_tlbs(void)
return ;
}
-#ifndef CONFIG_NAND_SPL
+#if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_SPL_BUILD)
void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn,
phys_addr_t *rpn)
{
@@ -332,4 +332,4 @@ void clear_ddr_tlbs(unsigned int memsize_in_meg)
}
-#endif /* !CONFIG_NAND_SPL */
+#endif /* not SPL */
diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
new file mode 100644
index 0000000..1c408e2
--- /dev/null
+++ b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
@@ -0,0 +1,87 @@
+/*
+ * (C) Copyright 2006
+ * Wolfgang Denk, DENX Software Engineering, wd at denx.de
+ *
+ * Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include "config.h" /* CONFIG_BOARDDIR */
+
+OUTPUT_ARCH(powerpc)
+SECTIONS
+{
+ . = CONFIG_SPL_TEXT_BASE;
+ .text : {
+ *(.text*)
+ }
+ _etext = .;
+
+ .reloc : {
+ _GOT2_TABLE_ = .;
+ KEEP(*(.got2))
+ KEEP(*(.got))
+ PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
+ _FIXUP_TABLE_ = .;
+ KEEP(*(.fixup))
+ }
+ __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
+ __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+ . = ALIGN(8);
+ .data : {
+ *(.rodata*)
+ *(.data*)
+ *(.sdata*)
+ }
+ _edata = .;
+
+ . = ALIGN(8);
+ __init_begin = .;
+ __init_end = .;
+/* FIXME for non-NAND SPL */
+#if defined(CONFIG_FSL_IFC) /* Restrict bootpg at 4K boundry for IFC */
+ .bootpg ADDR(.text) + 0x1000 :
+ {
+ start.o (.bootpg)
+ }
+#define RESET_VECTOR_OFFSET 0x1ffc /* IFC has 8K sram */
+#elif defined(CONFIG_FSL_ELBC)
+#define RESET_VECTOR_OFFSET 0xffc /* LBC has 4k sram */
+#else
+#error unknown NAND controller
+#endif
+ .resetvec ADDR(.text) + RESET_VECTOR_OFFSET : {
+ KEEP(*(.resetvec))
+ } = 0xffff
+
+ /*
+ * Make sure that the bss segment isn't linked at 0x0, otherwise its
+ * address won't be updated during relocation fixups.
+ */
+ . |= 0x10;
+
+ __bss_start = .;
+ .bss : {
+ *(.sbss*)
+ *(.bss*)
+ }
+ __bss_end__ = .;
+}
diff --git a/arch/powerpc/cpu/mpc8xxx/law.c b/arch/powerpc/cpu/mpc8xxx/law.c
index 223cd5d..ce1d71e 100644
--- a/arch/powerpc/cpu/mpc8xxx/law.c
+++ b/arch/powerpc/cpu/mpc8xxx/law.c
@@ -92,7 +92,7 @@ void disable_law(u8 idx)
return;
}
-#ifndef CONFIG_NAND_SPL
+#if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_SPL_BUILD)
static int get_law_entry(u8 i, struct law_entry *e)
{
u32 lawar;
@@ -122,7 +122,7 @@ int set_next_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id)
return idx;
}
-#ifndef CONFIG_NAND_SPL
+#if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_SPL_BUILD)
int set_last_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id)
{
u32 idx;
@@ -233,7 +233,7 @@ int set_ddr_laws(u64 start, u64 sz, enum law_trgt_if id)
return 0;
}
-#endif
+#endif /* not SPL */
void init_laws(void)
{
@@ -258,9 +258,10 @@ void init_laws(void)
gd->used_laws |= (1 << i);
}
-#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
+#if (defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)) || \
+ (defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD))
/*
- * in NAND boot we've already parsed the law_table and setup those LAWs
+ * in SPL boot we've already parsed the law_table and setup those LAWs
* so don't do it again.
*/
return;
diff --git a/doc/README.mpc85xx b/doc/README.mpc85xx
index 5a4b591..f9b023f 100644
--- a/doc/README.mpc85xx
+++ b/doc/README.mpc85xx
@@ -26,7 +26,7 @@ Major Config Switches during various boot Modes
----------------------------------------------
NOR boot
- !defined(CONFIG_SYS_RAMBOOT)
+ !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SPL)
NOR boot Secure
!defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT)
RAMBOOT(SD, SPI & NAND boot)
--
1.7.9.5
^ permalink raw reply related [flat|nested] 81+ messages in thread* [U-Boot] [PATCH v2 17/22] powerpc/mpc85xx/p1_p2_rdb_pc: new SPL support
2012-10-30 2:04 ` [U-Boot] [PATCH v2 00/22] " Scott Wood
` (15 preceding siblings ...)
2012-10-30 2:05 ` [U-Boot] [PATCH v2 16/22] spl/85xx: new SPL support Scott Wood
@ 2012-10-30 2:05 ` Scott Wood
2012-10-30 2:05 ` [U-Boot] [PATCH v2 18/22] spl/nand: introduce CONFIG_SPL_NAND_DRIVERS, _BASE, and _ECC Scott Wood
` (5 subsequent siblings)
22 siblings, 0 replies; 81+ messages in thread
From: Scott Wood @ 2012-10-30 2:05 UTC (permalink / raw)
To: u-boot
Introduces CONFIG_SPL_RELOC_TEXT_BASE and CONFIG_SPL_RELOC_STACK.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Cc: Andy Fleming <afleming@freescale.com>
---
README | 9 ++
board/freescale/p1_p2_rdb_pc/Makefile | 16 ++++
board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 2 +-
board/freescale/p1_p2_rdb_pc/spl_minimal.c | 131 +++++++++++++++++++++++++++
board/freescale/p1_p2_rdb_pc/tlb.c | 7 +-
5 files changed, 160 insertions(+), 5 deletions(-)
create mode 100644 board/freescale/p1_p2_rdb_pc/spl_minimal.c
diff --git a/README b/README
index cf83c47..b03796b 100644
--- a/README
+++ b/README
@@ -2633,6 +2633,10 @@ FIT uImage format:
CONFIG_SPL_TEXT_BASE
TEXT_BASE for linking the SPL binary.
+ CONFIG_SPL_RELOC_TEXT_BASE
+ Address to relocate to. If unspecified, this is equal to
+ CONFIG_SPL_TEXT_BASE (i.e. no relocation is done).
+
CONFIG_SPL_BSS_START_ADDR
Link address for the BSS within the SPL binary.
@@ -2642,6 +2646,11 @@ FIT uImage format:
CONFIG_SPL_STACK
Adress of the start of the stack SPL will use
+ CONFIG_SPL_RELOC_STACK
+ Adress of the start of the stack SPL will use after
+ relocation. If unspecified, this is equal to
+ CONFIG_SPL_STACK.
+
CONFIG_SYS_SPL_MALLOC_START
Starting address of the malloc pool used in SPL.
diff --git a/board/freescale/p1_p2_rdb_pc/Makefile b/board/freescale/p1_p2_rdb_pc/Makefile
index 0dcf7d1..5b45d72 100644
--- a/board/freescale/p1_p2_rdb_pc/Makefile
+++ b/board/freescale/p1_p2_rdb_pc/Makefile
@@ -24,11 +24,27 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).o
+MINIMAL=
+
+ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_SPL_INIT_MINIMAL
+MINIMAL=y
+endif
+endif
+
+ifdef MINIMAL
+
+COBJS-y += spl_minimal.o tlb.o law.o
+
+else
+
COBJS-y += $(BOARD).o
COBJS-y += ddr.o
COBJS-y += law.o
COBJS-y += tlb.o
+endif
+
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS-y))
SOBJS := $(addprefix $(obj),$(SOBJS))
diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
index aa39260..5b5b86c 100644
--- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
+++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
@@ -177,7 +177,7 @@ void board_gpio_init(void)
*/
setbits_be32(&pgpio->gpdir, 0x02130000);
-#ifndef CONFIG_SYS_RAMBOOT
+#if !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SPL)
/* init DDR3 reset signal */
setbits_be32(&pgpio->gpdir, 0x00200000);
setbits_be32(&pgpio->gpodr, 0x00200000);
diff --git a/board/freescale/p1_p2_rdb_pc/spl_minimal.c b/board/freescale/p1_p2_rdb_pc/spl_minimal.c
new file mode 100644
index 0000000..5c893ee
--- /dev/null
+++ b/board/freescale/p1_p2_rdb_pc/spl_minimal.c
@@ -0,0 +1,131 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ *
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <ns16550.h>
+#include <asm/io.h>
+#include <nand.h>
+#include <asm/fsl_law.h>
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/global_data.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Fixed sdram init -- doesn't use serial presence detect.
+ */
+void sdram_init(void)
+{
+ ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR;
+
+ __raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds);
+ __raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config);
+#if CONFIG_CHIP_SELECTS_PER_CTRL > 1
+ __raw_writel(CONFIG_SYS_DDR_CS1_BNDS, &ddr->cs1_bnds);
+ __raw_writel(CONFIG_SYS_DDR_CS1_CONFIG, &ddr->cs1_config);
+#endif
+ __raw_writel(CONFIG_SYS_DDR_TIMING_3, &ddr->timing_cfg_3);
+ __raw_writel(CONFIG_SYS_DDR_TIMING_0, &ddr->timing_cfg_0);
+ __raw_writel(CONFIG_SYS_DDR_TIMING_1, &ddr->timing_cfg_1);
+ __raw_writel(CONFIG_SYS_DDR_TIMING_2, &ddr->timing_cfg_2);
+
+ __raw_writel(CONFIG_SYS_DDR_CONTROL_2, &ddr->sdram_cfg_2);
+ __raw_writel(CONFIG_SYS_DDR_MODE_1, &ddr->sdram_mode);
+ __raw_writel(CONFIG_SYS_DDR_MODE_2, &ddr->sdram_mode_2);
+
+ __raw_writel(CONFIG_SYS_DDR_INTERVAL, &ddr->sdram_interval);
+ __raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init);
+ __raw_writel(CONFIG_SYS_DDR_CLK_CTRL, &ddr->sdram_clk_cntl);
+
+ __raw_writel(CONFIG_SYS_DDR_TIMING_4, &ddr->timing_cfg_4);
+ __raw_writel(CONFIG_SYS_DDR_TIMING_5, &ddr->timing_cfg_5);
+ __raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, &ddr->ddr_zq_cntl);
+ __raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL, &ddr->ddr_wrlvl_cntl);
+
+ /* Set, but do not enable the memory */
+ __raw_writel(CONFIG_SYS_DDR_CONTROL & ~SDRAM_CFG_MEM_EN, &ddr->sdram_cfg);
+
+ asm volatile("sync;isync");
+ udelay(500);
+
+ /* Let the controller go */
+ out_be32(&ddr->sdram_cfg, in_be32(&ddr->sdram_cfg) | SDRAM_CFG_MEM_EN);
+
+ set_next_law(0, CONFIG_SYS_SDRAM_SIZE_LAW, LAW_TRGT_IF_DDR_1);
+}
+
+void board_init_f(ulong bootflag)
+{
+ u32 plat_ratio;
+ ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+#ifndef CONFIG_QE
+ ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
+#endif
+
+ /* initialize selected port with appropriate baud rate */
+ plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
+ plat_ratio >>= 1;
+ gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
+
+ NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
+ gd->bus_clk / 16 / CONFIG_BAUDRATE);
+
+ puts("\nNAND boot... ");
+
+#ifndef CONFIG_QE
+ /* init DDR3 reset signal */
+ __raw_writel(0x02000000, &pgpio->gpdir);
+ __raw_writel(0x00200000, &pgpio->gpodr);
+ __raw_writel(0x00000000, &pgpio->gpdat);
+ udelay(1000);
+ __raw_writel(0x00200000, &pgpio->gpdat);
+ udelay(1000);
+ __raw_writel(0x00000000, &pgpio->gpdir);
+#endif
+
+ /* Initialize the DDR3 */
+ sdram_init();
+
+ /* copy code to RAM and jump to it - this should not return */
+ /* NOTE - code has to be copied out of NAND buffer before
+ * other blocks can be read.
+ */
+ relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+ nand_boot();
+}
+
+void putc(char c)
+{
+ if (c == '\n')
+ NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
+
+ NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
+}
+
+void puts(const char *str)
+{
+ while (*str)
+ putc(*str++);
+}
diff --git a/board/freescale/p1_p2_rdb_pc/tlb.c b/board/freescale/p1_p2_rdb_pc/tlb.c
index 6d22463..0873dd7 100644
--- a/board/freescale/p1_p2_rdb_pc/tlb.c
+++ b/board/freescale/p1_p2_rdb_pc/tlb.c
@@ -53,7 +53,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 1, BOOKE_PAGESZ_1M, 1),
-#ifndef CONFIG_NAND_SPL
+#ifndef CONFIG_SPL_BUILD
/* W**G* - Flash/promjet, localbus */
/* This will be changed to *I*G* after relocation to RAM. */
SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
@@ -85,7 +85,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
SET_TLB_ENTRY(1, CONFIG_SYS_PMC_BASE, CONFIG_SYS_PMC_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 10, BOOKE_PAGESZ_64K, 1),
-#endif
+#endif /* not SPL */
#ifdef CONFIG_SYS_NAND_BASE
/* *I*G - NAND */
@@ -94,7 +94,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
0, 7, BOOKE_PAGESZ_1M, 1),
#endif
-#ifdef CONFIG_SYS_RAMBOOT
+#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)
/* *I*G - eSDHC/eSPI/NAND boot */
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
@@ -108,7 +108,6 @@ struct fsl_e_tlb_entry tlb_table[] = {
0, 9, BOOKE_PAGESZ_1G, 1),
#endif
#endif
-
};
int num_tlb_entries = ARRAY_SIZE(tlb_table);
--
1.7.9.5
^ permalink raw reply related [flat|nested] 81+ messages in thread* [U-Boot] [PATCH v2 18/22] spl/nand: introduce CONFIG_SPL_NAND_DRIVERS, _BASE, and _ECC.
2012-10-30 2:04 ` [U-Boot] [PATCH v2 00/22] " Scott Wood
` (16 preceding siblings ...)
2012-10-30 2:05 ` [U-Boot] [PATCH v2 17/22] powerpc/mpc85xx/p1_p2_rdb_pc: " Scott Wood
@ 2012-10-30 2:05 ` Scott Wood
2012-10-30 2:05 ` [U-Boot] [PATCH v2 19/22] spl/nand: config symbol documentation Scott Wood
` (4 subsequent siblings)
22 siblings, 0 replies; 81+ messages in thread
From: Scott Wood @ 2012-10-30 2:05 UTC (permalink / raw)
To: u-boot
Some small SPLs do not use nand_base.c, and a subset of those also
require a special driver. Some SPLs need software ECC but others can't
fit it.
All existing boards that specify CONFIG_SPL_NAND_SUPPORT have these
symbols added to preserve existing behavior.
Signed-off-by: Scott Wood <scottwood@freescale.com>
--
v2: use positive logic for including bits of NAND, rather than
a MINIMAL symbol that excludes things.
---
README | 10 ++++++++++
drivers/mtd/nand/Makefile | 30 ++++++++++++++++++++++--------
include/configs/am3517_crane.h | 3 +++
include/configs/am3517_evm.h | 3 +++
include/configs/cam_enc_4xx.h | 3 +++
include/configs/da850evm.h | 3 +++
include/configs/devkit8000.h | 3 +++
include/configs/hawkboard.h | 3 +++
include/configs/igep00x0.h | 3 +++
include/configs/mcx.h | 3 +++
include/configs/omap3_beagle.h | 3 +++
include/configs/omap3_evm.h | 3 +++
include/configs/omap3_evm_quick_nand.h | 3 +++
include/configs/omap3_overo.h | 3 +++
include/configs/tam3517-common.h | 3 +++
include/configs/tricorder.h | 3 +++
16 files changed, 74 insertions(+), 8 deletions(-)
diff --git a/README b/README
index b03796b..efa19a4 100644
--- a/README
+++ b/README
@@ -2696,6 +2696,16 @@ FIT uImage format:
CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME
Filename to read to load U-Boot when reading from FAT
+ CONFIG_SPL_NAND_BASE
+ Include nand_base.c in the SPL. Requires
+ CONFIG_SPL_NAND_DRIVERS.
+
+ CONFIG_SPL_NAND_DRIVERS
+ SPL uses normal NAND drivers, not minimal drivers.
+
+ CONFIG_SPL_NAND_ECC
+ Include standard software ECC in the SPL
+
CONFIG_SPL_NAND_SIMPLE
Support for drivers/mtd/nand/libnand.o in SPL binary
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index beb99ca..d8a2dfc 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -26,21 +26,33 @@ include $(TOPDIR)/config.mk
LIB := $(obj)libnand.o
ifdef CONFIG_CMD_NAND
+
ifdef CONFIG_SPL_BUILD
-ifdef CONFIG_SPL_NAND_SIMPLE
-COBJS-y += nand_spl_simple.o
-endif
-ifdef CONFIG_SPL_NAND_LOAD
-COBJS-y += nand_spl_load.o
+
+ifdef CONFIG_SPL_NAND_DRIVERS
+NORMAL_DRIVERS=y
endif
-else
+
+COBJS-$(CONFIG_SPL_NAND_SIMPLE) += nand_spl_simple.o
+COBJS-$(CONFIG_SPL_NAND_LOAD) += nand_spl_load.o
+COBJS-$(CONFIG_SPL_NAND_ECC) += nand_ecc.o
+COBJS-$(CONFIG_SPL_NAND_BASE) += nand_base.o
+
+else # not spl
+
+NORMAL_DRIVERS=y
+
COBJS-y += nand.o
COBJS-y += nand_bbt.o
COBJS-y += nand_ids.o
COBJS-y += nand_util.o
-endif
COBJS-y += nand_ecc.o
COBJS-y += nand_base.o
+
+endif # not spl
+
+ifdef NORMAL_DRIVERS
+
COBJS-$(CONFIG_NAND_ECC_BCH) += nand_bch.o
COBJS-$(CONFIG_NAND_ATMEL) += atmel_nand.o
@@ -65,7 +77,9 @@ COBJS-$(CONFIG_NAND_SPEAR) += spr_nand.o
COBJS-$(CONFIG_TEGRA_NAND) += tegra_nand.o
COBJS-$(CONFIG_NAND_OMAP_GPMC) += omap_gpmc.o
COBJS-$(CONFIG_NAND_PLAT) += nand_plat.o
-endif
+
+endif # drivers
+endif # nand
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
diff --git a/include/configs/am3517_crane.h b/include/configs/am3517_crane.h
index 20a3df5..e1ad1e5 100644
--- a/include/configs/am3517_crane.h
+++ b/include/configs/am3517_crane.h
@@ -337,6 +337,9 @@
#define CONFIG_SPL_FAT_SUPPORT
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_ECC
#define CONFIG_SPL_POWER_SUPPORT
#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h
index ce71d13..f833275 100644
--- a/include/configs/am3517_evm.h
+++ b/include/configs/am3517_evm.h
@@ -336,6 +336,9 @@
#define CONFIG_SPL_FAT_SUPPORT
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_ECC
#define CONFIG_SPL_POWER_SUPPORT
#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
diff --git a/include/configs/cam_enc_4xx.h b/include/configs/cam_enc_4xx.h
index 56dc1cb..a7a698c 100644
--- a/include/configs/cam_enc_4xx.h
+++ b/include/configs/cam_enc_4xx.h
@@ -219,6 +219,9 @@
#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_ECC
#define CONFIG_SPL_NAND_SIMPLE
#define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
#define CONFIG_SPL_SERIAL_SUPPORT
diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h
index ddd6155..99b4de7 100644
--- a/include/configs/da850evm.h
+++ b/include/configs/da850evm.h
@@ -227,6 +227,9 @@
#define CONFIG_SYS_NAND_ECCBYTES 10
#define CONFIG_SYS_NAND_OOBSIZE 64
#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_ECC
#define CONFIG_SPL_NAND_SIMPLE
#define CONFIG_SPL_NAND_LOAD
#endif
diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h
index da3263f..83a8b5d 100644
--- a/include/configs/devkit8000.h
+++ b/include/configs/devkit8000.h
@@ -316,6 +316,9 @@
#define CONFIG_SPL_GPIO_SUPPORT
#define CONFIG_SPL_POWER_SUPPORT
#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_ECC
#define CONFIG_SPL_MMC_SUPPORT
#define CONFIG_SPL_FAT_SUPPORT
#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
diff --git a/include/configs/hawkboard.h b/include/configs/hawkboard.h
index c0e3ed3..8d27590 100644
--- a/include/configs/hawkboard.h
+++ b/include/configs/hawkboard.h
@@ -63,6 +63,9 @@
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_ECC
#define CONFIG_SPL_NAND_SIMPLE
#define CONFIG_SPL_LIBGENERIC_SUPPORT /* for udelay and __div64_32 for NAND */
#define CONFIG_SPL_SERIAL_SUPPORT
diff --git a/include/configs/igep00x0.h b/include/configs/igep00x0.h
index c81ab76..be7937d 100644
--- a/include/configs/igep00x0.h
+++ b/include/configs/igep00x0.h
@@ -338,6 +338,9 @@
#ifdef CONFIG_BOOT_NAND
#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_ECC
/* NAND boot config */
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
diff --git a/include/configs/mcx.h b/include/configs/mcx.h
index bf49cc1..b5bcba7 100644
--- a/include/configs/mcx.h
+++ b/include/configs/mcx.h
@@ -379,6 +379,9 @@
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_POWER_SUPPORT
#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_ECC
#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
#define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/
diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h
index 7a3cc16..e6f2f29 100644
--- a/include/configs/omap3_beagle.h
+++ b/include/configs/omap3_beagle.h
@@ -414,6 +414,9 @@
#define CONFIG_SPL_FAT_SUPPORT
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_ECC
#define CONFIG_SPL_GPIO_SUPPORT
#define CONFIG_SPL_POWER_SUPPORT
#define CONFIG_SPL_OMAP3_ID_NAND
diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h
index f6e4236..b4d925e 100644
--- a/include/configs/omap3_evm.h
+++ b/include/configs/omap3_evm.h
@@ -113,6 +113,9 @@
/* NAND SPL */
#define CONFIG_SPL_NAND_SIMPLE
#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_ECC
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_COUNT 64
#define CONFIG_SYS_NAND_PAGE_SIZE 2048
diff --git a/include/configs/omap3_evm_quick_nand.h b/include/configs/omap3_evm_quick_nand.h
index 362fa1d..8f02584 100644
--- a/include/configs/omap3_evm_quick_nand.h
+++ b/include/configs/omap3_evm_quick_nand.h
@@ -81,6 +81,9 @@
*/
#define CONFIG_SPL_NAND_SIMPLE
#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_ECC
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_COUNT 64
#define CONFIG_SYS_NAND_PAGE_SIZE 2048
diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h
index 626cf7a..fd31c73 100644
--- a/include/configs/omap3_overo.h
+++ b/include/configs/omap3_overo.h
@@ -319,6 +319,9 @@
#define CONFIG_SPL_FAT_SUPPORT
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_ECC
#define CONFIG_SPL_GPIO_SUPPORT
#define CONFIG_SPL_POWER_SUPPORT
#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
diff --git a/include/configs/tam3517-common.h b/include/configs/tam3517-common.h
index dd7757c..fb56a93 100644
--- a/include/configs/tam3517-common.h
+++ b/include/configs/tam3517-common.h
@@ -254,6 +254,9 @@
#define CONFIG_SPL_GPIO_SUPPORT
#define CONFIG_SPL_POWER_SUPPORT
#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_ECC
#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
#define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/
diff --git a/include/configs/tricorder.h b/include/configs/tricorder.h
index 5859a73..be0d2ec 100644
--- a/include/configs/tricorder.h
+++ b/include/configs/tricorder.h
@@ -282,6 +282,9 @@
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_POWER_SUPPORT
#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_ECC
#define CONFIG_SPL_MMC_SUPPORT
#define CONFIG_SPL_FAT_SUPPORT
#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
--
1.7.9.5
^ permalink raw reply related [flat|nested] 81+ messages in thread* [U-Boot] [PATCH v2 19/22] spl/nand: config symbol documentation
2012-10-30 2:04 ` [U-Boot] [PATCH v2 00/22] " Scott Wood
` (17 preceding siblings ...)
2012-10-30 2:05 ` [U-Boot] [PATCH v2 18/22] spl/nand: introduce CONFIG_SPL_NAND_DRIVERS, _BASE, and _ECC Scott Wood
@ 2012-10-30 2:05 ` Scott Wood
2012-10-30 2:05 ` [U-Boot] [PATCH v2 20/22] powerpc/mpc85xx/p1_p2_rdb_pc: convert from nand_spl to new spl Scott Wood
` (3 subsequent siblings)
22 siblings, 0 replies; 81+ messages in thread
From: Scott Wood @ 2012-10-30 2:05 UTC (permalink / raw)
To: u-boot
Document parameters used for specifying the NAND image to be loaded.
Also fix the definition of CONFIG_SPL_NAND_SIMPLE -- it's only
nand_spl_simple.c, not the entire nand directory. The word "simple" is
there for a reason. :-)
Signed-off-by: Scott Wood <scottwood@freescale.com>
---
v2: updated for makefile changes earlier in patchset
---
README | 17 ++--
drivers/mtd/nand/Makefile | 4 +
drivers/mtd/nand/fsl_elbc_spl.c | 168 +++++++++++++++++++++++++++++++++++++++
3 files changed, 183 insertions(+), 6 deletions(-)
create mode 100644 drivers/mtd/nand/fsl_elbc_spl.c
diff --git a/README b/README
index efa19a4..b27c843 100644
--- a/README
+++ b/README
@@ -2707,7 +2707,8 @@ FIT uImage format:
Include standard software ECC in the SPL
CONFIG_SPL_NAND_SIMPLE
- Support for drivers/mtd/nand/libnand.o in SPL binary
+ Support for NAND boot using simple NAND drivers that
+ expose the cmd_ctrl() interface.
CONFIG_SYS_NAND_5_ADDR_CYCLE, CONFIG_SYS_NAND_PAGE_COUNT,
CONFIG_SYS_NAND_PAGE_SIZE, CONFIG_SYS_NAND_OOBSIZE,
@@ -2715,15 +2716,19 @@ FIT uImage format:
CONFIG_SYS_NAND_ECCPOS, CONFIG_SYS_NAND_ECCSIZE,
CONFIG_SYS_NAND_ECCBYTES
Defines the size and behavior of the NAND that SPL uses
- to read U-Boot with CONFIG_SPL_NAND_SIMPLE
+ to read U-Boot
CONFIG_SYS_NAND_U_BOOT_OFFS
- Location in NAND for CONFIG_SPL_NAND_SIMPLE to read U-Boot
- from.
+ Location in NAND to read U-Boot from
+
+ CONFIG_SYS_NAND_U_BOOT_DST
+ Location in memory to load U-Boot to
+
+ CONFIG_SYS_NAND_U_BOOT_SIZE
+ Size of image to load
CONFIG_SYS_NAND_U_BOOT_START
- Location in memory for CONFIG_SPL_NAND_SIMPLE to load U-Boot
- to.
+ Entry point in loaded image to jump to
CONFIG_SYS_NAND_HW_ECC_OOBFIRST
Define this if you need to first read the OOB and then the
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index d8a2dfc..28e52bd 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -78,6 +78,10 @@ COBJS-$(CONFIG_TEGRA_NAND) += tegra_nand.o
COBJS-$(CONFIG_NAND_OMAP_GPMC) += omap_gpmc.o
COBJS-$(CONFIG_NAND_PLAT) += nand_plat.o
+else # minimal SPL drivers
+
+COBJS-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_spl.o
+
endif # drivers
endif # nand
diff --git a/drivers/mtd/nand/fsl_elbc_spl.c b/drivers/mtd/nand/fsl_elbc_spl.c
new file mode 100644
index 0000000..50ff4fe
--- /dev/null
+++ b/drivers/mtd/nand/fsl_elbc_spl.c
@@ -0,0 +1,168 @@
+/*
+ * NAND boot for Freescale Enhanced Local Bus Controller, Flash Control Machine
+ *
+ * (C) Copyright 2006-2008
+ * Stefan Roese, DENX Software Engineering, sr at denx.de.
+ *
+ * Copyright (c) 2008 Freescale Semiconductor, Inc.
+ * Author: Scott Wood <scottwood@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/fsl_lbc.h>
+#include <nand.h>
+
+#define WINDOW_SIZE 8192
+
+static void nand_wait(void)
+{
+ fsl_lbc_t *regs = LBC_BASE_ADDR;
+
+ for (;;) {
+ uint32_t status = in_be32(®s->ltesr);
+
+ if (status == 1)
+ return;
+
+ if (status & 1) {
+ puts("read failed (ltesr)\n");
+ for (;;);
+ }
+ }
+}
+
+static int nand_load_image(uint32_t offs, unsigned int uboot_size, void *vdst)
+{
+ fsl_lbc_t *regs = LBC_BASE_ADDR;
+ uchar *buf = (uchar *)CONFIG_SYS_NAND_BASE;
+ const int large = CONFIG_SYS_NAND_OR_PRELIM & OR_FCM_PGS;
+ const int block_shift = large ? 17 : 14;
+ const int block_size = 1 << block_shift;
+ const int page_size = large ? 2048 : 512;
+ const int bad_marker = large ? page_size + 0 : page_size + 5;
+ int fmr = (15 << FMR_CWTO_SHIFT) | (2 << FMR_AL_SHIFT) | 2;
+ int pos = 0;
+ char *dst = vdst;
+
+ if (offs & (block_size - 1)) {
+ puts("bad offset\n");
+ for (;;);
+ }
+
+ if (large) {
+ fmr |= FMR_ECCM;
+ out_be32(®s->fcr, (NAND_CMD_READ0 << FCR_CMD0_SHIFT) |
+ (NAND_CMD_READSTART << FCR_CMD1_SHIFT));
+ out_be32(®s->fir,
+ (FIR_OP_CW0 << FIR_OP0_SHIFT) |
+ (FIR_OP_CA << FIR_OP1_SHIFT) |
+ (FIR_OP_PA << FIR_OP2_SHIFT) |
+ (FIR_OP_CW1 << FIR_OP3_SHIFT) |
+ (FIR_OP_RBW << FIR_OP4_SHIFT));
+ } else {
+ out_be32(®s->fcr, NAND_CMD_READ0 << FCR_CMD0_SHIFT);
+ out_be32(®s->fir,
+ (FIR_OP_CW0 << FIR_OP0_SHIFT) |
+ (FIR_OP_CA << FIR_OP1_SHIFT) |
+ (FIR_OP_PA << FIR_OP2_SHIFT) |
+ (FIR_OP_RBW << FIR_OP3_SHIFT));
+ }
+
+ out_be32(®s->fbcr, 0);
+ clrsetbits_be32(®s->bank[0].br, BR_DECC, BR_DECC_CHK_GEN);
+
+ while (pos < uboot_size) {
+ int i = 0;
+ out_be32(®s->fbar, offs >> block_shift);
+
+ do {
+ int j;
+ unsigned int page_offs = (offs & (block_size - 1)) << 1;
+
+ out_be32(®s->ltesr, ~0);
+ out_be32(®s->lteatr, 0);
+ out_be32(®s->fpar, page_offs);
+ out_be32(®s->fmr, fmr);
+ out_be32(®s->lsor, 0);
+ nand_wait();
+
+ page_offs %= WINDOW_SIZE;
+
+ /*
+ * If either of the first two pages are marked bad,
+ * continue to the next block.
+ */
+ if (i++ < 2 && buf[page_offs + bad_marker] != 0xff) {
+ puts("skipping\n");
+ offs = (offs + block_size) & ~(block_size - 1);
+ pos &= ~(block_size - 1);
+ break;
+ }
+
+ for (j = 0; j < page_size; j++)
+ dst[pos + j] = buf[page_offs + j];
+
+ pos += page_size;
+ offs += page_size;
+ } while ((offs & (block_size - 1)) && (pos < uboot_size));
+ }
+
+ return 0;
+}
+
+/*
+ * The main entry for NAND booting. It's necessary that SDRAM is already
+ * configured and available since this code loads the main U-Boot image
+ * from NAND into SDRAM and starts it from there.
+ */
+void nand_boot(void)
+{
+ __attribute__((noreturn)) void (*uboot)(void);
+ /*
+ * Load U-Boot image from NAND into RAM
+ */
+ nand_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS,
+ CONFIG_SYS_NAND_U_BOOT_SIZE,
+ (void *)CONFIG_SYS_NAND_U_BOOT_DST);
+
+#ifdef CONFIG_NAND_ENV_DST
+ nand_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+ (void *)CONFIG_NAND_ENV_DST);
+
+#ifdef CONFIG_ENV_OFFSET_REDUND
+ nand_load_image(CONFIG_ENV_OFFSET_REDUND, CONFIG_ENV_SIZE,
+ (void *)CONFIG_NAND_ENV_DST + CONFIG_ENV_SIZE);
+#endif
+#endif
+
+#ifdef CONFIG_SPL_FLUSH_IMAGE
+ /*
+ * Clean d-cache and invalidate i-cache, to
+ * make sure that no stale data is executed.
+ */
+ flush_cache(CONFIG_SYS_NAND_U_BOOT_DST, CONFIG_SYS_NAND_U_BOOT_SIZE);
+#endif
+
+ puts("transfering control\n");
+ /*
+ * Jump to U-Boot image
+ */
+ uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START;
+ (*uboot)();
+}
--
1.7.9.5
^ permalink raw reply related [flat|nested] 81+ messages in thread* [U-Boot] [PATCH v2 20/22] powerpc/mpc85xx/p1_p2_rdb_pc: convert from nand_spl to new spl
2012-10-30 2:04 ` [U-Boot] [PATCH v2 00/22] " Scott Wood
` (18 preceding siblings ...)
2012-10-30 2:05 ` [U-Boot] [PATCH v2 19/22] spl/nand: config symbol documentation Scott Wood
@ 2012-10-30 2:05 ` Scott Wood
2012-10-30 2:05 ` [U-Boot] [PATCH v2 21/22] powerpc/mpc85xx/p1_p2_rdb_pc: clean up memory map Scott Wood
` (2 subsequent siblings)
22 siblings, 0 replies; 81+ messages in thread
From: Scott Wood @ 2012-10-30 2:05 UTC (permalink / raw)
To: u-boot
Signed-off-by: Scott Wood <scottwood@freescale.com>
Cc: Andy Fleming <afleming@freescale.com>
---
include/configs/p1_p2_rdb_pc.h | 54 ++++----
nand_spl/board/freescale/p1_p2_rdb_pc/Makefile | 142 ---------------------
nand_spl/board/freescale/p1_p2_rdb_pc/nand_boot.c | 132 -------------------
3 files changed, 28 insertions(+), 300 deletions(-)
delete mode 100644 nand_spl/board/freescale/p1_p2_rdb_pc/Makefile
delete mode 100644 nand_spl/board/freescale/p1_p2_rdb_pc/nand_boot.c
diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index 350150b..7af4d93 100644
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -140,16 +140,25 @@
#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
#endif
-#if defined(CONFIG_NAND) && defined(CONFIG_NAND_FSL_ELBC)
-#define CONFIG_NAND_U_BOOT
-#define CONFIG_SYS_EXTRA_ENV_RELOC
-#define CONFIG_SYS_RAMBOOT
-#define CONFIG_SYS_TEXT_BASE_SPL 0xff800000
-#ifdef CONFIG_NAND_SPL
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL
-#else
-#define CONFIG_SYS_TEXT_BASE 0x11001000
-#endif /* CONFIG_NAND_SPL */
+#ifdef CONFIG_NAND
+#define CONFIG_SPL
+#define CONFIG_SPL_INIT_MINIMAL
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_MINIMAL
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
+
+#define CONFIG_SYS_TEXT_BASE 0x00201000
+#define CONFIG_SPL_TEXT_BASE 0xfffff000
+#define CONFIG_SPL_MAX_SIZE (4 * 1024)
+#define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000
+#define CONFIG_SPL_RELOC_STACK 0x00100000
+#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) + CONFIG_SPL_MAX_SIZE)
+#define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE)
+#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
+#define CONFIG_SYS_NAND_U_BOOT_OFFS 0
+#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
#endif
#ifndef CONFIG_SYS_TEXT_BASE
@@ -161,8 +170,12 @@
#endif
#ifndef CONFIG_SYS_MONITOR_BASE
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
+#else
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
#endif
+#endif
/* High Level Configuration Options */
#define CONFIG_BOOKE
@@ -221,7 +234,7 @@
/* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
SPL code*/
-#if defined(CONFIG_NAND_SPL)
+#ifdef CONFIG_SPL_BUILD
#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
#endif
@@ -392,15 +405,6 @@
#define CONFIG_CMD_NAND
#define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024)
-/* NAND boot: 4K NAND loader config */
-#define CONFIG_SYS_NAND_SPL_SIZE 0x1000
-#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) + CONFIG_SYS_NAND_SPL_SIZE)
-#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000 - CONFIG_SYS_NAND_SPL_SIZE)
-#define CONFIG_SYS_NAND_U_BOOT_START 0x11000000
-#define CONFIG_SYS_NAND_U_BOOT_OFFS (0)
-#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
-#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000)
-
#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
| BR_PS_8 /* Port Size = 8 bit */ \
@@ -461,7 +465,7 @@
OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \
OR_GPCM_EAD)
-#ifdef CONFIG_NAND_U_BOOT
+#ifdef CONFIG_NAND
#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
#define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
@@ -511,7 +515,7 @@
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
-#ifdef CONFIG_NAND_SPL
+#ifdef CONFIG_SPL_BUILD
#define CONFIG_NS16550_MIN_FUNCTIONS
#endif
@@ -709,7 +713,6 @@
/*
* Environment
*/
-#ifdef CONFIG_SYS_RAMBOOT
#ifdef CONFIG_RAMBOOT_SPIFLASH
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SPI_BUS 0
@@ -724,16 +727,15 @@
#define CONFIG_FSL_FIXED_MMC_LOCATION
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_SYS_MMC_ENV_DEV 0
-#elif defined(CONFIG_NAND_U_BOOT)
+#elif defined(CONFIG_NAND)
#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
#define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
-#else
+#elif defined(CONFIG_SYS_RAMBOOT)
#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
#define CONFIG_ENV_SIZE 0x2000
-#endif
#else
#define CONFIG_ENV_IS_IN_FLASH
#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
diff --git a/nand_spl/board/freescale/p1_p2_rdb_pc/Makefile b/nand_spl/board/freescale/p1_p2_rdb_pc/Makefile
deleted file mode 100644
index 797a800..0000000
--- a/nand_spl/board/freescale/p1_p2_rdb_pc/Makefile
+++ /dev/null
@@ -1,142 +0,0 @@
-#
-# (C) Copyright 2007
-# Stefan Roese, DENX Software Engineering, sr at denx.de.
-#
-# Copyright 2011 Freescale Semiconductor, Inc.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-NAND_SPL := y
-CONFIG_SYS_TEXT_BASE_SPL := 0xfff00000
-PAD_TO := 0xff801000
-
-include $(TOPDIR)/config.mk
-
-nandobj := $(OBJTREE)/nand_spl/
-
-LDSCRIPT= $(TOPDIR)/$(CPUDIR)/u-boot-nand_spl.lds
-LSTSCRIPT= $(nandobj)/board/$(BOARDDIR)/u-boot.lst
-LDFLAGS := -T $(nandobj)u-boot-nand_spl.lds -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) \
- $(LDFLAGS) $(LDFLAGS_FINAL)
-AFLAGS += -DCONFIG_NAND_SPL
-CFLAGS += -DCONFIG_NAND_SPL
-
-SOBJS = start.o resetvec.o
-COBJS = cache.o cpu_init_early.o spl_minimal.o fsl_law.o law.o \
- nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o
-
-SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
-OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
-__OBJS := $(SOBJS) $(COBJS)
-LNDIR := $(nandobj)board/$(BOARDDIR)
-
-ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
-
-all: $(obj).depend $(ALL)
-
-$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
- $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@
-
-$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl
- $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
-
-$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot-nand_spl.lds
- cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \
- -Map $(nandobj)u-boot-spl.map \
- -o $(nandobj)u-boot-spl
-
-# The following line expands into whole rule which generates $(LSTSCRIPT),
-# the file containing u-boots LG-array linker section. This is included into
-# $(LDSCRIPT). The function make_u_boot_list is defined in helper.mk file.
-$(eval $(call make_u_boot_list, $(LSTSCRIPT), $(OBJS)))
-$(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT) $(LSTSCRIPT)
- $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -I$(obj) -ansi -D__ASSEMBLY__ -P - <$< >$@
-
-# create symbolic links for common files
-
-$(obj)cache.c:
- @rm -f $(obj)cache.c
- ln -sf $(SRCTREE)/arch/powerpc/lib/cache.c $(obj)cache.c
-
-$(obj)cpu_init_early.c:
- @rm -f $(obj)cpu_init_early.c
- ln -sf $(SRCTREE)/$(CPUDIR)/cpu_init_early.c $(obj)cpu_init_early.c
-
-$(obj)spl_minimal.c:
- @rm -f $(obj)spl_minimal.c
- ln -sf $(SRCTREE)/$(CPUDIR)/spl_minimal.c $(obj)spl_minimal.c
-
-$(obj)fsl_law.c:
- @rm -f $(obj)fsl_law.c
- ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc8xxx/law.c $(obj)fsl_law.c
-
-$(obj)law.c:
- @rm -f $(obj)law.c
- ln -sf $(SRCTREE)/board/$(BOARDDIR)/law.c $(obj)law.c
-
-$(obj)nand_boot_fsl_elbc.c:
- @rm -f $(obj)nand_boot_fsl_elbc.c
- ln -sf $(SRCTREE)/nand_spl/nand_boot_fsl_elbc.c \
- $(obj)nand_boot_fsl_elbc.c
-
-$(obj)ns16550.c:
- @rm -f $(obj)ns16550.c
- ln -sf $(SRCTREE)/drivers/serial/ns16550.c $(obj)ns16550.c
-
-$(obj)resetvec.S:
- @rm -f $(obj)resetvec.S
- ln -s $(SRCTREE)/$(CPUDIR)/resetvec.S $(obj)resetvec.S
-
-$(obj)fixed_ivor.S:
- @rm -f $(obj)fixed_ivor.S
- ln -sf $(SRCTREE)/$(CPUDIR)/fixed_ivor.S $(obj)fixed_ivor.S
-
-$(obj)start.S: $(obj)fixed_ivor.S
- @rm -f $(obj)start.S
- ln -sf $(SRCTREE)/$(CPUDIR)/start.S $(obj)start.S
-
-$(obj)tlb.c:
- @rm -f $(obj)tlb.c
- ln -sf $(SRCTREE)/$(CPUDIR)/tlb.c $(obj)tlb.c
-
-$(obj)tlb_table.c:
- @rm -f $(obj)tlb_table.c
- ln -sf $(SRCTREE)/board/$(BOARDDIR)/tlb.c $(obj)tlb_table.c
-
-ifneq ($(OBJTREE), $(SRCTREE))
-$(obj)nand_boot.c:
- @rm -f $(obj)nand_boot.c
- ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $(obj)nand_boot.c
-endif
-
-#########################################################################
-
-$(obj)%.o: $(obj)%.S
- $(CC) $(AFLAGS) -c -o $@ $<
-
-$(obj)%.o: $(obj)%.c
- $(CC) $(CFLAGS) -c -o $@ $<
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/nand_spl/board/freescale/p1_p2_rdb_pc/nand_boot.c b/nand_spl/board/freescale/p1_p2_rdb_pc/nand_boot.c
deleted file mode 100644
index 4c140c1..0000000
--- a/nand_spl/board/freescale/p1_p2_rdb_pc/nand_boot.c
+++ /dev/null
@@ -1,132 +0,0 @@
-/*
- * Copyright 2011 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- *
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- */
-
-#include <common.h>
-#include <ns16550.h>
-#include <asm/io.h>
-#include <nand.h>
-#include <asm/fsl_law.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/global_data.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * Fixed sdram init -- doesn't use serial presence detect.
- */
-void sdram_init(void)
-{
- ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR;
-
- __raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds);
- __raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config);
-#if CONFIG_CHIP_SELECTS_PER_CTRL > 1
- __raw_writel(CONFIG_SYS_DDR_CS1_BNDS, &ddr->cs1_bnds);
- __raw_writel(CONFIG_SYS_DDR_CS1_CONFIG, &ddr->cs1_config);
-#endif
- __raw_writel(CONFIG_SYS_DDR_TIMING_3, &ddr->timing_cfg_3);
- __raw_writel(CONFIG_SYS_DDR_TIMING_0, &ddr->timing_cfg_0);
- __raw_writel(CONFIG_SYS_DDR_TIMING_1, &ddr->timing_cfg_1);
- __raw_writel(CONFIG_SYS_DDR_TIMING_2, &ddr->timing_cfg_2);
-
- __raw_writel(CONFIG_SYS_DDR_CONTROL_2, &ddr->sdram_cfg_2);
- __raw_writel(CONFIG_SYS_DDR_MODE_1, &ddr->sdram_mode);
- __raw_writel(CONFIG_SYS_DDR_MODE_2, &ddr->sdram_mode_2);
-
- __raw_writel(CONFIG_SYS_DDR_INTERVAL, &ddr->sdram_interval);
- __raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init);
- __raw_writel(CONFIG_SYS_DDR_CLK_CTRL, &ddr->sdram_clk_cntl);
-
- __raw_writel(CONFIG_SYS_DDR_TIMING_4, &ddr->timing_cfg_4);
- __raw_writel(CONFIG_SYS_DDR_TIMING_5, &ddr->timing_cfg_5);
- __raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, &ddr->ddr_zq_cntl);
- __raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL, &ddr->ddr_wrlvl_cntl);
-
- /* Set, but do not enable the memory */
- __raw_writel(CONFIG_SYS_DDR_CONTROL & ~SDRAM_CFG_MEM_EN, &ddr->sdram_cfg);
-
- asm volatile("sync;isync");
- udelay(500);
-
- /* Let the controller go */
- out_be32(&ddr->sdram_cfg, in_be32(&ddr->sdram_cfg) | SDRAM_CFG_MEM_EN);
-
- set_next_law(0, CONFIG_SYS_SDRAM_SIZE_LAW, LAW_TRGT_IF_DDR_1);
-}
-
-void board_init_f(ulong bootflag)
-{
- u32 plat_ratio;
- ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
-#ifndef CONFIG_QE
- ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
-#endif
-
- /* initialize selected port with appropriate baud rate */
- plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
- plat_ratio >>= 1;
- gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
-
- NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
- gd->bus_clk / 16 / CONFIG_BAUDRATE);
-
- puts("\nNAND boot... ");
-
-#ifndef CONFIG_QE
- /* init DDR3 reset signal */
- __raw_writel(0x02000000, &pgpio->gpdir);
- __raw_writel(0x00200000, &pgpio->gpodr);
- __raw_writel(0x00000000, &pgpio->gpdat);
- udelay(1000);
- __raw_writel(0x00200000, &pgpio->gpdat);
- udelay(1000);
- __raw_writel(0x00000000, &pgpio->gpdir);
-#endif
-
- /* Initialize the DDR3 */
- sdram_init();
-
- /* copy code to RAM and jump to it - this should not return */
- /* NOTE - code has to be copied out of NAND buffer before
- * other blocks can be read.
- */
- relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, 0,
- CONFIG_SYS_NAND_U_BOOT_RELOC);
-}
-
-void board_init_r(gd_t *gd, ulong dest_addr)
-{
- nand_boot();
-}
-
-void putc(char c)
-{
- if (c == '\n')
- NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
-
- NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
-}
-
-void puts(const char *str)
-{
- while (*str)
- putc(*str++);
-}
--
1.7.9.5
^ permalink raw reply related [flat|nested] 81+ messages in thread* [U-Boot] [PATCH v2 21/22] powerpc/mpc85xx/p1_p2_rdb_pc: clean up memory map
2012-10-30 2:04 ` [U-Boot] [PATCH v2 00/22] " Scott Wood
` (19 preceding siblings ...)
2012-10-30 2:05 ` [U-Boot] [PATCH v2 20/22] powerpc/mpc85xx/p1_p2_rdb_pc: convert from nand_spl to new spl Scott Wood
@ 2012-10-30 2:05 ` Scott Wood
2012-10-30 2:05 ` [U-Boot] [PATCH v2 22/22] powerpc/mpc85xx/p2020rdb-pca: Use L2 SRAM for SPL boot Scott Wood
2012-10-30 17:04 ` [U-Boot] [PATCH v2 00/22] Convert p1_p2_rdb_pc to new spl Tom Rini
22 siblings, 0 replies; 81+ messages in thread
From: Scott Wood @ 2012-10-30 2:05 UTC (permalink / raw)
To: u-boot
- Sort by address, and fix column alignment
- Don't label things as localbus that aren't. Instead, put chipselect
info at the end of the description for localbus windows. Note that
NAND/NOR have their chipselects swapped when booting from NAND, and CS2
can be either PMC or VSC7385 depending on hwconfig.
- Shrink NAND to the 32K that's actually mapped in the localbus
- Assign an address and size to L2 SRAM. Remove the similarly named
but unintelligible "L2 SDRAM(REV.)".
- Remove the untrue comment about L1 stack being mapped with TLB0.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Cc: Andy Fleming <afleming@freescale.com>
---
board/freescale/p1_p2_rdb_pc/law.c | 2 +-
include/configs/p1_p2_rdb_pc.h | 22 +++++++++-------------
2 files changed, 10 insertions(+), 14 deletions(-)
diff --git a/board/freescale/p1_p2_rdb_pc/law.c b/board/freescale/p1_p2_rdb_pc/law.c
index 0da8300..cb5e7b7 100644
--- a/board/freescale/p1_p2_rdb_pc/law.c
+++ b/board/freescale/p1_p2_rdb_pc/law.c
@@ -32,7 +32,7 @@ struct law_entry law_table[] = {
#endif
SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_LBC),
#ifdef CONFIG_SYS_NAND_BASE_PHYS
- SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
+ SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_32K, LAW_TRGT_IF_LBC),
#endif
};
diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index 7af4d93..ba7a364 100644
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -331,21 +331,17 @@
/*
* Memory map
*
- * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable
+ * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable
* 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3)
+ * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1
+ * 0xff80_0000 0xff80_7fff NAND flash 32K non-cacheable CS1/0
+ * 0xff98_0000 0xff98_ffff PMC 64K non-cacheable CS2
+ * 0xffa0_0000 0xffaf_ffff CPLD 1M non-cacheable CS3
+ * 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable CS2
* 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
- *
- * Localbus cacheable (TBD)
- * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable
- *
- * Localbus non-cacheable
- * 0xec00_0000 0xefff_ffff FLASH Up to 64M non-cacheable
- * 0xff80_0000 0xff8f_ffff NAND flash 1M non-cacheable
- * 0xff90_0000 0xff97_ffff L2 SDRAM(REV.) 512K cacheable(optional)
- * 0xffa0_0000 0xffaf_ffff CPLD 1M non-cacheable
- * 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable
- * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
- * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
+ * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable
+ * 0xffd8_0000 0xffdf_ffff L2 SRAM Up to 512K cacheable
+ * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
*/
--
1.7.9.5
^ permalink raw reply related [flat|nested] 81+ messages in thread* [U-Boot] [PATCH v2 22/22] powerpc/mpc85xx/p2020rdb-pca: Use L2 SRAM for SPL boot
2012-10-30 2:04 ` [U-Boot] [PATCH v2 00/22] " Scott Wood
` (20 preceding siblings ...)
2012-10-30 2:05 ` [U-Boot] [PATCH v2 21/22] powerpc/mpc85xx/p1_p2_rdb_pc: clean up memory map Scott Wood
@ 2012-10-30 2:05 ` Scott Wood
2012-10-30 3:17 ` Tabi Timur-B04825
2012-11-13 22:41 ` [U-Boot] [PATCH v3] " Scott Wood
2012-10-30 17:04 ` [U-Boot] [PATCH v2 00/22] Convert p1_p2_rdb_pc to new spl Tom Rini
22 siblings, 2 replies; 81+ messages in thread
From: Scott Wood @ 2012-10-30 2:05 UTC (permalink / raw)
To: u-boot
This allows DDR configuration to be deferred to the final U-Boot image,
which is able to make use of SPD data. The SPL itself cannot use SPD due
to code size constraints. It previously used fixed register values for
DDR configuration, and those values did not work on the p2020rdb-pca
board I tested with. It's possible that different revisions of the board
require different settings. Using SPD eliminates that problem.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Cc: Andy Fleming <afleming@freescale.com>
---
board/freescale/p1_p2_rdb_pc/spl_minimal.c | 5 ++-
board/freescale/p1_p2_rdb_pc/tlb.c | 15 ++++++-
include/configs/p1_p2_rdb_pc.h | 65 +++++++++++++---------------
3 files changed, 46 insertions(+), 39 deletions(-)
diff --git a/board/freescale/p1_p2_rdb_pc/spl_minimal.c b/board/freescale/p1_p2_rdb_pc/spl_minimal.c
index 5c893ee..8e2725f 100644
--- a/board/freescale/p1_p2_rdb_pc/spl_minimal.c
+++ b/board/freescale/p1_p2_rdb_pc/spl_minimal.c
@@ -23,6 +23,7 @@
#include <ns16550.h>
#include <asm/io.h>
#include <nand.h>
+#include <linux/compiler.h>
#include <asm/fsl_law.h>
#include <asm/fsl_ddr_sdram.h>
#include <asm/global_data.h>
@@ -32,7 +33,7 @@ DECLARE_GLOBAL_DATA_PTR;
/*
* Fixed sdram init -- doesn't use serial presence detect.
*/
-void sdram_init(void)
+static void __maybe_unused sdram_init(void)
{
ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR;
@@ -101,8 +102,10 @@ void board_init_f(ulong bootflag)
__raw_writel(0x00000000, &pgpio->gpdir);
#endif
+#ifndef CONFIG_SYS_INIT_L2_ADDR
/* Initialize the DDR3 */
sdram_init();
+#endif
/* copy code to RAM and jump to it - this should not return */
/* NOTE - code has to be copied out of NAND buffer before
diff --git a/board/freescale/p1_p2_rdb_pc/tlb.c b/board/freescale/p1_p2_rdb_pc/tlb.c
index 0873dd7..3e4dffd 100644
--- a/board/freescale/p1_p2_rdb_pc/tlb.c
+++ b/board/freescale/p1_p2_rdb_pc/tlb.c
@@ -95,6 +95,16 @@ struct fsl_e_tlb_entry tlb_table[] = {
#endif
#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)
+#ifdef CONFIG_SYS_INIT_L2_ADDR
+ /* L2SRAM */
+ SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 8, BOOKE_PAGESZ_256K, 1),
+ SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000,
+ CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 12, BOOKE_PAGESZ_256K, 1),
+#else
/* *I*G - eSDHC/eSPI/NAND boot */
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
@@ -106,8 +116,9 @@ struct fsl_e_tlb_entry tlb_table[] = {
CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 9, BOOKE_PAGESZ_1G, 1),
-#endif
-#endif
+#endif /* P1020MBG */
+#endif /* not L2 SRAM */
+#endif /* RAMBOOT/SPL */
};
int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index ba7a364..f02ba2b 100644
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -38,6 +38,7 @@
#define __SW_BOOT_MASK 0x03
#define __SW_BOOT_NOR 0xe4
#define __SW_BOOT_SD 0x54
+#define CONFIG_SYS_L2_SIZE (256 << 10)
#endif
#if defined(CONFIG_P1020UTM)
@@ -46,6 +47,7 @@
#define __SW_BOOT_MASK 0x03
#define __SW_BOOT_NOR 0xe0
#define __SW_BOOT_SD 0x50
+#define CONFIG_SYS_L2_SIZE (256 << 10)
#endif
#if defined(CONFIG_P1020RDB)
@@ -61,6 +63,7 @@
#define __SW_BOOT_SD 0x9c
#define __SW_BOOT_NAND 0xec
#define __SW_BOOT_PCIE 0x6c
+#define CONFIG_SYS_L2_SIZE (256 << 10)
#endif
#if defined(CONFIG_P1021RDB)
@@ -78,6 +81,7 @@
#define __SW_BOOT_SD 0x9c
#define __SW_BOOT_NAND 0xec
#define __SW_BOOT_PCIE 0x6c
+#define CONFIG_SYS_L2_SIZE (256 << 10)
#endif
#if defined(CONFIG_P1024RDB)
@@ -91,6 +95,7 @@
#define __SW_BOOT_SPI 0x08
#define __SW_BOOT_SD 0x04
#define __SW_BOOT_NAND 0x0c
+#define CONFIG_SYS_L2_SIZE (256 << 10)
#endif
#if defined(CONFIG_P1025RDB)
@@ -108,6 +113,7 @@
#define __SW_BOOT_SPI 0x08
#define __SW_BOOT_SD 0x04
#define __SW_BOOT_NAND 0x0c
+#define CONFIG_SYS_L2_SIZE (256 << 10)
#endif
#if defined(CONFIG_P2020RDB)
@@ -122,6 +128,13 @@
#define __SW_BOOT_SD 0x68 /* or 0x18 */
#define __SW_BOOT_NAND 0xe8
#define __SW_BOOT_PCIE 0xa8
+#define CONFIG_SYS_L2_SIZE (512 << 10)
+#endif
+
+#if CONFIG_SYS_L2_SIZE >= (512 << 10)
+#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR /* must be 32-bit */
+#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
#endif
#ifdef CONFIG_SDCARD
@@ -149,14 +162,25 @@
#define CONFIG_SPL_FLUSH_IMAGE
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
-#define CONFIG_SYS_TEXT_BASE 0x00201000
#define CONFIG_SPL_TEXT_BASE 0xfffff000
#define CONFIG_SPL_MAX_SIZE (4 * 1024)
+
+#ifdef CONFIG_SYS_INIT_L2_ADDR
+/* We multiply CONFIG_SPL_MAX_SIZE by two to leave some room for BSS. */
+#define CONFIG_SYS_TEXT_BASE 0xf8f82000
+#define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - CONFIG_SPL_MAX_SIZE * 2)
+#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_END - CONFIG_SPL_MAX_SIZE * 2)
+#define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR)
+#define CONFIG_SYS_NAND_U_BOOT_START (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SPL_MAX_SIZE)
+#else
+#define CONFIG_SYS_TEXT_BASE 0x00201000
#define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000
#define CONFIG_SPL_RELOC_STACK 0x00100000
-#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) + CONFIG_SPL_MAX_SIZE)
#define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE)
#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
+#endif
+
+#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000)
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0
#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
#endif
@@ -261,39 +285,7 @@
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
/* Default settings for DDR3 */
-#ifdef CONFIG_P2020RDB
-#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
-#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202
-#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
-#define CONFIG_SYS_DDR_CS1_BNDS 0x00000000
-#define CONFIG_SYS_DDR_CS1_CONFIG 0x00000000
-#define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000
-
-#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
-#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
-#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
-#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
-
-#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
-#define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8645F607
-#define CONFIG_SYS_DDR_SR_CNTR 0x00000000
-#define CONFIG_SYS_DDR_RCW_1 0x00000000
-#define CONFIG_SYS_DDR_RCW_2 0x00000000
-#define CONFIG_SYS_DDR_CONTROL 0xC7000000 /* Type = DDR3 */
-#define CONFIG_SYS_DDR_CONTROL_2 0x24401000
-#define CONFIG_SYS_DDR_TIMING_4 0x00220001
-#define CONFIG_SYS_DDR_TIMING_5 0x02401400
-
-#define CONFIG_SYS_DDR_TIMING_3 0x00020000
-#define CONFIG_SYS_DDR_TIMING_0 0x00330104
-#define CONFIG_SYS_DDR_TIMING_1 0x6f6B4644
-#define CONFIG_SYS_DDR_TIMING_2 0x0FA88CCF
-#define CONFIG_SYS_DDR_CLK_CTRL 0x02000000
-#define CONFIG_SYS_DDR_MODE_1 0x00421422
-#define CONFIG_SYS_DDR_MODE_2 0x04000000
-#define CONFIG_SYS_DDR_INTERVAL 0x0C300100
-
-#else
+#ifndef CONFIG_P2020RDB
#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
@@ -334,13 +326,14 @@
* 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable
* 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3)
* 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1
+ * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 512K cacheable
+ * (early boot only)
* 0xff80_0000 0xff80_7fff NAND flash 32K non-cacheable CS1/0
* 0xff98_0000 0xff98_ffff PMC 64K non-cacheable CS2
* 0xffa0_0000 0xffaf_ffff CPLD 1M non-cacheable CS3
* 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable CS2
* 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
* 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable
- * 0xffd8_0000 0xffdf_ffff L2 SRAM Up to 512K cacheable
* 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
*/
--
1.7.9.5
^ permalink raw reply related [flat|nested] 81+ messages in thread* [U-Boot] [PATCH v2 22/22] powerpc/mpc85xx/p2020rdb-pca: Use L2 SRAM for SPL boot
2012-10-30 2:05 ` [U-Boot] [PATCH v2 22/22] powerpc/mpc85xx/p2020rdb-pca: Use L2 SRAM for SPL boot Scott Wood
@ 2012-10-30 3:17 ` Tabi Timur-B04825
2012-10-30 23:37 ` Scott Wood
2012-11-13 22:41 ` [U-Boot] [PATCH v3] " Scott Wood
1 sibling, 1 reply; 81+ messages in thread
From: Tabi Timur-B04825 @ 2012-10-30 3:17 UTC (permalink / raw)
To: u-boot
On Mon, Oct 29, 2012 at 9:05 PM, Scott Wood <scottwood@freescale.com> wrote:
> diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
> index ba7a364..f02ba2b 100644
> --- a/include/configs/p1_p2_rdb_pc.h
> +++ b/include/configs/p1_p2_rdb_pc.h
> @@ -38,6 +38,7 @@
> #define __SW_BOOT_MASK 0x03
> #define __SW_BOOT_NOR 0xe4
> #define __SW_BOOT_SD 0x54
> +#define CONFIG_SYS_L2_SIZE (256 << 10)
Shouldn't this be in config_mpc85xx.h?
--
Timur Tabi
Linux kernel developer@Freescale
^ permalink raw reply [flat|nested] 81+ messages in thread
* [U-Boot] [PATCH v2 22/22] powerpc/mpc85xx/p2020rdb-pca: Use L2 SRAM for SPL boot
2012-10-30 3:17 ` Tabi Timur-B04825
@ 2012-10-30 23:37 ` Scott Wood
0 siblings, 0 replies; 81+ messages in thread
From: Scott Wood @ 2012-10-30 23:37 UTC (permalink / raw)
To: u-boot
On 10/29/2012 10:17:20 PM, Tabi Timur-B04825 wrote:
> On Mon, Oct 29, 2012 at 9:05 PM, Scott Wood <scottwood@freescale.com>
> wrote:
>
> > diff --git a/include/configs/p1_p2_rdb_pc.h
> b/include/configs/p1_p2_rdb_pc.h
> > index ba7a364..f02ba2b 100644
> > --- a/include/configs/p1_p2_rdb_pc.h
> > +++ b/include/configs/p1_p2_rdb_pc.h
> > @@ -38,6 +38,7 @@
> > #define __SW_BOOT_MASK 0x03
> > #define __SW_BOOT_NOR 0xe4
> > #define __SW_BOOT_SD 0x54
> > +#define CONFIG_SYS_L2_SIZE (256 << 10)
>
> Shouldn't this be in config_mpc85xx.h?
Ideally yes, but we use the result later in the board-specific config
file, so it becomes a depedency mess. We can move it if we start
including config_mpc85xx.h from the board config file instead of later
on.
-Scott
^ permalink raw reply [flat|nested] 81+ messages in thread
* [U-Boot] [PATCH v3] powerpc/mpc85xx/p2020rdb-pca: Use L2 SRAM for SPL boot
2012-10-30 2:05 ` [U-Boot] [PATCH v2 22/22] powerpc/mpc85xx/p2020rdb-pca: Use L2 SRAM for SPL boot Scott Wood
2012-10-30 3:17 ` Tabi Timur-B04825
@ 2012-11-13 22:41 ` Scott Wood
1 sibling, 0 replies; 81+ messages in thread
From: Scott Wood @ 2012-11-13 22:41 UTC (permalink / raw)
To: u-boot
This allows DDR configuration to be deferred to the final U-Boot image,
which is able to make use of SPD data. The SPL itself cannot use SPD due
to code size constraints. It previously used fixed register values for
DDR configuration, and those values did not work on the p2020rdb-pca
board I tested with. It's possible that different revisions of the board
require different settings. Using SPD eliminates that problem.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Cc: Andy Fleming <afleming@freescale.com>
---
v3: Fix a build break due to removal of fixed DDR defines -- this was a
last minute change in the previous patch, but I thought I had tested
it... :-P
v2: new patch in v2 of patchset
board/freescale/p1_p2_rdb_pc/ddr.c | 2 +
board/freescale/p1_p2_rdb_pc/spl_minimal.c | 7 ++-
board/freescale/p1_p2_rdb_pc/tlb.c | 15 +++++-
include/configs/p1_p2_rdb_pc.h | 69 +++++++++++++---------------
4 files changed, 54 insertions(+), 39 deletions(-)
diff --git a/board/freescale/p1_p2_rdb_pc/ddr.c b/board/freescale/p1_p2_rdb_pc/ddr.c
index 88ba56f..9355536 100644
--- a/board/freescale/p1_p2_rdb_pc/ddr.c
+++ b/board/freescale/p1_p2_rdb_pc/ddr.c
@@ -206,6 +206,7 @@ int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
}
#endif /* CONFIG_SYS_DDR_RAW_TIMING */
+#ifdef CONFIG_SYS_DDR_CS0_BNDS
/* Fixed sdram init -- doesn't use serial presence detect. */
phys_size_t fixed_sdram(void)
{
@@ -260,6 +261,7 @@ phys_size_t fixed_sdram(void)
return ddr_size;
}
+#endif
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,
diff --git a/board/freescale/p1_p2_rdb_pc/spl_minimal.c b/board/freescale/p1_p2_rdb_pc/spl_minimal.c
index 5c893ee..d48fb01 100644
--- a/board/freescale/p1_p2_rdb_pc/spl_minimal.c
+++ b/board/freescale/p1_p2_rdb_pc/spl_minimal.c
@@ -23,16 +23,18 @@
#include <ns16550.h>
#include <asm/io.h>
#include <nand.h>
+#include <linux/compiler.h>
#include <asm/fsl_law.h>
#include <asm/fsl_ddr_sdram.h>
#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
+#ifndef CONFIG_SYS_INIT_L2_ADDR
/*
* Fixed sdram init -- doesn't use serial presence detect.
*/
-void sdram_init(void)
+static void sdram_init(void)
{
ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR;
@@ -71,6 +73,7 @@ void sdram_init(void)
set_next_law(0, CONFIG_SYS_SDRAM_SIZE_LAW, LAW_TRGT_IF_DDR_1);
}
+#endif
void board_init_f(ulong bootflag)
{
@@ -101,8 +104,10 @@ void board_init_f(ulong bootflag)
__raw_writel(0x00000000, &pgpio->gpdir);
#endif
+#ifndef CONFIG_SYS_INIT_L2_ADDR
/* Initialize the DDR3 */
sdram_init();
+#endif
/* copy code to RAM and jump to it - this should not return */
/* NOTE - code has to be copied out of NAND buffer before
diff --git a/board/freescale/p1_p2_rdb_pc/tlb.c b/board/freescale/p1_p2_rdb_pc/tlb.c
index 0873dd7..3e4dffd 100644
--- a/board/freescale/p1_p2_rdb_pc/tlb.c
+++ b/board/freescale/p1_p2_rdb_pc/tlb.c
@@ -95,6 +95,16 @@ struct fsl_e_tlb_entry tlb_table[] = {
#endif
#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)
+#ifdef CONFIG_SYS_INIT_L2_ADDR
+ /* L2SRAM */
+ SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 8, BOOKE_PAGESZ_256K, 1),
+ SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000,
+ CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 12, BOOKE_PAGESZ_256K, 1),
+#else
/* *I*G - eSDHC/eSPI/NAND boot */
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
@@ -106,8 +116,9 @@ struct fsl_e_tlb_entry tlb_table[] = {
CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 9, BOOKE_PAGESZ_1G, 1),
-#endif
-#endif
+#endif /* P1020MBG */
+#endif /* not L2 SRAM */
+#endif /* RAMBOOT/SPL */
};
int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index ba7a364..964bfcd 100644
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -38,6 +38,7 @@
#define __SW_BOOT_MASK 0x03
#define __SW_BOOT_NOR 0xe4
#define __SW_BOOT_SD 0x54
+#define CONFIG_SYS_L2_SIZE (256 << 10)
#endif
#if defined(CONFIG_P1020UTM)
@@ -46,6 +47,7 @@
#define __SW_BOOT_MASK 0x03
#define __SW_BOOT_NOR 0xe0
#define __SW_BOOT_SD 0x50
+#define CONFIG_SYS_L2_SIZE (256 << 10)
#endif
#if defined(CONFIG_P1020RDB)
@@ -61,6 +63,7 @@
#define __SW_BOOT_SD 0x9c
#define __SW_BOOT_NAND 0xec
#define __SW_BOOT_PCIE 0x6c
+#define CONFIG_SYS_L2_SIZE (256 << 10)
#endif
#if defined(CONFIG_P1021RDB)
@@ -78,6 +81,7 @@
#define __SW_BOOT_SD 0x9c
#define __SW_BOOT_NAND 0xec
#define __SW_BOOT_PCIE 0x6c
+#define CONFIG_SYS_L2_SIZE (256 << 10)
#endif
#if defined(CONFIG_P1024RDB)
@@ -91,6 +95,7 @@
#define __SW_BOOT_SPI 0x08
#define __SW_BOOT_SD 0x04
#define __SW_BOOT_NAND 0x0c
+#define CONFIG_SYS_L2_SIZE (256 << 10)
#endif
#if defined(CONFIG_P1025RDB)
@@ -108,6 +113,7 @@
#define __SW_BOOT_SPI 0x08
#define __SW_BOOT_SD 0x04
#define __SW_BOOT_NAND 0x0c
+#define CONFIG_SYS_L2_SIZE (256 << 10)
#endif
#if defined(CONFIG_P2020RDB)
@@ -122,6 +128,14 @@
#define __SW_BOOT_SD 0x68 /* or 0x18 */
#define __SW_BOOT_NAND 0xe8
#define __SW_BOOT_PCIE 0xa8
+#define CONFIG_SYS_L2_SIZE (512 << 10)
+#endif
+
+#if CONFIG_SYS_L2_SIZE >= (512 << 10)
+/* must be 32-bit */
+#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
+#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
#endif
#ifdef CONFIG_SDCARD
@@ -149,14 +163,28 @@
#define CONFIG_SPL_FLUSH_IMAGE
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
-#define CONFIG_SYS_TEXT_BASE 0x00201000
#define CONFIG_SPL_TEXT_BASE 0xfffff000
#define CONFIG_SPL_MAX_SIZE (4 * 1024)
+
+#ifdef CONFIG_SYS_INIT_L2_ADDR
+/* We multiply CONFIG_SPL_MAX_SIZE by two to leave some room for BSS. */
+#define CONFIG_SYS_TEXT_BASE 0xf8f82000
+#define CONFIG_SPL_RELOC_TEXT_BASE \
+ (CONFIG_SYS_INIT_L2_END - CONFIG_SPL_MAX_SIZE * 2)
+#define CONFIG_SPL_RELOC_STACK \
+ (CONFIG_SYS_INIT_L2_END - CONFIG_SPL_MAX_SIZE * 2)
+#define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR)
+#define CONFIG_SYS_NAND_U_BOOT_START \
+ (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SPL_MAX_SIZE)
+#else
+#define CONFIG_SYS_TEXT_BASE 0x00201000
#define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000
#define CONFIG_SPL_RELOC_STACK 0x00100000
-#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) + CONFIG_SPL_MAX_SIZE)
#define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE)
#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
+#endif
+
+#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000)
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0
#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
#endif
@@ -261,39 +289,7 @@
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
/* Default settings for DDR3 */
-#ifdef CONFIG_P2020RDB
-#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
-#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202
-#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
-#define CONFIG_SYS_DDR_CS1_BNDS 0x00000000
-#define CONFIG_SYS_DDR_CS1_CONFIG 0x00000000
-#define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000
-
-#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
-#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
-#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
-#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
-
-#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
-#define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8645F607
-#define CONFIG_SYS_DDR_SR_CNTR 0x00000000
-#define CONFIG_SYS_DDR_RCW_1 0x00000000
-#define CONFIG_SYS_DDR_RCW_2 0x00000000
-#define CONFIG_SYS_DDR_CONTROL 0xC7000000 /* Type = DDR3 */
-#define CONFIG_SYS_DDR_CONTROL_2 0x24401000
-#define CONFIG_SYS_DDR_TIMING_4 0x00220001
-#define CONFIG_SYS_DDR_TIMING_5 0x02401400
-
-#define CONFIG_SYS_DDR_TIMING_3 0x00020000
-#define CONFIG_SYS_DDR_TIMING_0 0x00330104
-#define CONFIG_SYS_DDR_TIMING_1 0x6f6B4644
-#define CONFIG_SYS_DDR_TIMING_2 0x0FA88CCF
-#define CONFIG_SYS_DDR_CLK_CTRL 0x02000000
-#define CONFIG_SYS_DDR_MODE_1 0x00421422
-#define CONFIG_SYS_DDR_MODE_2 0x04000000
-#define CONFIG_SYS_DDR_INTERVAL 0x0C300100
-
-#else
+#ifndef CONFIG_P2020RDB
#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
@@ -334,13 +330,14 @@
* 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable
* 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3)
* 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1
+ * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 512K cacheable
+ * (early boot only)
* 0xff80_0000 0xff80_7fff NAND flash 32K non-cacheable CS1/0
* 0xff98_0000 0xff98_ffff PMC 64K non-cacheable CS2
* 0xffa0_0000 0xffaf_ffff CPLD 1M non-cacheable CS3
* 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable CS2
* 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
* 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable
- * 0xffd8_0000 0xffdf_ffff L2 SRAM Up to 512K cacheable
* 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
*/
--
1.7.9.5
^ permalink raw reply related [flat|nested] 81+ messages in thread
* [U-Boot] [PATCH v2 00/22] Convert p1_p2_rdb_pc to new spl
2012-10-30 2:04 ` [U-Boot] [PATCH v2 00/22] " Scott Wood
` (21 preceding siblings ...)
2012-10-30 2:05 ` [U-Boot] [PATCH v2 22/22] powerpc/mpc85xx/p2020rdb-pca: Use L2 SRAM for SPL boot Scott Wood
@ 2012-10-30 17:04 ` Tom Rini
2012-10-30 20:17 ` Scott Wood
22 siblings, 1 reply; 81+ messages in thread
From: Tom Rini @ 2012-10-30 17:04 UTC (permalink / raw)
To: u-boot
On Mon, Oct 29, 2012 at 09:04:48PM -0500, Scott Wood wrote:
> Tested on p2020rdb-pca and p1020rdb-pc.
>
> Jos?? Miguel Gon??alves (1):
> Add u-boot-pad.bin target to the Makefile
>
> Scott Wood (21):
[snip]
> spl: rename u-boot-pad.bin to u-boot-with-spl.bin
OK, one thing I'm missing is where is PAD_TO being set? I thought when
this was talked about before I was saying we should set a soft default
of 1 or something so we can re-use this target? Looking at Stefan's
mpc5200 SPL series, u-boot-with-spl.bin would be fine there, if there
was a default PAD_TO set.
--
Tom
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^ permalink raw reply [flat|nested] 81+ messages in thread* [U-Boot] [PATCH v2 00/22] Convert p1_p2_rdb_pc to new spl
2012-10-30 17:04 ` [U-Boot] [PATCH v2 00/22] Convert p1_p2_rdb_pc to new spl Tom Rini
@ 2012-10-30 20:17 ` Scott Wood
2012-10-30 21:12 ` Tom Rini
0 siblings, 1 reply; 81+ messages in thread
From: Scott Wood @ 2012-10-30 20:17 UTC (permalink / raw)
To: u-boot
On 10/30/2012 12:04:40 PM, Tom Rini wrote:
> On Mon, Oct 29, 2012 at 09:04:48PM -0500, Scott Wood wrote:
>
> > Tested on p2020rdb-pca and p1020rdb-pc.
> >
> > Jos?? Miguel Gon??alves (1):
> > Add u-boot-pad.bin target to the Makefile
> >
> > Scott Wood (21):
> [snip]
> > spl: rename u-boot-pad.bin to u-boot-with-spl.bin
>
> OK, one thing I'm missing is where is PAD_TO being set?
It isn't.
> I thought when this was talked about before I was saying we should
> set a soft default
> of 1 or something so we can re-use this target?
Right, I'd forgotten about that. It seems to work though with PAD_TO
being empty.
-Scott
^ permalink raw reply [flat|nested] 81+ messages in thread
* [U-Boot] [PATCH v2 00/22] Convert p1_p2_rdb_pc to new spl
2012-10-30 20:17 ` Scott Wood
@ 2012-10-30 21:12 ` Tom Rini
2012-11-13 22:42 ` Scott Wood
0 siblings, 1 reply; 81+ messages in thread
From: Tom Rini @ 2012-10-30 21:12 UTC (permalink / raw)
To: u-boot
On Tue, Oct 30, 2012 at 03:17:04PM -0500, Scott Wood wrote:
> On 10/30/2012 12:04:40 PM, Tom Rini wrote:
> >On Mon, Oct 29, 2012 at 09:04:48PM -0500, Scott Wood wrote:
> >
> >> Tested on p2020rdb-pca and p1020rdb-pc.
> >>
> >> Jos?? Miguel Gon??alves (1):
> >> Add u-boot-pad.bin target to the Makefile
> >>
> >> Scott Wood (21):
> >[snip]
> >> spl: rename u-boot-pad.bin to u-boot-with-spl.bin
> >
> >OK, one thing I'm missing is where is PAD_TO being set?
>
> It isn't.
>
> >I thought when this was talked about before I was saying we should
> >set a soft default
> >of 1 or something so we can re-use this target?
>
> Right, I'd forgotten about that. It seems to work though with
> PAD_TO being empty.
Indeed. Shame on me for not checking that before but a trivial test
locally shows that works.
Assuming you have no further comments about Stefan's mpc5200 series I'll
pull his in tomorrow'ish, but with a few parts of your series (these two
patches, the fixup gcc test one) as well instead of what he has, to try
and make things go a little quicker.
--
Tom
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^ permalink raw reply [flat|nested] 81+ messages in thread
* [U-Boot] [PATCH v2 00/22] Convert p1_p2_rdb_pc to new spl
2012-10-30 21:12 ` Tom Rini
@ 2012-11-13 22:42 ` Scott Wood
0 siblings, 0 replies; 81+ messages in thread
From: Scott Wood @ 2012-11-13 22:42 UTC (permalink / raw)
To: u-boot
On 10/30/2012 04:12:56 PM, Tom Rini wrote:
> On Tue, Oct 30, 2012 at 03:17:04PM -0500, Scott Wood wrote:
> > On 10/30/2012 12:04:40 PM, Tom Rini wrote:
> > >On Mon, Oct 29, 2012 at 09:04:48PM -0500, Scott Wood wrote:
> > >
> > >> Tested on p2020rdb-pca and p1020rdb-pc.
> > >>
> > >> Jos?? Miguel Gon??alves (1):
> > >> Add u-boot-pad.bin target to the Makefile
> > >>
> > >> Scott Wood (21):
> > >[snip]
> > >> spl: rename u-boot-pad.bin to u-boot-with-spl.bin
> > >
> > >OK, one thing I'm missing is where is PAD_TO being set?
> >
> > It isn't.
> >
> > >I thought when this was talked about before I was saying we should
> > >set a soft default
> > >of 1 or something so we can re-use this target?
> >
> > Right, I'd forgotten about that. It seems to work though with
> > PAD_TO being empty.
>
> Indeed. Shame on me for not checking that before but a trivial test
> locally shows that works.
>
> Assuming you have no further comments about Stefan's mpc5200 series
> I'll
> pull his in tomorrow'ish, but with a few parts of your series (these
> two
> patches, the fixup gcc test one) as well instead of what he has, to
> try
> and make things go a little quicker.
Were you still going to do this, or should I go ahead and prepare a
pull request for my stuff?
-Scott
^ permalink raw reply [flat|nested] 81+ messages in thread