[U-Boot] [PATCH resend 1/3] tegra20: complete periph_id enum

[U-Boot] [PATCH resend 1/3] tegra20: complete periph_id enum

[Lucas Stach]

Most Tegra boards output the ULPI reference clock on pad DEV2.

Complete the periph_id enum so that we are able to enable this
clock output circuit.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Acked-by: Simon Glass <sjg@chromium.org>
---
 arch/arm/cpu/tegra20-common/clock.c       | 1 +
 arch/arm/include/asm/arch-tegra20/clock.h | 6 ++++++
 2 Dateien ge?ndert, 7 Zeilen hinzugef?gt(+)

diff --git a/arch/arm/cpu/tegra20-common/clock.c b/arch/arm/cpu/tegra20-common/clock.c
index 2403874..d9bb851 100644
--- a/arch/arm/cpu/tegra20-common/clock.c
+++ b/arch/arm/cpu/tegra20-common/clock.c
@@ -502,6 +502,7 @@ static int clock_periph_id_isvalid(enum periph_id id)
 		case PERIPH_ID_RESERVED81:
 		case PERIPH_ID_RESERVED82:
 		case PERIPH_ID_RESERVED83:
+		case PERIPH_ID_RESERVED91:
 			printf("Peripheral id %d is reserved\n", id);
 			break;
 		default:
diff --git a/arch/arm/include/asm/arch-tegra20/clock.h b/arch/arm/include/asm/arch-tegra20/clock.h
index ff83bbf..20db9e6 100644
--- a/arch/arm/include/asm/arch-tegra20/clock.h
+++ b/arch/arm/include/asm/arch-tegra20/clock.h
@@ -175,6 +175,12 @@ enum periph_id {
 
 	/* 88 */
 	PERIPH_ID_CRAM2,
+	PERIPH_ID_SYNC_CLK_DOUBLER,
+	PERIPH_ID_CLK_M_DOUBLER,
+	PERIPH_ID_RESERVED91,
+	PERIPH_ID_SUS_OUT,
+	PERIPH_ID_DEV2_OUT,
+	PERIPH_ID_DEV1_OUT,
 
 	PERIPH_ID_COUNT,
 	PERIPH_ID_NONE = -1,
-- 
1.7.11.4

[U-Boot] [PATCH v3 2/3] tegra20: add clock_set_pllout function

[Lucas Stach]

Common practice on Tegra 2 boards is to use the pllp_out4 FO
to generate the ULPI reference clock. For this to work we have
to override the default hardware generated output divider.

This function adds a clean way to do so.

v2:
- check if pllout is valid

v3:
- fix checkpatch complaints

Signed-off-by: Lucas Stach <dev@lynxeye.de>
---
 arch/arm/cpu/tegra20-common/clock.c         | 38 +++++++++++++++++++++++++++++
 arch/arm/cpu/tegra20-common/warmboot_avp.c  |  2 +-
 arch/arm/include/asm/arch-tegra20/clk_rst.h | 11 +++++++--
 arch/arm/include/asm/arch-tegra20/clock.h   | 19 +++++++++++++++
 4 Dateien ge?ndert, 67 Zeilen hinzugef?gt(+), 3 Zeilen entfernt(-)

diff --git a/arch/arm/cpu/tegra20-common/clock.c b/arch/arm/cpu/tegra20-common/clock.c
index d9bb851..701359f 100644
--- a/arch/arm/cpu/tegra20-common/clock.c
+++ b/arch/arm/cpu/tegra20-common/clock.c
@@ -396,6 +396,16 @@ static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = {
 	NONE(CRAM2),
 };
 
+/* number of clock outputs of a PLL */
+static const u8 pll_num_clkouts[] = {
+	1,	/* PLLC */
+	1,	/* PLLM */
+	4,	/* PLLP */
+	1,	/* PLLA */
+	0,	/* PLLU */
+	0,	/* PLLD */
+};
+
 /*
  * Get the oscillator frequency, from the corresponding hardware configuration
  * field.
@@ -604,6 +614,34 @@ unsigned long clock_get_periph_rate(enum periph_id periph_id,
 		(readl(reg) & OUT_CLK_DIVISOR_MASK) >> OUT_CLK_DIVISOR_SHIFT);
 }
 
+int clock_set_pllout(enum clock_id clkid, enum pll_out_id pllout, unsigned rate)
+{
+	struct clk_pll *pll = get_pll(clkid);
+	int data = 0, div = 0, offset = 0;
+
+	if (!clock_id_is_pll(clkid))
+		return -1;
+
+	if (pllout + 1 > pll_num_clkouts[clkid])
+		return -1;
+
+	div = clk_get_divider(8, pll_rate[clkid], rate);
+
+	if (div < 0)
+		return -1;
+
+	/* out2 and out4 are in the high part of the register */
+	if (pllout == PLL_OUT2 || pllout == PLL_OUT4)
+		offset = 16;
+
+	data = (div << PLL_OUT_RATIO_SHIFT) |
+			PLL_OUT_OVRRIDE | PLL_OUT_CLKEN | PLL_OUT_RSTN;
+	clrsetbits_le32(&pll->pll_out[pllout >> 1],
+			PLL_OUT_RATIO_MASK << offset, data << offset);
+
+	return 0;
+}
+
 /**
  * Find the best available 7.1 format divisor given a parent clock rate and
  * required child clock rate. This function assumes that a second-stage
diff --git a/arch/arm/cpu/tegra20-common/warmboot_avp.c b/arch/arm/cpu/tegra20-common/warmboot_avp.c
index 80a5a15..f08da1b 100644
--- a/arch/arm/cpu/tegra20-common/warmboot_avp.c
+++ b/arch/arm/cpu/tegra20-common/warmboot_avp.c
@@ -214,7 +214,7 @@ void wb_start(void)
 
 	reg = PLLM_OUT1_RSTN_RESET_DISABLE | PLLM_OUT1_CLKEN_ENABLE |
 	      PLLM_OUT1_RATIO_VAL_8;
-	writel(reg, &clkrst->crc_pll[CLOCK_ID_MEMORY].pll_out);
+	writel(reg, &clkrst->crc_pll[CLOCK_ID_MEMORY].pll_out[0]);
 
 	reg = SCLK_SWAKE_FIQ_SRC_PLLM_OUT1 | SCLK_SWAKE_IRQ_SRC_PLLM_OUT1 |
 	      SCLK_SWAKE_RUN_SRC_PLLM_OUT1 | SCLK_SWAKE_IDLE_SRC_PLLM_OUT1 |
diff --git a/arch/arm/include/asm/arch-tegra20/clk_rst.h b/arch/arm/include/asm/arch-tegra20/clk_rst.h
index 8c3be91..7b548c2 100644
--- a/arch/arm/include/asm/arch-tegra20/clk_rst.h
+++ b/arch/arm/include/asm/arch-tegra20/clk_rst.h
@@ -27,8 +27,7 @@
 /* PLL registers - there are several PLLs in the clock controller */
 struct clk_pll {
 	uint pll_base;		/* the control register */
-	uint pll_out;		/* output control */
-	uint reserved;
+	uint pll_out[2];	/* output control */
 	uint pll_misc;		/* other misc things */
 };
 
@@ -112,6 +111,14 @@ struct clk_rst_ctlr {
 #define PLL_DIVM_SHIFT		0
 #define PLL_DIVM_MASK		(0x1f << PLL_DIVM_SHIFT)
 
+/* CLK_RST_CONTROLLER_PLLx_OUTx_0 */
+#define PLL_OUT_RSTN		(1 << 0)
+#define PLL_OUT_CLKEN		(1 << 1)
+#define PLL_OUT_OVRRIDE		(1 << 2)
+
+#define PLL_OUT_RATIO_SHIFT	8
+#define PLL_OUT_RATIO_MASK	(0xffU << PLL_OUT_RATIO_SHIFT)
+
 /* CLK_RST_CONTROLLER_PLLx_MISC_0 */
 #define PLL_CPCON_SHIFT		8
 #define PLL_CPCON_MASK		(15U << PLL_CPCON_SHIFT)
diff --git a/arch/arm/include/asm/arch-tegra20/clock.h b/arch/arm/include/asm/arch-tegra20/clock.h
index 20db9e6..4ee6a50 100644
--- a/arch/arm/include/asm/arch-tegra20/clock.h
+++ b/arch/arm/include/asm/arch-tegra20/clock.h
@@ -186,6 +186,13 @@ enum periph_id {
 	PERIPH_ID_NONE = -1,
 };
 
+enum pll_out_id {
+	PLL_OUT1,
+	PLL_OUT2,
+	PLL_OUT3,
+	PLL_OUT4
+};
+
 /* Converts a clock number to a clock register: 0=L, 1=H, 2=U */
 #define PERIPH_REG(id) ((id) >> 5)
 
@@ -218,6 +225,18 @@ unsigned long clock_start_pll(enum clock_id id, u32 divm, u32 divn,
 		u32 divp, u32 cpcon, u32 lfcon);
 
 /**
+ * Set PLL output frequency
+ *
+ * @param clkid		clock id
+ * @param pllout	pll output id (
+ * @param rate		desired output rate
+ *
+ * @return 0 if ok, -1 on error (invalid clock id or no suitable divider)
+ */
+int clock_set_pllout(enum clock_id clkid, enum pll_out_id pllout,
+		unsigned rate);
+
+/**
  * Read low-level parameters of a PLL.
  *
  * @param id	clock id to read (note: USB is not supported)
-- 
1.7.11.4

[U-Boot] [PATCH v2 3/3] tegra20: rework UART GPIO handling

[Lucas Stach]

Rename board provided gpio_config_uart() to
gpio_early_init_uart() as it does the same thing as the equally
called function provided by the uart-switch code. This allows
to simply call this function in early board init whether or not
we are building with CONFIG_UART_SWITCH defined.

Also provide a weak symbol for this function, to avoid the
need to provide this function for boards that don't need any
fixup.

This patch supersedes the earlier posted
"tegra: convert gpio_config_uart to weak symbol".
Build tested with MAKEALL -s tegra20

v2:
- fix checkpatch warning

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Acked-by: Simon Glass <sjg@chromium.org>
---
 arch/arm/cpu/arm720t/tegra20/board.h   |  2 +-
 arch/arm/cpu/arm720t/tegra20/spl.c     |  4 ----
 board/avionic-design/common/tamonten.c |  7 -------
 board/compal/paz00/paz00.c             |  7 -------
 board/compulab/trimslice/trimslice.c   |  7 -------
 board/nvidia/common/board.c            | 12 ++++++++----
 board/nvidia/harmony/harmony.c         |  7 -------
 board/nvidia/seaboard/seaboard.c       |  2 +-
 board/nvidia/whistler/whistler.c       |  7 -------
 9 Dateien ge?ndert, 10 Zeilen hinzugef?gt(+), 45 Zeilen entfernt(-)

diff --git a/arch/arm/cpu/arm720t/tegra20/board.h b/arch/arm/cpu/arm720t/tegra20/board.h
index 61b91c0..260767d 100644
--- a/arch/arm/cpu/arm720t/tegra20/board.h
+++ b/arch/arm/cpu/arm720t/tegra20/board.h
@@ -22,4 +22,4 @@
  */
 
 void board_init_uart_f(void);
-void gpio_config_uart(void);
+void gpio_early_init_uart(void);
diff --git a/arch/arm/cpu/arm720t/tegra20/spl.c b/arch/arm/cpu/arm720t/tegra20/spl.c
index 6c16dce..4f54117 100644
--- a/arch/arm/cpu/arm720t/tegra20/spl.c
+++ b/arch/arm/cpu/arm720t/tegra20/spl.c
@@ -65,11 +65,7 @@ void board_init_f(ulong dummy)
 	board_init_uart_f();
 
 	/* Initialize periph GPIOs */
-#ifdef CONFIG_SPI_UART_SWITCH
 	gpio_early_init_uart();
-#else
-	gpio_config_uart();
-#endif
 
 	/*
 	 * We call relocate_code() with relocation target same as the
diff --git a/board/avionic-design/common/tamonten.c b/board/avionic-design/common/tamonten.c
index 93f12ea..6d9369d 100644
--- a/board/avionic-design/common/tamonten.c
+++ b/board/avionic-design/common/tamonten.c
@@ -41,13 +41,6 @@
 #include <mmc.h>
 #endif
 
-/*
- * Routine: gpio_config_uart
- * Description: Does nothing on Tamonten - no conflict w/SPI.
- */
-void gpio_config_uart(void)
-{
-}
 
 #ifdef CONFIG_BOARD_EARLY_INIT_F
 void gpio_early_init(void)
diff --git a/board/compal/paz00/paz00.c b/board/compal/paz00/paz00.c
index 0f8f167..6aa2e57 100644
--- a/board/compal/paz00/paz00.c
+++ b/board/compal/paz00/paz00.c
@@ -24,13 +24,6 @@
 #include <mmc.h>
 #endif
 
-/*
- * Routine: gpio_config_uart
- * Description: Does nothing on Paz00 - no conflict w/SPI.
- */
-void gpio_config_uart(void)
-{
-}
 
 #ifdef CONFIG_TEGRA_MMC
 /*
diff --git a/board/compulab/trimslice/trimslice.c b/board/compulab/trimslice/trimslice.c
index 893cca8..c589a06 100644
--- a/board/compulab/trimslice/trimslice.c
+++ b/board/compulab/trimslice/trimslice.c
@@ -34,13 +34,6 @@
 #include <mmc.h>
 #endif
 
-/*
- * Routine: gpio_config_uart
- * Description: Does nothing on TrimSlice - no UART-related GPIOs.
- */
-void gpio_config_uart(void)
-{
-}
 
 void pin_mux_spi(void)
 {
diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c
index afe832a..db2c2cf 100644
--- a/board/nvidia/common/board.c
+++ b/board/nvidia/common/board.c
@@ -72,6 +72,13 @@ void __pin_mux_spi(void)
 
 void pin_mux_spi(void) __attribute__((weak, alias("__pin_mux_spi")));
 
+void __gpio_early_init_uart(void)
+{
+}
+
+void gpio_early_init_uart(void)
+__attribute__((weak, alias("__gpio_early_init_uart")));
+
 /*
  * Routine: power_det_init
  * Description: turn off power detects
@@ -156,11 +163,8 @@ int board_early_init_f(void)
 
 	/* Initialize periph GPIOs */
 	gpio_early_init();
-#ifdef CONFIG_SPI_UART_SWITCH
 	gpio_early_init_uart();
-#else
-	gpio_config_uart();
-#endif
+
 	return 0;
 }
 #endif	/* EARLY_INIT */
diff --git a/board/nvidia/harmony/harmony.c b/board/nvidia/harmony/harmony.c
index b4a811d..da1649a 100644
--- a/board/nvidia/harmony/harmony.c
+++ b/board/nvidia/harmony/harmony.c
@@ -33,13 +33,6 @@
 #include <mmc.h>
 #endif
 
-/*
- * Routine: gpio_config_uart
- * Description: Does nothing on Harmony - no conflict w/SPI.
- */
-void gpio_config_uart(void)
-{
-}
 
 #ifdef CONFIG_TEGRA_MMC
 /*
diff --git a/board/nvidia/seaboard/seaboard.c b/board/nvidia/seaboard/seaboard.c
index 667f60a..d2df2df 100644
--- a/board/nvidia/seaboard/seaboard.c
+++ b/board/nvidia/seaboard/seaboard.c
@@ -46,7 +46,7 @@ static void gpio_config_uart_seaboard(void)
 	gpio_direction_output(GPIO_PI3, 0);
 }
 
-void gpio_config_uart(void)
+void gpio_early_init_uart(void)
 {
 	if (machine_is_ventana())
 		return;
diff --git a/board/nvidia/whistler/whistler.c b/board/nvidia/whistler/whistler.c
index 598b2e5..e8325fe 100644
--- a/board/nvidia/whistler/whistler.c
+++ b/board/nvidia/whistler/whistler.c
@@ -34,13 +34,6 @@
 #include <mmc.h>
 #endif
 
-/*
- * Routine: gpio_config_uart
- * Description: Does nothing on Whistler - no UART-related GPIOs.
- */
-void gpio_config_uart(void)
-{
-}
 
 /*
  * Routine: pin_mux_mmc
-- 
1.7.11.4

[U-Boot] [PATCH resend 1/3] tegra20: complete periph_id enum

[Tom Warren]

Lucas,

On Wed, Sep 26, 2012 at 9:19 AM, Tom Warren <TWarren@nvidia.com> wrote:
> Lucas,
>
>> -----Original Message-----
>> From: Lucas Stach [mailto:dev at lynxeye.de]
>> Sent: Tuesday, September 25, 2012 11:21 PM
>> To: Tom Warren
>> Cc: u-boot at lists.denx.de
>> Subject: [PATCH resend 1/3] tegra20: complete periph_id enum
>
> Please see http://www.denx.de/wiki/view/U-Boot/Patches#Sending_updated_patch_versions ("Sending updated patch versions"). It's hard to track these patches with disparate subject lines - they should all be grouped as '[PATCH n/3 v3] tegra20: ...', etc.  Also, your change logs ('v3 - fix checkpatch complaints', etc.) should be below the '---' line so they don't get included in the commit message.
>
> I'll apply these this time, since they're small, but please follow the rules on the wiki future updated patches. It makes it much easier for me to track these in Patchwork.
>
> Thanks,
>
> Tom
>>
>> Most Tegra boards output the ULPI reference clock on pad DEV2.
>>
>> Complete the periph_id enum so that we are able to enable this clock output
>> circuit.
>>
>> Signed-off-by: Lucas Stach <dev@lynxeye.de>
>> Acked-by: Stephen Warren <swarren@wwwdotorg.org>
>> Acked-by: Simon Glass <sjg@chromium.org>
>> ---
>>  arch/arm/cpu/tegra20-common/clock.c       | 1 +
>>  arch/arm/include/asm/arch-tegra20/clock.h | 6 ++++++
>>  2 Dateien ge?ndert, 7 Zeilen hinzugef?gt(+)
>>
>> diff --git a/arch/arm/cpu/tegra20-common/clock.c b/arch/arm/cpu/tegra20-
>> common/clock.c
>> index 2403874..d9bb851 100644
>> --- a/arch/arm/cpu/tegra20-common/clock.c
>> +++ b/arch/arm/cpu/tegra20-common/clock.c
>> @@ -502,6 +502,7 @@ static int clock_periph_id_isvalid(enum periph_id id)
>>               case PERIPH_ID_RESERVED81:
>>               case PERIPH_ID_RESERVED82:
>>               case PERIPH_ID_RESERVED83:
>> +             case PERIPH_ID_RESERVED91:
>>                       printf("Peripheral id %d is reserved\n", id);
>>                       break;
>>               default:
>> diff --git a/arch/arm/include/asm/arch-tegra20/clock.h
>> b/arch/arm/include/asm/arch-tegra20/clock.h
>> index ff83bbf..20db9e6 100644
>> --- a/arch/arm/include/asm/arch-tegra20/clock.h
>> +++ b/arch/arm/include/asm/arch-tegra20/clock.h
>> @@ -175,6 +175,12 @@ enum periph_id {
>>
>>       /* 88 */
>>       PERIPH_ID_CRAM2,
>> +     PERIPH_ID_SYNC_CLK_DOUBLER,
>> +     PERIPH_ID_CLK_M_DOUBLER,
>> +     PERIPH_ID_RESERVED91,
>> +     PERIPH_ID_SUS_OUT,
>> +     PERIPH_ID_DEV2_OUT,
>> +     PERIPH_ID_DEV1_OUT,
>>
>>       PERIPH_ID_COUNT,
>>       PERIPH_ID_NONE = -1,
>> --
>> 1.7.11.4
> --
> nvpublic
>

This series (3 patches) applied to u-boot-tegra/next and pushed to denx.de.

Thanks,

Tom