From mboxrd@z Thu Jan 1 00:00:00 1970 From: Scott Wood Date: Tue, 23 Oct 2012 20:40:20 -0500 Subject: [U-Boot] [PATCH 27/28] powerpc/mpc85xx: Rewrite spin table to comply with ePAPR v1.1 In-Reply-To: <1349718271-26503-27-git-send-email-yorksun@freescale.com> (from yorksun@freescale.com on Mon Oct 8 12:44:30 2012) References: <1349718271-26503-1-git-send-email-yorksun@freescale.com> <1349718271-26503-27-git-send-email-yorksun@freescale.com> Message-ID: <1351042820.7132.14@snotra> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On 10/08/2012 12:44:30 PM, York Sun wrote: > Move spin table to cached memory to comply with ePAPR v1.1. > Load R3 with 64-bit value if CONFIG_SYS_PPC64 is defined. > > 'M' bit is set for DDR TLB to maintain cache coherence. > > See details in doc/README.mpc85xx-spin-table. > > Signed-off-by: York Sun > --- > README | 6 + > arch/powerpc/cpu/mpc85xx/fdt.c | 13 ++- > arch/powerpc/cpu/mpc85xx/mp.c | 61 +++++----- > arch/powerpc/cpu/mpc85xx/mp.h | 5 +- > arch/powerpc/cpu/mpc85xx/release.S | 179 > +++++++++++++++++------------ > arch/powerpc/cpu/mpc85xx/tlb.c | 2 +- > arch/powerpc/include/asm/config_mpc85xx.h | 3 + > doc/README.mpc85xx-spin-table | 26 +++++ > 8 files changed, 183 insertions(+), 112 deletions(-) > create mode 100644 doc/README.mpc85xx-spin-table As we discussed internally, this patch needs to be RFC until changes go into Linux to be compatible with a cacheable spin table. -Scott