From mboxrd@z Thu Jan 1 00:00:00 1970 From: Scott Wood Date: Fri, 26 Oct 2012 18:34:52 -0500 Subject: [U-Boot] [PATCH] powerpc/mpc85xx: Temporary fix for spin table backward compatibility In-Reply-To: <1351289129-32544-1-git-send-email-yorksun@freescale.com> (from yorksun@freescale.com on Fri Oct 26 17:05:29 2012) Message-ID: <1351294492.23094.11@snotra> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On 10/26/2012 05:05:29 PM, York Sun wrote: > diff --git a/arch/powerpc/cpu/mpc85xx/release.S > b/arch/powerpc/cpu/mpc85xx/release.S > index 4ba44a9..b68272b 100644 > --- a/arch/powerpc/cpu/mpc85xx/release.S > +++ b/arch/powerpc/cpu/mpc85xx/release.S > @@ -351,6 +351,13 @@ __secondary_reset_vector: > .align L1_CACHE_SHIFT > .global __second_half_boot_page > __second_half_boot_page: > +#ifdef CONFIG_PPC_SPINTABLE_COMPATIBLE > + lis r3,(spin_table_compat - __second_half_boot_page)@h > + ori r3,r3,(spin_table_compat - __second_half_boot_page)@l > + add r3,r3,r11 /* r11 has the address of __second_half_boot_page > */ > + lwz r14,0(r3) > +#endif Please tab after the mnemonic. > #define EPAPR_MAGIC 0x45504150 > #define ENTRY_ADDR_UPPER 0 > #define ENTRY_ADDR_LOWER 4 > @@ -383,7 +390,24 @@ __second_half_boot_page: > stw r8,ENTRY_ADDR_LOWER(r10) > > /* spin waiting for addr */ > -3: lwz r4,ENTRY_ADDR_LOWER(r10) > +3: > +/* > + * To comply with ePAPR 1.1, the spin table has been moved to > cache-enabled > + * memory. Old OS may not work with this change. A patch is waiting > to be > + * accepted for Linux kernel. Other OS needs similar fix to spin > table. > + * For OSes with old spin table code, we can enable this temporary > fix by > + * setting environmental variable "spin_table_compat". For new OSes, > set > + * "spin_table_compat=no". After all OSes are fixed, we can remove > this macro > + * and related code. For now, it is enabled by default. > + */ Let's be realistic -- s/all OSes are fixed/Linux is fixed/ > + > +#ifdef CONFIG_PPC_SPINTABLE_COMPATIBLE > + .align L1_CACHE_SHIFT > + .global spin_table_compat > +spin_table_compat: > + .long 1 > +#endif Tab after .long > + > __spin_table_end: > .space 4096 - (__spin_table_end - __spin_table) > diff --git a/arch/powerpc/include/asm/config_mpc85xx.h > b/arch/powerpc/include/asm/config_mpc85xx.h > index 03baaee..29833bb 100644 > --- a/arch/powerpc/include/asm/config_mpc85xx.h > +++ b/arch/powerpc/include/asm/config_mpc85xx.h > @@ -27,6 +27,13 @@ > #error "Do not define CONFIG_SYS_CCSRBAR_DEFAULT in the board header > file." > #endif > > +/* > + * This macro should be removed when we no longer care about > backwards > + * compatibility with older operating systems. Cacheable spin table > support > + * will be added in Linux 3.8. > + */ > +#define CONFIG_PPC_SPINTABLE_COMPATIBLE Put the crystal ball away -- we don't know it will be in 3.8 (though hopefully it will be). We just know it won't make it any sooner than that (unless Kumar can push it as a bug fix, which seems unlikely). -Scott