From mboxrd@z Thu Jan 1 00:00:00 1970 From: Vasanth Ananthan Date: Fri, 23 Nov 2012 17:38:55 +0530 Subject: [U-Boot] [PATCH v2 1/4] Exynos5: Add clock support for SATA In-Reply-To: <1353672538-15610-1-git-send-email-vasanthananthan@gmail.com> References: <1353672538-15610-1-git-send-email-vasanthananthan@gmail.com> Message-ID: <1353672538-15610-2-git-send-email-vasanthananthan@gmail.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de This patch adds clock support for SATA Signed-off-by: Vasanth Ananthan --- arch/arm/cpu/armv7/exynos/clock.c | 22 ++++++++++++++++++++++ arch/arm/include/asm/arch-exynos/clk.h | 1 + 2 files changed, 23 insertions(+) diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index fe61f88..22b327b 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -26,6 +26,7 @@ #include #include #include +#include /* Epll Clock division values to achive different frequency output */ static struct set_epll_con_val exynos5_epll_div[] = { @@ -326,6 +327,19 @@ static unsigned long exynos4_get_uart_clk(int dev_index) return uclk; } +static unsigned long exynos5_get_sata_clk(void) +{ + struct exynos5_clock *clk = + (struct exynos5_clock *)samsung_get_base_clock(); + + /* + * This clock is used as a input for 1ms timer, so return + * the clock equivalent to 1 MHz + */ + + return CONFIG_SYS_CLK_FREQ / 10; +} + /* exynos5: return uart clock frequency */ static unsigned long exynos5_get_uart_clk(int dev_index) { @@ -963,6 +977,14 @@ unsigned long get_uart_clk(int dev_index) return exynos4_get_uart_clk(dev_index); } +unsigned long get_sata_clock(void) +{ + if (cpu_is_exynos5()) + return exynos5_get_sata_clk(); + + return -ENOSYS; +} + void set_mmc_clk(int dev_index, unsigned int div) { if (cpu_is_exynos5()) diff --git a/arch/arm/include/asm/arch-exynos/clk.h b/arch/arm/include/asm/arch-exynos/clk.h index cd12323..182ed95 100644 --- a/arch/arm/include/asm/arch-exynos/clk.h +++ b/arch/arm/include/asm/arch-exynos/clk.h @@ -42,5 +42,6 @@ void set_i2s_clk_source(void); int set_i2s_clk_prescaler(unsigned int src_frq, unsigned int dst_frq); int set_epll_clk(unsigned long rate); int set_spi_clk(int periph_id, unsigned int rate); +unsigned long get_sata_clk(void); #endif -- 1.7.9.5