From mboxrd@z Thu Jan  1 00:00:00 1970
From: Scott Wood <scottwood@freescale.com>
Date: Wed, 19 Dec 2012 13:02:44 -0600
Subject: [U-Boot] [PATCH] NAND: allow custom SW ECC when using nand plat
 driver
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On 12/18/2012 05:27:00 PM, Chris Kiick wrote:
> Allow boards to set their own ECC layouts and functions in  
> NAND_PLAT_INIT
> without being stomped on by nand_base.c intialization.
> 
> Signed-off-by: ckiick <chris@kiicks.net>
> ---
>  drivers/mtd/nand/nand_base.c |   11 +++++++----
>  drivers/mtd/nand/nand_plat.c |    4 ++--
>  include/configs/qong.h       |    2 +-
>  3 files changed, 10 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/mtd/nand/nand_base.c  
> b/drivers/mtd/nand/nand_base.c
> index a2d06be..614fc72 100644
> --- a/drivers/mtd/nand/nand_base.c
> +++ b/drivers/mtd/nand/nand_base.c
> @@ -3035,8 +3035,10 @@ int nand_scan_tail(struct mtd_info *mtd)
>          chip->ecc.mode = NAND_ECC_SOFT;
> 
>      case NAND_ECC_SOFT:
> -        chip->ecc.calculate = nand_calculate_ecc;
> -        chip->ecc.correct = nand_correct_data;
> +        if (!chip->ecc.calculate)
> +            chip->ecc.calculate = nand_calculate_ecc;
> +        if (!chip->ecc.correct)
> +            chip->ecc.correct = nand_correct_data;
>          chip->ecc.read_page = nand_read_page_swecc;
>          chip->ecc.read_subpage = nand_read_subpage;
>          chip->ecc.write_page = nand_write_page_swecc;
> @@ -3044,9 +3046,10 @@ int nand_scan_tail(struct mtd_info *mtd)
>          chip->ecc.write_page_raw = nand_write_page_raw;
>          chip->ecc.read_oob = nand_read_oob_std;
>          chip->ecc.write_oob = nand_write_oob_std;
> -        if (!chip->ecc.size)
> +        if (!chip->ecc.size) {
>              chip->ecc.size = 256;
> -        chip->ecc.bytes = 3;
> +            chip->ecc.bytes = 3;
> +        }
>          break;
> 
>      case NAND_ECC_SOFT_BCH:

How is this part specific to nand plat?

I'm not sure how specifying your own ECC functions fits with the  
purpose of either NAND_ECC_SOFT or nand plat.

> diff --git a/drivers/mtd/nand/nand_plat.c  
> b/drivers/mtd/nand/nand_plat.c
> index 37a0206..b3bda11 100644
> --- a/drivers/mtd/nand/nand_plat.c
> +++ b/drivers/mtd/nand/nand_plat.c
> @@ -8,7 +8,7 @@
>  /* Your board must implement the following macros:
>   *  NAND_PLAT_WRITE_CMD(chip, cmd)
>   *  NAND_PLAT_WRITE_ADR(chip, cmd)
> - *  NAND_PLAT_INIT()
> + *  NAND_PLAT_INIT(nand)
>   *
>   * It may also implement the following:
>   *  NAND_PLAT_DEV_READY(chip)
> @@ -53,7 +53,7 @@ int board_nand_init(struct nand_chip *nand)
>  #endif
> 
>  #ifdef NAND_PLAT_INIT
> -    NAND_PLAT_INIT();
> +    NAND_PLAT_INIT(nand);
>  #endif
> 
>      nand->cmd_ctrl = plat_cmd_ctrl;
> diff --git a/include/configs/qong.h b/include/configs/qong.h
> index d9bf201..077cbae 100644
> --- a/include/configs/qong.h
> +++ b/include/configs/qong.h
> @@ -226,7 +226,7 @@ extern int qong_nand_rdy(void *chip);
>  #define CONFIG_NAND_PLAT
>  #define CONFIG_SYS_MAX_NAND_DEVICE     1
>  #define CONFIG_SYS_NAND_BASE    CS3_BASE
> -#define NAND_PLAT_INIT() qong_nand_plat_init(nand)
> +#define NAND_PLAT_INIT(nand) qong_nand_plat_init(nand)
> 
>  #define QONG_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1  
> << 24))
>  #define QONG_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1  
> << 23))

This part looks unrelated.

-Scott