[U-Boot] [PATCH 05/11] Blackfin: bf60x: support big cplb page

Sonic Zhang
2013-02-07T07:47:32Z

From: Bob Liu <lliubbo@gmail.com>

Bf60x support 16K, 64K, 16M and 64M cplb pages, this patch add support for them.
So that bf609-ezkit can use it's 128M memory.

Signed-off-by: Bob Liu <lliubbo@gmail.com>
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
---
arch/blackfin/include/asm/cplb.h | 17 +++++++++++------
arch/blackfin/lib/board.c | 27 ++++++++++++++++++++-------
2 files changed, 31 insertions(+), 13 deletions(-)

diff --git a/arch/blackfin/include/asm/cplb.h b/arch/blackfin/include/asm/cplb.h
index cc21e93..afdc920 100644
--- a/arch/blackfin/include/asm/cplb.h
+++ b/arch/blackfin/include/asm/cplb.h
@@ -45,9 +45,14 @@
#define CPLB_INOCACHE CPLB_USER_RD | CPLB_VALID
#define CPLB_IDOCACHE CPLB_INOCACHE | CPLB_L1_CHBL

-/* Data Attibutes*/
+#if defined(__ADSPBF60x__)
+#define PAGE_SIZE (PAGE_SIZE_16MB)
+#else
+#define PAGE_SIZE (PAGE_SIZE_4MB)
+#endif

-#define SDRAM_IGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID)
+/* Data Attibutes*/
+#define SDRAM_IGENERIC (PAGE_SIZE | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID)
#define SDRAM_IKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
#define L1_IMEMORY (PAGE_SIZE_1MB | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
#define SDRAM_INON_CHBL (PAGE_SIZE_4MB | CPLB_USER_RD | CPLB_VALID)
@@ -59,18 +64,18 @@
#endif

#ifdef CONFIG_DCACHE_WB /*Write Back Policy */
-#define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
+#define SDRAM_DGENERIC (PAGE_SIZE | CPLB_L1_CHBL | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
#define SDRAM_DNON_CHBL (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
#define SDRAM_DKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_USER_WR | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158_WORKAROUND)
#define L1_DMEMORY (PAGE_SIZE_4MB | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
-#define SDRAM_EBIU (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
+#define SDRAM_EBIU (PAGE_SIZE | CPLB_DIRTY | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158_WORKAROUND)

#else /*Write Through */
-#define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
+#define SDRAM_DGENERIC (PAGE_SIZE | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
#define SDRAM_DNON_CHBL (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
#define SDRAM_DKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158_WORKAROUND)
#define L1_DMEMORY (PAGE_SIZE_4MB | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
-#define SDRAM_EBIU (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
+#define SDRAM_EBIU (PAGE_SIZE | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
#endif

#endif /* _CPLB_H */
diff --git a/arch/blackfin/lib/board.c b/arch/blackfin/lib/board.c
index 098f685..e3f7fe3 100644
--- a/arch/blackfin/lib/board.c
+++ b/arch/blackfin/lib/board.c
@@ -94,12 +94,12 @@ static void display_global_data(void)
printf(" \\-bi_flashoffset: %lx\n", bd->bi_flashoffset);
}

-#define CPLB_PAGE_SIZE (4 * 1024 * 1024)
-#define CPLB_PAGE_MASK (~(CPLB_PAGE_SIZE - 1))
void init_cplbtables(void)
{
volatile uint32_t *ICPLB_ADDR, *ICPLB_DATA;
volatile uint32_t *DCPLB_ADDR, *DCPLB_DATA;
+ uint32_t cplb_page_size;
+ uint32_t cplb_page_mask;
uint32_t extern_memory;
size_t i;

@@ -127,12 +127,19 @@ void init_cplbtables(void)
icplb_add(0xFFA00000, L1_IMEMORY);
dcplb_add(0xFF800000, L1_DMEMORY);
++i;
+#if defined(__ADSPBF60x__)
+ icplb_add(0x0, 0x0);
+ dcplb_add(CONFIG_SYS_FLASH_BASE, SDRAM_EBIU);
+ ++i;
+#endif
+ cplb_page_size = (4 * 1024 * 1024);
+ cplb_page_mask = (~(cplb_page_size - 1));

if (CONFIG_MEM_SIZE) {
uint32_t mbase = CONFIG_SYS_MONITOR_BASE;
uint32_t mend = mbase + CONFIG_SYS_MONITOR_LEN;
- mbase &= CPLB_PAGE_MASK;
- mend &= CPLB_PAGE_MASK;
+ mbase &= cplb_page_mask;
+ mend &= cplb_page_mask;

icplb_add(mbase, SDRAM_IKERNEL);
dcplb_add(mbase, SDRAM_DKERNEL);
@@ -150,9 +157,11 @@ void init_cplbtables(void)
}
}

+#ifndef __ADSPBF60x__
icplb_add(0x20000000, SDRAM_INON_CHBL);
dcplb_add(0x20000000, SDRAM_EBIU);
++i;
+#endif

/* Add entries for the rest of external RAM up to the bootrom */
extern_memory = 0;
@@ -163,14 +172,18 @@ void init_cplbtables(void)
++i;
icplb_add(extern_memory, SDRAM_IKERNEL);
dcplb_add(extern_memory, SDRAM_DKERNEL);
- extern_memory += CPLB_PAGE_SIZE;
+ extern_memory += cplb_page_size;
++i;
#endif

- while (i < 16 && extern_memory < (CONFIG_SYS_MONITOR_BASE & CPLB_PAGE_MASK)) {
+#if defined(__ADSPBF60x__)
+ cplb_page_size = (16 * 1024 * 1024);
+ cplb_page_mask = (~(cplb_page_size - 1));
+#endif
+ while (i < 16 && extern_memory < (CONFIG_SYS_MONITOR_BASE & cplb_page_mask)) {
icplb_add(extern_memory, SDRAM_IGENERIC);
dcplb_add(extern_memory, SDRAM_DGENERIC);
- extern_memory += CPLB_PAGE_SIZE;
+ extern_memory += cplb_page_size;
++i;
}
while (i < 16) {
--
1.7.0.4