* [U-Boot] [PATCH] am33xx:ddr:Fix config_sdram to work for all DDR
@ 2013-03-08 17:40 Tom Rini
2013-03-26 14:52 ` [U-Boot] " Tom Rini
0 siblings, 1 reply; 2+ messages in thread
From: Tom Rini @ 2013-03-08 17:40 UTC (permalink / raw)
To: u-boot
From: Steve Kipisz <s-kipisz2@ti.com>
The original write to sdram_config is correct for DDR3 but incorrect
for DDR2 so SPL was hanging. For DDR2, the write to sdram_config
should be after the writes to ref_ctrl. This was working for DDR3
because there was a write of 0x2800 to ref_ctrl before a write
to sdram_config.
Tested on: GP EVM 1.1A (DDR2), GP EVM 1.5A (DDR3),
Beaglebone A6 (DDR2), Beagleone Blacd A4A (DDR3)
Signed-off-by: Steve Kipisz <s-kipisz2@ti.com>
---
arch/arm/cpu/armv7/am33xx/ddr.c | 5 ++++-
1 files changed, 4 insertions(+), 1 deletions(-)
diff --git a/arch/arm/cpu/armv7/am33xx/ddr.c b/arch/arm/cpu/armv7/am33xx/ddr.c
index 448cc40..7932a39 100644
--- a/arch/arm/cpu/armv7/am33xx/ddr.c
+++ b/arch/arm/cpu/armv7/am33xx/ddr.c
@@ -54,10 +54,13 @@ void config_sdram(const struct emif_regs *regs)
writel(0x2800, &emif_reg->emif_sdram_ref_ctrl);
writel(regs->zq_config, &emif_reg->emif_zq_config);
writel(regs->sdram_config, &cstat->secure_emif_sdram_config);
+ writel(regs->sdram_config, &emif_reg->emif_sdram_config);
+ writel(regs->ref_ctrl, &emif_reg->emif_sdram_ref_ctrl);
+ writel(regs->ref_ctrl, &emif_reg->emif_sdram_ref_ctrl_shdw);
}
- writel(regs->sdram_config, &emif_reg->emif_sdram_config);
writel(regs->ref_ctrl, &emif_reg->emif_sdram_ref_ctrl);
writel(regs->ref_ctrl, &emif_reg->emif_sdram_ref_ctrl_shdw);
+ writel(regs->sdram_config, &emif_reg->emif_sdram_config);
}
/**
--
1.7.2.3
^ permalink raw reply related [flat|nested] 2+ messages in thread
* [U-Boot] am33xx:ddr:Fix config_sdram to work for all DDR
2013-03-08 17:40 [U-Boot] [PATCH] am33xx:ddr:Fix config_sdram to work for all DDR Tom Rini
@ 2013-03-26 14:52 ` Tom Rini
0 siblings, 0 replies; 2+ messages in thread
From: Tom Rini @ 2013-03-26 14:52 UTC (permalink / raw)
To: u-boot
On Fri, Mar 08, 2013 at 07:40:58AM -0000, Tom Rini wrote:
> From: Steve Kipisz <s-kipisz2@ti.com>
>
> The original write to sdram_config is correct for DDR3 but incorrect
> for DDR2 so SPL was hanging. For DDR2, the write to sdram_config
> should be after the writes to ref_ctrl. This was working for DDR3
> because there was a write of 0x2800 to ref_ctrl before a write
> to sdram_config.
>
> Tested on: GP EVM 1.1A (DDR2), GP EVM 1.5A (DDR3),
> Beaglebone A6 (DDR2), Beagleone Blacd A4A (DDR3)
>
> Signed-off-by: Steve Kipisz <s-kipisz2@ti.com>
Applied to u-boot-ti/master (and already pulled into u-boot-arm),
thanks!
--
Tom
^ permalink raw reply [flat|nested] 2+ messages in thread
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