From: York Sun <yorksun@freescale.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 11/23] powerpc/t4240qds: Update DDR timing table
Date: Fri, 22 Mar 2013 10:15:19 -0700 [thread overview]
Message-ID: <1363972531-25641-11-git-send-email-yorksun@freescale.com> (raw)
In-Reply-To: <1363972531-25641-1-git-send-email-yorksun@freescale.com>
Update the timing table to support more rank density, based on the theory
that similar density DIMMs have similar clock adjust and write level start
timing. Update the timing for 1600 and 1866 MT/s. Tested with Micron
MT18JSF1G72AZ-1G9E1 DIMMs, iDIMM M3CN-4GMJ3C0C-M92.
Signed-off-by: York Sun <yorksun@freescale.com>
---
board/freescale/t4qds/ddr.c | 56 ++++++++++++++++++++++++++-----------------
1 file changed, 34 insertions(+), 22 deletions(-)
diff --git a/board/freescale/t4qds/ddr.c b/board/freescale/t4qds/ddr.c
index 692616a..90b6490 100644
--- a/board/freescale/t4qds/ddr.c
+++ b/board/freescale/t4qds/ddr.c
@@ -19,6 +19,7 @@ DECLARE_GLOBAL_DATA_PTR;
struct board_specific_parameters {
u32 n_ranks;
u32 datarate_mhz_high;
+ u32 rank_gb;
u32 clk_adjust;
u32 wrlvl_start;
u32 wrlvl_ctl_2;
@@ -36,16 +37,19 @@ struct board_specific_parameters {
static const struct board_specific_parameters udimm0[] = {
/*
* memory controller 0
- * num| hi| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T
- * ranks| mhz|adjst| start | ctl2 | ctl3 | |delay |
+ * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T
+ * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay |
*/
- {2, 1350, 5, 7, 0x0809090b, 0x0c0c0d09, 0xff, 2, 0},
- {2, 1666, 5, 8, 0x080a0a0c, 0x0c0d0e0a, 0xff, 2, 0},
- {2, 2140, 5, 8, 0x090a0b0c, 0x0e0f100b, 0xff, 2, 0},
- {1, 1350, 5, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0},
- {1, 1700, 5, 8, 0x080a0a0c, 0x0c0d0e0a, 0xff, 2, 0},
- {1, 1900, 4, 8, 0x080a0a0c, 0x0e0e0f0a, 0xff, 2, 0},
- {1, 2140, 4, 8, 0x090a0b0c, 0x0e0f100b, 0xff, 2, 0},
+ {2, 1350, 4, 4, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0},
+ {2, 1350, 0, 5, 7, 0x0709090b, 0x0c0c0d09, 0xff, 2, 0},
+ {2, 1666, 4, 4, 8, 0x080a0a0d, 0x0d10100b, 0xff, 2, 0},
+ {2, 1666, 0, 5, 7, 0x080a0a0c, 0x0d0d0e0a, 0xff, 2, 0},
+ {2, 1900, 0, 4, 8, 0x090a0b0e, 0x0f11120c, 0xff, 2, 0},
+ {2, 2140, 0, 4, 8, 0x090a0b0e, 0x0f11120c, 0xff, 2, 0},
+ {1, 1350, 0, 5, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0},
+ {1, 1700, 0, 5, 8, 0x080a0a0c, 0x0c0d0e0a, 0xff, 2, 0},
+ {1, 1900, 0, 4, 8, 0x080a0a0c, 0x0e0e0f0a, 0xff, 2, 0},
+ {1, 2140, 0, 4, 8, 0x090a0b0c, 0x0e0f100b, 0xff, 2, 0},
{}
};
@@ -61,19 +65,19 @@ static const struct board_specific_parameters *udimms[] = {
static const struct board_specific_parameters rdimm0[] = {
/*
* memory controller 0
- * num| hi| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T
- * ranks| mhz|adjst| start | ctl2 | ctl3 | |delay |
+ * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T
+ * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay |
*/
- {4, 1350, 5, 9, 0x08070605, 0x07080805, 0xff, 2, 0},
- {4, 1666, 5, 8, 0x08070605, 0x07080805, 0xff, 2, 0},
- {4, 2140, 5, 8, 0x08070605, 0x07081805, 0xff, 2, 0},
- {2, 1350, 5, 7, 0x0809090b, 0x0c0c0d09, 0xff, 2, 0},
- {2, 1666, 5, 8, 0x080a0a0c, 0x0c0d0e0a, 0xff, 2, 0},
- {2, 2140, 5, 8, 0x090a0b0c, 0x0e0f100b, 0xff, 2, 0},
- {1, 1350, 5, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0},
- {1, 1700, 5, 8, 0x080a0a0c, 0x0c0d0e0a, 0xff, 2, 0},
- {1, 1900, 4, 8, 0x080a0a0c, 0x0e0e0f0a, 0xff, 2, 0},
- {1, 2140, 4, 8, 0x090a0b0c, 0x0e0f100b, 0xff, 2, 0},
+ {4, 1350, 0, 5, 9, 0x08070605, 0x07080805, 0xff, 2, 0},
+ {4, 1666, 0, 5, 8, 0x08070605, 0x07080805, 0xff, 2, 0},
+ {4, 2140, 0, 5, 8, 0x08070605, 0x07081805, 0xff, 2, 0},
+ {2, 1350, 0, 5, 7, 0x0809090b, 0x0c0c0d09, 0xff, 2, 0},
+ {2, 1666, 0, 5, 8, 0x080a0a0c, 0x0c0d0e0a, 0xff, 2, 0},
+ {2, 2140, 0, 5, 8, 0x090a0b0c, 0x0e0f100b, 0xff, 2, 0},
+ {1, 1350, 0, 5, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0},
+ {1, 1700, 0, 5, 8, 0x080a0a0c, 0x0c0d0e0a, 0xff, 2, 0},
+ {1, 1900, 0, 4, 8, 0x080a0a0c, 0x0e0e0f0a, 0xff, 2, 0},
+ {1, 2140, 0, 4, 8, 0x090a0b0c, 0x0e0f100b, 0xff, 2, 0},
{}
};
@@ -113,7 +117,8 @@ void fsl_ddr_board_options(memctl_options_t *popts,
*/
ddr_freq = get_ddr_freq(0) / 1000000;
while (pbsp->datarate_mhz_high) {
- if (pbsp->n_ranks == pdimm->n_ranks) {
+ if (pbsp->n_ranks == pdimm->n_ranks &&
+ (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
if (ddr_freq <= pbsp->datarate_mhz_high) {
popts->cpo_override = pbsp->cpo;
popts->write_data_delay =
@@ -146,6 +151,13 @@ void fsl_ddr_board_options(memctl_options_t *popts,
panic("DIMM is not supported by this board");
}
found:
+ debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
+ "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, "
+ "wrlvl_ctrl_3 0x%x\n",
+ pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
+ pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
+ pbsp->wrlvl_ctl_3);
+
/*
* Factors to consider for half-strength driver enable:
* - number of DIMMs installed
--
1.7.9.5
next prev parent reply other threads:[~2013-03-22 17:15 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-03-22 17:15 [U-Boot] [PATCH 01/23] B4860: Corrected FMAN1 operating frequency print at u-boot York Sun
2013-03-22 17:15 ` [U-Boot] [PATCH 02/23] Add definitions for HDBCR registers York Sun
2013-03-22 17:15 ` [U-Boot] [PATCH 03/23] powerpc/pcie: add PCIe version 3.x support York Sun
2013-03-22 17:15 ` [U-Boot] [PATCH 04/23] powerpc/mpc85xx: Update corenet global utility block registers York Sun
2013-03-22 17:15 ` [U-Boot] [PATCH 05/23] powerpc/t4240qds: Fix SPI flash type York Sun
2013-03-22 17:15 ` [U-Boot] [PATCH 06/23] e6500: Move L1 enablement after L2 enablement York Sun
2013-03-22 17:15 ` [U-Boot] [PATCH 07/23] T4/serdes: fix the serdes clock frequency display York Sun
2013-03-22 17:15 ` [U-Boot] [PATCH 08/23] powerpc/t4240qds: fix XAUI card PHY address York Sun
2013-03-22 17:15 ` [U-Boot] [PATCH 09/23] Fman/t4240: some fix for 10G XAUI York Sun
2013-03-22 20:48 ` Wolfgang Denk
2013-03-22 17:15 ` [U-Boot] [PATCH 10/23] T4/SerDes: correct the SATA index York Sun
2013-03-22 20:49 ` Wolfgang Denk
2013-03-22 17:15 ` York Sun [this message]
2013-03-22 20:50 ` [U-Boot] [PATCH 11/23] powerpc/t4240qds: Update DDR timing table Wolfgang Denk
2013-03-22 17:15 ` [U-Boot] [PATCH 12/23] powerpc/mpc8xxx: Fix DDR 3-way interleaving York Sun
2013-03-22 17:15 ` [U-Boot] [PATCH 13/23] powerpc/mpc85xx: Fix portal setup York Sun
2013-03-22 17:15 ` [U-Boot] [PATCH 14/23] powerpc/t4240qds: Add voltage ID support York Sun
2013-03-22 20:50 ` Wolfgang Denk
2013-03-22 17:15 ` [U-Boot] [PATCH 15/23] T4/USB: Add USB 2.0 UTMI dual phy support York Sun
2013-03-22 20:51 ` Wolfgang Denk
2013-03-22 17:15 ` [U-Boot] [PATCH 16/23] T4/serdes: fix the actual serdes clock frequency York Sun
2013-03-22 17:15 ` [U-Boot] [PATCH 17/23] powerpc/85xx: add missing QMAN frequency calculation York Sun
2013-03-22 17:15 ` [U-Boot] [PATCH 18/23] powerpc/corenet2: Print SerDes protocol in decimal York Sun
2013-03-22 17:15 ` [U-Boot] [PATCH 19/23] powerpc/mpc85xx: Fix PIR parsing for chassis2 York Sun
2013-03-22 17:15 ` [U-Boot] [PATCH 20/23] powerpc/t4240: Fix SerDes protocol arrays with const prefix York Sun
2013-03-22 17:15 ` [U-Boot] [PATCH 21/23] powerpc/mpc85xx: Add T4160 SoC York Sun
2013-03-22 17:15 ` [U-Boot] [PATCH 22/23] powerpc/t4240qds: Move SoC define into boards.cfg York Sun
2013-03-22 17:15 ` [U-Boot] [PATCH 23/23] powerpc: Add T4160QDS York Sun
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