From mboxrd@z Thu Jan 1 00:00:00 1970 From: York Sun Date: Fri, 22 Mar 2013 10:15:24 -0700 Subject: [U-Boot] [PATCH 16/23] T4/serdes: fix the actual serdes clock frequency In-Reply-To: <1363972531-25641-1-git-send-email-yorksun@freescale.com> References: <1363972531-25641-1-git-send-email-yorksun@freescale.com> Message-ID: <1363972531-25641-16-git-send-email-yorksun@freescale.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de From: Roy Zang The correct bit maps in BRDCFG2 are 0 1 2 3 4 5 6 7 S1RATE[1:0] S2RATE[1:0] S3RATE[1:0] S4RATE[1:0] Signed-off-by: Roy Zang --- board/freescale/t4qds/t4qds.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/freescale/t4qds/t4qds.c b/board/freescale/t4qds/t4qds.c index 78322df..acce13c 100644 --- a/board/freescale/t4qds/t4qds.c +++ b/board/freescale/t4qds/t4qds.c @@ -587,7 +587,7 @@ int misc_init_r(void) sw = QIXIS_READ(brdcfg[2]); for (i = 0; i < MAX_SERDES; i++) { - unsigned int clock = (sw >> (2 * i)) & 3; + unsigned int clock = (sw >> (6 - 2 * i)) & 3; switch (clock) { case 0: actual[i] = SRDS_PLLCR0_RFCK_SEL_100; -- 1.7.9.5