From: York Sun <yorksun@freescale.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 19/23] powerpc/mpc85xx: Fix PIR parsing for chassis2
Date: Fri, 22 Mar 2013 10:15:27 -0700 [thread overview]
Message-ID: <1363972531-25641-19-git-send-email-yorksun@freescale.com> (raw)
In-Reply-To: <1363972531-25641-1-git-send-email-yorksun@freescale.com>
The PIR parsing algorithm we used is not only for E6500. It applies to all
SoCs with chassis 2.
Signed-off-by: York Sun <yorksun@freescale.com>
---
arch/powerpc/cpu/mpc85xx/release.S | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/release.S b/arch/powerpc/cpu/mpc85xx/release.S
index 0dea871..467ea10 100644
--- a/arch/powerpc/cpu/mpc85xx/release.S
+++ b/arch/powerpc/cpu/mpc85xx/release.S
@@ -159,9 +159,9 @@ __secondary_start_page:
* we cannot access it yet before setting up a new TLB
*/
mfspr r0,SPRN_PIR
-#if defined(CONFIG_E6500)
+#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
/*
- * PIR definition for E6500
+ * PIR definition for Chassis 2
* 0-17 Reserved (logic 0s)
* 8-19 CHIP_ID, 2'b00 - SoC 1
* all others - reserved
@@ -187,7 +187,7 @@ __secondary_start_page:
slwi r8,r4,6 /* spin table is padded to 64 byte */
add r10,r3,r8
-#ifdef CONFIG_E6500
+#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
mfspr r0,SPRN_PIR
/*
* core 0 thread 0: pir reset value 0x00, new pir 0
--
1.7.9.5
next prev parent reply other threads:[~2013-03-22 17:15 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-03-22 17:15 [U-Boot] [PATCH 01/23] B4860: Corrected FMAN1 operating frequency print at u-boot York Sun
2013-03-22 17:15 ` [U-Boot] [PATCH 02/23] Add definitions for HDBCR registers York Sun
2013-03-22 17:15 ` [U-Boot] [PATCH 03/23] powerpc/pcie: add PCIe version 3.x support York Sun
2013-03-22 17:15 ` [U-Boot] [PATCH 04/23] powerpc/mpc85xx: Update corenet global utility block registers York Sun
2013-03-22 17:15 ` [U-Boot] [PATCH 05/23] powerpc/t4240qds: Fix SPI flash type York Sun
2013-03-22 17:15 ` [U-Boot] [PATCH 06/23] e6500: Move L1 enablement after L2 enablement York Sun
2013-03-22 17:15 ` [U-Boot] [PATCH 07/23] T4/serdes: fix the serdes clock frequency display York Sun
2013-03-22 17:15 ` [U-Boot] [PATCH 08/23] powerpc/t4240qds: fix XAUI card PHY address York Sun
2013-03-22 17:15 ` [U-Boot] [PATCH 09/23] Fman/t4240: some fix for 10G XAUI York Sun
2013-03-22 20:48 ` Wolfgang Denk
2013-03-22 17:15 ` [U-Boot] [PATCH 10/23] T4/SerDes: correct the SATA index York Sun
2013-03-22 20:49 ` Wolfgang Denk
2013-03-22 17:15 ` [U-Boot] [PATCH 11/23] powerpc/t4240qds: Update DDR timing table York Sun
2013-03-22 20:50 ` Wolfgang Denk
2013-03-22 17:15 ` [U-Boot] [PATCH 12/23] powerpc/mpc8xxx: Fix DDR 3-way interleaving York Sun
2013-03-22 17:15 ` [U-Boot] [PATCH 13/23] powerpc/mpc85xx: Fix portal setup York Sun
2013-03-22 17:15 ` [U-Boot] [PATCH 14/23] powerpc/t4240qds: Add voltage ID support York Sun
2013-03-22 20:50 ` Wolfgang Denk
2013-03-22 17:15 ` [U-Boot] [PATCH 15/23] T4/USB: Add USB 2.0 UTMI dual phy support York Sun
2013-03-22 20:51 ` Wolfgang Denk
2013-03-22 17:15 ` [U-Boot] [PATCH 16/23] T4/serdes: fix the actual serdes clock frequency York Sun
2013-03-22 17:15 ` [U-Boot] [PATCH 17/23] powerpc/85xx: add missing QMAN frequency calculation York Sun
2013-03-22 17:15 ` [U-Boot] [PATCH 18/23] powerpc/corenet2: Print SerDes protocol in decimal York Sun
2013-03-22 17:15 ` York Sun [this message]
2013-03-22 17:15 ` [U-Boot] [PATCH 20/23] powerpc/t4240: Fix SerDes protocol arrays with const prefix York Sun
2013-03-22 17:15 ` [U-Boot] [PATCH 21/23] powerpc/mpc85xx: Add T4160 SoC York Sun
2013-03-22 17:15 ` [U-Boot] [PATCH 22/23] powerpc/t4240qds: Move SoC define into boards.cfg York Sun
2013-03-22 17:15 ` [U-Boot] [PATCH 23/23] powerpc: Add T4160QDS York Sun
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