[U-Boot] [PATCH 06/23] e6500: Move L1 enablement after L2 enablement

public inbox for u-boot@lists.denx.de
 help / color / mirror / Atom feed

From: York Sun <yorksun@freescale.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 06/23] e6500: Move L1 enablement after L2 enablement
Date: Fri, 22 Mar 2013 10:15:14 -0700	[thread overview]
Message-ID: <1363972531-25641-6-git-send-email-yorksun@freescale.com> (raw)
In-Reply-To: <1363972531-25641-1-git-send-email-yorksun@freescale.com>

From: Andy Fleming <afleming@freescale.com>

The L1 D-cache on e6500 is write-through. This means that it's not
considered a good idea to have the L1 up and running if the L2 is
disabled. We don't actually *use* the L1 until after the L2 is
brought up on e6500, so go ahead and move the L1 enablement after
that code is done.

Signed-off-by: Andy Fleming <afleming@freescale.com>
---
 arch/powerpc/cpu/mpc85xx/start.S |   94 +++++++++++++++++++-------------------
 1 file changed, 47 insertions(+), 47 deletions(-)

diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index 2ce5505..5542d0a 100644
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -173,52 +173,6 @@ l2_disabled:
 	mfspr	r1,DBSR
 	mtspr	DBSR,r1		/* Clear all valid bits */
 
-	/*
-	 *	Enable L1 Caches early
-	 *
-	 */
-
-#ifdef CONFIG_SYS_CACHE_STASHING
-	/* set stash id to (coreID) * 2 + 32 + L1 CT (0) */
-	li	r2,(32 + 0)
-	mtspr	L1CSR2,r2
-#endif
-
-	/* Enable/invalidate the I-Cache */
-	lis	r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@h
-	ori	r2,r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@l
-	mtspr	SPRN_L1CSR1,r2
-1:
-	mfspr	r3,SPRN_L1CSR1
-	and.	r1,r3,r2
-	bne	1b
-
-	lis	r3,(L1CSR1_CPE|L1CSR1_ICE)@h
-	ori	r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l
-	mtspr	SPRN_L1CSR1,r3
-	isync
-2:
-	mfspr	r3,SPRN_L1CSR1
-	andi.	r1,r3,L1CSR1_ICE at l
-	beq	2b
-
-	/* Enable/invalidate the D-Cache */
-	lis	r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@h
-	ori	r2,r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@l
-	mtspr	SPRN_L1CSR0,r2
-1:
-	mfspr	r3,SPRN_L1CSR0
-	and.	r1,r3,r2
-	bne	1b
-
-	lis	r3,(L1CSR0_CPE|L1CSR0_DCE)@h
-	ori	r3,r3,(L1CSR0_CPE|L1CSR0_DCE)@l
-	mtspr	SPRN_L1CSR0,r3
-	isync
-2:
-	mfspr	r3,SPRN_L1CSR0
-	andi.	r1,r3,L1CSR0_DCE at l
-	beq	2b
 
 	.macro	create_tlb1_entry esel ts tsize epn wimg rpn perm phy_high scratch
 	lis	\scratch, FSL_BOOKE_MAS0(1, \esel, 0)@h
@@ -782,11 +736,57 @@ enable_l2_cluster_l2:
 	bne	1b
 	lis	r4, L2CSR0_L2E at h
 	sync
-	stw	r4, 0(r3)	/* eanble L2 */
+	stw	r4, 0(r3)	/* enable L2 */
 delete_ccsr_l2_tlb:
 	delete_tlb0_entry 0, CONFIG_SYS_CCSRBAR + 0xC20000, MAS2_I|MAS2_G, r3
 #endif
 
+	/*
+	 * Enable the L1. On e6500, this has to be done
+	 * after the L2 is up.
+	 */
+
+#ifdef CONFIG_SYS_CACHE_STASHING
+	/* set stash id to (coreID) * 2 + 32 + L1 CT (0) */
+	li	r2,(32 + 0)
+	mtspr	L1CSR2,r2
+#endif
+
+	/* Enable/invalidate the I-Cache */
+	lis	r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@h
+	ori	r2,r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@l
+	mtspr	SPRN_L1CSR1,r2
+1:
+	mfspr	r3,SPRN_L1CSR1
+	and.	r1,r3,r2
+	bne	1b
+
+	lis	r3,(L1CSR1_CPE|L1CSR1_ICE)@h
+	ori	r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l
+	mtspr	SPRN_L1CSR1,r3
+	isync
+2:
+	mfspr	r3,SPRN_L1CSR1
+	andi.	r1,r3,L1CSR1_ICE at l
+	beq	2b
+
+	/* Enable/invalidate the D-Cache */
+	lis	r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@h
+	ori	r2,r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@l
+	mtspr	SPRN_L1CSR0,r2
+1:
+	mfspr	r3,SPRN_L1CSR0
+	and.	r1,r3,r2
+	bne	1b
+
+	lis	r3,(L1CSR0_CPE|L1CSR0_DCE)@h
+	ori	r3,r3,(L1CSR0_CPE|L1CSR0_DCE)@l
+	mtspr	SPRN_L1CSR0,r3
+	isync
+2:
+	mfspr	r3,SPRN_L1CSR0
+	andi.	r1,r3,L1CSR0_DCE at l
+	beq	2b
 #ifdef CONFIG_SYS_FSL_ERRATUM_A004510
 #define DCSR_LAWBARH0	(CONFIG_SYS_CCSRBAR + 0x1000)
 #define LAW_SIZE_1M	0x13
-- 
1.7.9.5

next prev parent reply	other threads:[~2013-03-22 17:15 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2013-03-22 17:15 [U-Boot] [PATCH 01/23] B4860: Corrected FMAN1 operating frequency print at u-boot York Sun
2013-03-22 17:15 ` [U-Boot] [PATCH 02/23] Add definitions for HDBCR registers York Sun
2013-03-22 17:15 ` [U-Boot] [PATCH 03/23] powerpc/pcie: add PCIe version 3.x support York Sun
2013-03-22 17:15 ` [U-Boot] [PATCH 04/23] powerpc/mpc85xx: Update corenet global utility block registers York Sun
2013-03-22 17:15 ` [U-Boot] [PATCH 05/23] powerpc/t4240qds: Fix SPI flash type York Sun
2013-03-22 17:15 ` York Sun [this message]
2013-03-22 17:15 ` [U-Boot] [PATCH 07/23] T4/serdes: fix the serdes clock frequency display York Sun
2013-03-22 17:15 ` [U-Boot] [PATCH 08/23] powerpc/t4240qds: fix XAUI card PHY address York Sun
2013-03-22 17:15 ` [U-Boot] [PATCH 09/23] Fman/t4240: some fix for 10G XAUI York Sun
2013-03-22 20:48   ` Wolfgang Denk
2013-03-22 17:15 ` [U-Boot] [PATCH 10/23] T4/SerDes: correct the SATA index York Sun
2013-03-22 20:49   ` Wolfgang Denk
2013-03-22 17:15 ` [U-Boot] [PATCH 11/23] powerpc/t4240qds: Update DDR timing table York Sun
2013-03-22 20:50   ` Wolfgang Denk
2013-03-22 17:15 ` [U-Boot] [PATCH 12/23] powerpc/mpc8xxx: Fix DDR 3-way interleaving York Sun
2013-03-22 17:15 ` [U-Boot] [PATCH 13/23] powerpc/mpc85xx: Fix portal setup York Sun
2013-03-22 17:15 ` [U-Boot] [PATCH 14/23] powerpc/t4240qds: Add voltage ID support York Sun
2013-03-22 20:50   ` Wolfgang Denk
2013-03-22 17:15 ` [U-Boot] [PATCH 15/23] T4/USB: Add USB 2.0 UTMI dual phy support York Sun
2013-03-22 20:51   ` Wolfgang Denk
2013-03-22 17:15 ` [U-Boot] [PATCH 16/23] T4/serdes: fix the actual serdes clock frequency York Sun
2013-03-22 17:15 ` [U-Boot] [PATCH 17/23] powerpc/85xx: add missing QMAN frequency calculation York Sun
2013-03-22 17:15 ` [U-Boot] [PATCH 18/23] powerpc/corenet2: Print SerDes protocol in decimal York Sun
2013-03-22 17:15 ` [U-Boot] [PATCH 19/23] powerpc/mpc85xx: Fix PIR parsing for chassis2 York Sun
2013-03-22 17:15 ` [U-Boot] [PATCH 20/23] powerpc/t4240: Fix SerDes protocol arrays with const prefix York Sun
2013-03-22 17:15 ` [U-Boot] [PATCH 21/23] powerpc/mpc85xx: Add T4160 SoC York Sun
2013-03-22 17:15 ` [U-Boot] [PATCH 22/23] powerpc/t4240qds: Move SoC define into boards.cfg York Sun
2013-03-22 17:15 ` [U-Boot] [PATCH 23/23] powerpc: Add T4160QDS York Sun

find likely ancestor, descendant, or conflicting patches for this message:
( dfblob:2ce5505 dfblob:5542d0a )
 OR (
bs:"[U-Boot] [PATCH 06/23] e6500: Move L1 enablement after L2 enablement" )
	(help)

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=1363972531-25641-6-git-send-email-yorksun@freescale.com \
    --to=yorksun@freescale.com \
    --cc=u-boot@lists.denx.de \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link

Be sure your reply has a Subject: header at the top and a blank line before the message body.

This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox