From: York Sun <yorksun@freescale.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 03/21] fsl_ifc: add support for different IFC bank count
Date: Fri, 22 Mar 2013 10:23:54 -0700 [thread overview]
Message-ID: <1363973052-25918-1-git-send-email-yorksun@freescale.com> (raw)
From: Mingkai Hu <Mingkai.hu@freescale.com>
Calculate reserved fields according to IFC bank count
1. Move csor_ext register behind csor register and fix res offset
2. move ifc bank count to config_mpc85xx.h to support 8 bank count
There's no IFC controller instead of eLBC controller on some platforms,
such as MPC8536, P2041, P3041, P4080 etc, so there's no macro definition
for the number of IFC chip select(CONFIG_SYS_FSL_IFC_BANK_COUNT) which
is used in the IFC controller header file fsl_ifc.h on these platforms.
Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
---
arch/powerpc/cpu/mpc85xx/cpu.c | 2 +-
arch/powerpc/cpu/mpc8xxx/fsl_ifc.c | 58 ++++++++++++++++++++++++++++-
arch/powerpc/include/asm/config_mpc85xx.h | 7 ++++
arch/powerpc/include/asm/fsl_ifc.h | 42 +++++++++++++++------
4 files changed, 96 insertions(+), 13 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index df2ab6d..379a7df 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -34,8 +34,8 @@
#include <asm/io.h>
#include <asm/mmu.h>
#include <asm/fsl_ifc.h>
-#include <asm/fsl_law.h>
#include <asm/fsl_lbc.h>
+#include <asm/fsl_law.h>
#include <post.h>
#include <asm/processor.h>
#include <asm/fsl_ddr_sdram.h>
diff --git a/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c b/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c
index 56b319f..f0da355 100644
--- a/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c
+++ b/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c
@@ -26,7 +26,7 @@ void print_ifc_regs(void)
int i, j;
printf("IFC Controller Registers\n");
- for (i = 0; i < FSL_IFC_BANK_COUNT; i++) {
+ for (i = 0; i < CONFIG_SYS_FSL_IFC_BANK_COUNT; i++) {
printf("CSPR%d:0x%08X\tAMASK%d:0x%08X\tCSOR%d:0x%08X\n",
i, get_ifc_cspr(i), i, get_ifc_amask(i),
i, get_ifc_csor(i));
@@ -94,4 +94,60 @@ void init_early_memctl_regs(void)
set_ifc_amask(IFC_CS3, CONFIG_SYS_AMASK3);
set_ifc_csor(IFC_CS3, CONFIG_SYS_CSOR3);
#endif
+
+#ifdef CONFIG_SYS_CSPR4_EXT
+ set_ifc_cspr_ext(IFC_CS4, CONFIG_SYS_CSPR4_EXT);
+#endif
+#if defined(CONFIG_SYS_CSPR4) && defined(CONFIG_SYS_CSOR4)
+ set_ifc_ftim(IFC_CS4, IFC_FTIM0, CONFIG_SYS_CS4_FTIM0);
+ set_ifc_ftim(IFC_CS4, IFC_FTIM1, CONFIG_SYS_CS4_FTIM1);
+ set_ifc_ftim(IFC_CS4, IFC_FTIM2, CONFIG_SYS_CS4_FTIM2);
+ set_ifc_ftim(IFC_CS4, IFC_FTIM3, CONFIG_SYS_CS4_FTIM3);
+
+ set_ifc_cspr(IFC_CS4, CONFIG_SYS_CSPR4);
+ set_ifc_amask(IFC_CS4, CONFIG_SYS_AMASK4);
+ set_ifc_csor(IFC_CS4, CONFIG_SYS_CSOR4);
+#endif
+
+#ifdef CONFIG_SYS_CSPR5_EXT
+ set_ifc_cspr_ext(IFC_CS5, CONFIG_SYS_CSPR5_EXT);
+#endif
+#if defined(CONFIG_SYS_CSPR5) && defined(CONFIG_SYS_CSOR5)
+ set_ifc_ftim(IFC_CS5, IFC_FTIM0, CONFIG_SYS_CS5_FTIM0);
+ set_ifc_ftim(IFC_CS5, IFC_FTIM1, CONFIG_SYS_CS5_FTIM1);
+ set_ifc_ftim(IFC_CS5, IFC_FTIM2, CONFIG_SYS_CS5_FTIM2);
+ set_ifc_ftim(IFC_CS5, IFC_FTIM3, CONFIG_SYS_CS5_FTIM3);
+
+ set_ifc_cspr(IFC_CS5, CONFIG_SYS_CSPR5);
+ set_ifc_amask(IFC_CS5, CONFIG_SYS_AMASK5);
+ set_ifc_csor(IFC_CS5, CONFIG_SYS_CSOR5);
+#endif
+
+#ifdef CONFIG_SYS_CSPR6_EXT
+ set_ifc_cspr_ext(IFC_CS6, CONFIG_SYS_CSPR6_EXT);
+#endif
+#if defined(CONFIG_SYS_CSPR6) && defined(CONFIG_SYS_CSOR6)
+ set_ifc_ftim(IFC_CS6, IFC_FTIM0, CONFIG_SYS_CS6_FTIM0);
+ set_ifc_ftim(IFC_CS6, IFC_FTIM1, CONFIG_SYS_CS6_FTIM1);
+ set_ifc_ftim(IFC_CS6, IFC_FTIM2, CONFIG_SYS_CS6_FTIM2);
+ set_ifc_ftim(IFC_CS6, IFC_FTIM3, CONFIG_SYS_CS6_FTIM3);
+
+ set_ifc_cspr(IFC_CS6, CONFIG_SYS_CSPR6);
+ set_ifc_amask(IFC_CS6, CONFIG_SYS_AMASK6);
+ set_ifc_csor(IFC_CS6, CONFIG_SYS_CSOR6);
+#endif
+
+#ifdef CONFIG_SYS_CSPR7_EXT
+ set_ifc_cspr_ext(IFC_CS7, CONFIG_SYS_CSPR7_EXT);
+#endif
+#if defined(CONFIG_SYS_CSPR7) && defined(CONFIG_SYS_CSOR7)
+ set_ifc_ftim(IFC_CS7, IFC_FTIM0, CONFIG_SYS_CS7_FTIM0);
+ set_ifc_ftim(IFC_CS7, IFC_FTIM1, CONFIG_SYS_CS7_FTIM1);
+ set_ifc_ftim(IFC_CS7, IFC_FTIM2, CONFIG_SYS_CS7_FTIM2);
+ set_ifc_ftim(IFC_CS7, IFC_FTIM3, CONFIG_SYS_CS7_FTIM3);
+
+ set_ifc_cspr(IFC_CS7, CONFIG_SYS_CSPR7);
+ set_ifc_amask(IFC_CS7, CONFIG_SYS_AMASK7);
+ set_ifc_csor(IFC_CS7, CONFIG_SYS_CSOR7);
+#endif
}
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index 5def364..7a1cdc7 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -139,6 +139,7 @@
#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_NUM_DDR_CONTROLLERS 1
+#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
@@ -491,6 +492,7 @@
#define CONFIG_TSECV2
#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_NUM_DDR_CONTROLLERS 1
+#define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#define CONFIG_NAND_FSL_IFC
#define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
@@ -504,6 +506,7 @@
#define CONFIG_TSECV2
#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_NUM_DDR_CONTROLLERS 2
+#define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#define CONFIG_NAND_FSL_IFC
#define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
@@ -529,6 +532,7 @@
#define CONFIG_SYS_NUM_FM2_10GEC 2
#define CONFIG_NUM_DDR_CONTROLLERS 3
#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
+#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
#define CONFIG_SYS_FMAN_V3
#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
#define CONFIG_SYS_FSL_TBCLK_DIV 16
@@ -562,6 +566,7 @@
#define CONFIG_SYS_NUM_FM2_10GEC 1
#define CONFIG_NUM_DDR_CONTROLLERS 2
#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
+#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
#define CONFIG_SYS_FMAN_V3
#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
#define CONFIG_SYS_FSL_TBCLK_DIV 16
@@ -590,6 +595,7 @@
#define CONFIG_SYS_NUM_FM1_DTSEC 4
#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
+#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
#define CONFIG_SYS_FMAN_V3
#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
#define CONFIG_SYS_FSL_TBCLK_DIV 16
@@ -612,6 +618,7 @@
#define CONFIG_SYS_NUM_FM1_10GEC 2
#define CONFIG_NUM_DDR_CONTROLLERS 2
#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
+#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
#define CONFIG_SYS_FMAN_V3
#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
#define CONFIG_SYS_FSL_TBCLK_DIV 16
diff --git a/arch/powerpc/include/asm/fsl_ifc.h b/arch/powerpc/include/asm/fsl_ifc.h
index ba41b73..debcb6b 100644
--- a/arch/powerpc/include/asm/fsl_ifc.h
+++ b/arch/powerpc/include/asm/fsl_ifc.h
@@ -21,6 +21,7 @@
#ifndef __ASM_PPC_FSL_IFC_H
#define __ASM_PPC_FSL_IFC_H
+#ifdef CONFIG_FSL_IFC
#include <config.h>
#include <common.h>
@@ -798,13 +799,15 @@ extern void init_early_memctl_regs(void);
#define set_ifc_ftim(i, j, v) \
(out_be32(&(IFC_BASE_ADDR)->ftim_cs[i].ftim[j], v))
-#define FSL_IFC_BANK_COUNT 4
-
enum ifc_chip_sel {
IFC_CS0,
IFC_CS1,
IFC_CS2,
IFC_CS3,
+ IFC_CS4,
+ IFC_CS5,
+ IFC_CS6,
+ IFC_CS7,
};
enum ifc_ftims {
@@ -907,6 +910,22 @@ struct fsl_ifc_gpcm {
u32 res4[0x1F3];
};
+#ifdef CONFIG_SYS_FSL_IFC_BANK_COUNT
+#if (CONFIG_SYS_FSL_IFC_BANK_COUNT <= 8)
+#define CONFIG_SYS_FSL_IFC_CSPR_RES \
+ (0x25 - CONFIG_SYS_FSL_IFC_BANK_COUNT * 3)
+#define CONFIG_SYS_FSL_IFC_AMASK_RES \
+ (0x24 - CONFIG_SYS_FSL_IFC_BANK_COUNT * 3)
+#define CONFIG_SYS_FSL_IFC_CSOR_RES \
+ (0x24 - CONFIG_SYS_FSL_IFC_BANK_COUNT * 3)
+#define CONFIG_SYS_FSL_IFC_FTIM_RES \
+ (0x90 - CONFIG_SYS_FSL_IFC_BANK_COUNT * 0xc)
+#else
+#error IFC BANK count not vaild
+#endif
+#else
+#error IFC BANK count not defined
+#endif
/*
* IFC Controller Registers
@@ -918,24 +937,24 @@ struct fsl_ifc {
u32 cspr_ext;
u32 cspr;
u32 res2;
- } cspr_cs[FSL_IFC_BANK_COUNT];
- u32 res3[0x19];
+ } cspr_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT];
+ u32 res3[CONFIG_SYS_FSL_IFC_CSPR_RES];
struct {
u32 amask;
u32 res4[0x2];
- } amask_cs[FSL_IFC_BANK_COUNT];
- u32 res5[0x17];
+ } amask_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT];
+ u32 res5[CONFIG_SYS_FSL_IFC_AMASK_RES];
struct {
- u32 csor_ext;
u32 csor;
+ u32 csor_ext;
u32 res6;
- } csor_cs[FSL_IFC_BANK_COUNT];
- u32 res7[0x19];
+ } csor_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT];
+ u32 res7[CONFIG_SYS_FSL_IFC_CSOR_RES];
struct {
u32 ftim[4];
u32 res8[0x8];
- } ftim_cs[FSL_IFC_BANK_COUNT];
- u32 res9[0x60];
+ } ftim_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT];
+ u32 res9[CONFIG_SYS_FSL_IFC_FTIM_RES];
u32 rb_stat;
u32 res10[0x2];
u32 ifc_gcr;
@@ -961,6 +980,7 @@ struct fsl_ifc {
#undef CSPR_MSEL_NOR
#define CSPR_MSEL_NOR CSPR_MSEL_GPCM
#endif
+#endif /* CONFIG_FSL_IFC */
#endif /* __ASSEMBLY__ */
#endif /* __ASM_PPC_FSL_IFC_H */
--
1.7.9.5
next reply other threads:[~2013-03-22 17:23 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-03-22 17:23 York Sun [this message]
2013-03-22 17:23 ` [U-Boot] [PATCH 04/21] powerpc/mpc85xx b8460 PCIe registers are not at QORIQ_CHASSIS2 location York Sun
2013-03-22 17:23 ` [U-Boot] [PATCH 05/21] powerpc/mpc85xx: Add setting of clock-frequency for T4/B4 clockgen node York Sun
2013-03-22 20:54 ` Wolfgang Denk
2013-03-22 17:23 ` [U-Boot] [PATCH 06/21] t4240qds/eth: fixup ethernet for t4240qds York Sun
2013-03-22 17:23 ` [U-Boot] [PATCH 07/21] net/fm: fixup ethernet for mEMAC York Sun
2013-03-22 20:55 ` Wolfgang Denk
2013-03-22 17:23 ` [U-Boot] [PATCH 08/21] powerpc/85xx: fix build error introduced by serdes_get_prtcl York Sun
2013-03-22 17:24 ` [U-Boot] [PATCH 09/21] net/phy: add VSC8574 support York Sun
2013-03-22 20:55 ` Wolfgang Denk
2013-03-22 17:24 ` [U-Boot] [PATCH 10/21] T4240/net: use QSGMII card PHY address by default York Sun
2013-03-22 17:24 ` [U-Boot] [PATCH 11/21] T4/usb: move usb 2.0 utmi dual phy init code to cpu_init.c York Sun
2013-03-22 17:24 ` [U-Boot] [PATCH 12/21] powerpc/mpc85xx: Update workaround for DDR erratum A-004934 York Sun
2013-03-22 17:24 ` [U-Boot] [PATCH 13/21] powerpc/mpc8xxx: Allow board file to override DDR address assignment York Sun
2013-03-22 17:24 ` [U-Boot] [PATCH 14/21] powerpc/b4860qds: Assign DDR address in board file York Sun
2013-03-22 20:57 ` Wolfgang Denk
2013-03-22 17:24 ` [U-Boot] [PATCH 15/21] powerpc/t4qds: Fix disabling remote I2C connection York Sun
2013-03-22 17:24 ` [U-Boot] [PATCH 16/21] T4240/eth: fix SGMII card PHY address York Sun
2013-03-22 20:57 ` Wolfgang Denk
2013-03-22 17:24 ` [U-Boot] [PATCH 17/21] powerpc/srio: Remove duplicate macro definitions York Sun
2013-03-22 17:24 ` [U-Boot] [PATCH 18/21] powerpc/boot: Change the macro of Boot from SRIO and PCIE master module York Sun
2013-03-22 17:24 ` [U-Boot] [PATCH 19/21] powerpc/b4860qds: Add the tlb entries for SRIO interfaces York Sun
2013-03-22 20:58 ` Wolfgang Denk
2013-03-22 17:24 ` [U-Boot] [PATCH 20/21] powerpc/b4860qds: Master module for boot from SRIO and PCIE York Sun
2013-03-22 17:24 ` [U-Boot] [PATCH 21/21] powerpc/b4860qds: Slave " York Sun
2013-03-22 20:58 ` Wolfgang Denk
2013-05-10 21:49 ` [U-Boot] [PATCH 03/21] fsl_ifc: add support for different IFC bank count Andy Fleming
2013-05-14 8:59 ` Hu Mingkai-B21284
2013-05-14 14:43 ` Fleming Andy-AFLEMING
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1363973052-25918-1-git-send-email-yorksun@freescale.com \
--to=yorksun@freescale.com \
--cc=u-boot@lists.denx.de \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox