From mboxrd@z Thu Jan 1 00:00:00 1970 From: York Sun Date: Fri, 22 Mar 2013 10:23:55 -0700 Subject: [U-Boot] [PATCH 04/21] powerpc/mpc85xx b8460 PCIe registers are not at QORIQ_CHASSIS2 location In-Reply-To: <1363973052-25918-1-git-send-email-yorksun@freescale.com> References: <1363973052-25918-1-git-send-email-yorksun@freescale.com> Message-ID: <1363973052-25918-2-git-send-email-yorksun@freescale.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de From: Ed Swarthout Even B4860 has chassis generation 2, but its PCIe registers are at the same location as other corenet SoCs. Signed-off-by: Ed Swarthout --- arch/powerpc/include/asm/immap_85xx.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 99b6bb3..c09c127 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -2954,7 +2954,7 @@ struct ccsr_pman { #define CONFIG_SYS_MPC85xx_IFC_OFFSET 0x124000 #define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0x130000 #define CONFIG_SYS_FSL_CORENET_RMAN_OFFSET 0x1e0000 -#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 +#if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && !defined(CONFIG_PPC_B4860) #define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0x240000 #define CONFIG_SYS_MPC85xx_PCIE2_OFFSET 0x250000 #define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0x260000 -- 1.7.9.5