[U-Boot] [PATCH 03/21] fsl_ifc: add support for different IFC bank count

[U-Boot] [PATCH 03/21] fsl_ifc: add support for different IFC bank count

[York Sun]

From: Mingkai Hu <Mingkai.hu@freescale.com>

Calculate reserved fields according to IFC bank count

1. Move csor_ext register behind csor register and fix res offset
2. move ifc bank count to config_mpc85xx.h to support 8 bank count

There's no IFC controller instead of eLBC controller on some platforms,
such as MPC8536, P2041, P3041, P4080 etc, so there's no macro definition
for the number of IFC chip select(CONFIG_SYS_FSL_IFC_BANK_COUNT) which
is used in the IFC controller header file fsl_ifc.h on these platforms.

Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
---
 arch/powerpc/cpu/mpc85xx/cpu.c            |    2 +-
 arch/powerpc/cpu/mpc8xxx/fsl_ifc.c        |   58 ++++++++++++++++++++++++++++-
 arch/powerpc/include/asm/config_mpc85xx.h |    7 ++++
 arch/powerpc/include/asm/fsl_ifc.h        |   42 +++++++++++++++------
 4 files changed, 96 insertions(+), 13 deletions(-)

diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index df2ab6d..379a7df 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -34,8 +34,8 @@
 #include <asm/io.h>
 #include <asm/mmu.h>
 #include <asm/fsl_ifc.h>
-#include <asm/fsl_law.h>
 #include <asm/fsl_lbc.h>
+#include <asm/fsl_law.h>
 #include <post.h>
 #include <asm/processor.h>
 #include <asm/fsl_ddr_sdram.h>
diff --git a/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c b/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c
index 56b319f..f0da355 100644
--- a/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c
+++ b/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c
@@ -26,7 +26,7 @@ void print_ifc_regs(void)
 	int i, j;
 
 	printf("IFC Controller Registers\n");
-	for (i = 0; i < FSL_IFC_BANK_COUNT; i++) {
+	for (i = 0; i < CONFIG_SYS_FSL_IFC_BANK_COUNT; i++) {
 		printf("CSPR%d:0x%08X\tAMASK%d:0x%08X\tCSOR%d:0x%08X\n",
 			i, get_ifc_cspr(i), i, get_ifc_amask(i),
 			i, get_ifc_csor(i));
@@ -94,4 +94,60 @@ void init_early_memctl_regs(void)
 	set_ifc_amask(IFC_CS3, CONFIG_SYS_AMASK3);
 	set_ifc_csor(IFC_CS3, CONFIG_SYS_CSOR3);
 #endif
+
+#ifdef CONFIG_SYS_CSPR4_EXT
+	set_ifc_cspr_ext(IFC_CS4, CONFIG_SYS_CSPR4_EXT);
+#endif
+#if defined(CONFIG_SYS_CSPR4) && defined(CONFIG_SYS_CSOR4)
+	set_ifc_ftim(IFC_CS4, IFC_FTIM0, CONFIG_SYS_CS4_FTIM0);
+	set_ifc_ftim(IFC_CS4, IFC_FTIM1, CONFIG_SYS_CS4_FTIM1);
+	set_ifc_ftim(IFC_CS4, IFC_FTIM2, CONFIG_SYS_CS4_FTIM2);
+	set_ifc_ftim(IFC_CS4, IFC_FTIM3, CONFIG_SYS_CS4_FTIM3);
+
+	set_ifc_cspr(IFC_CS4, CONFIG_SYS_CSPR4);
+	set_ifc_amask(IFC_CS4, CONFIG_SYS_AMASK4);
+	set_ifc_csor(IFC_CS4, CONFIG_SYS_CSOR4);
+#endif
+
+#ifdef CONFIG_SYS_CSPR5_EXT
+	set_ifc_cspr_ext(IFC_CS5, CONFIG_SYS_CSPR5_EXT);
+#endif
+#if defined(CONFIG_SYS_CSPR5) && defined(CONFIG_SYS_CSOR5)
+	set_ifc_ftim(IFC_CS5, IFC_FTIM0, CONFIG_SYS_CS5_FTIM0);
+	set_ifc_ftim(IFC_CS5, IFC_FTIM1, CONFIG_SYS_CS5_FTIM1);
+	set_ifc_ftim(IFC_CS5, IFC_FTIM2, CONFIG_SYS_CS5_FTIM2);
+	set_ifc_ftim(IFC_CS5, IFC_FTIM3, CONFIG_SYS_CS5_FTIM3);
+
+	set_ifc_cspr(IFC_CS5, CONFIG_SYS_CSPR5);
+	set_ifc_amask(IFC_CS5, CONFIG_SYS_AMASK5);
+	set_ifc_csor(IFC_CS5, CONFIG_SYS_CSOR5);
+#endif
+
+#ifdef CONFIG_SYS_CSPR6_EXT
+	set_ifc_cspr_ext(IFC_CS6, CONFIG_SYS_CSPR6_EXT);
+#endif
+#if defined(CONFIG_SYS_CSPR6) && defined(CONFIG_SYS_CSOR6)
+	set_ifc_ftim(IFC_CS6, IFC_FTIM0, CONFIG_SYS_CS6_FTIM0);
+	set_ifc_ftim(IFC_CS6, IFC_FTIM1, CONFIG_SYS_CS6_FTIM1);
+	set_ifc_ftim(IFC_CS6, IFC_FTIM2, CONFIG_SYS_CS6_FTIM2);
+	set_ifc_ftim(IFC_CS6, IFC_FTIM3, CONFIG_SYS_CS6_FTIM3);
+
+	set_ifc_cspr(IFC_CS6, CONFIG_SYS_CSPR6);
+	set_ifc_amask(IFC_CS6, CONFIG_SYS_AMASK6);
+	set_ifc_csor(IFC_CS6, CONFIG_SYS_CSOR6);
+#endif
+
+#ifdef CONFIG_SYS_CSPR7_EXT
+	set_ifc_cspr_ext(IFC_CS7, CONFIG_SYS_CSPR7_EXT);
+#endif
+#if defined(CONFIG_SYS_CSPR7) && defined(CONFIG_SYS_CSOR7)
+	set_ifc_ftim(IFC_CS7, IFC_FTIM0, CONFIG_SYS_CS7_FTIM0);
+	set_ifc_ftim(IFC_CS7, IFC_FTIM1, CONFIG_SYS_CS7_FTIM1);
+	set_ifc_ftim(IFC_CS7, IFC_FTIM2, CONFIG_SYS_CS7_FTIM2);
+	set_ifc_ftim(IFC_CS7, IFC_FTIM3, CONFIG_SYS_CS7_FTIM3);
+
+	set_ifc_cspr(IFC_CS7, CONFIG_SYS_CSPR7);
+	set_ifc_amask(IFC_CS7, CONFIG_SYS_AMASK7);
+	set_ifc_csor(IFC_CS7, CONFIG_SYS_CSOR7);
+#endif
 }
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index 5def364..7a1cdc7 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -139,6 +139,7 @@
 #define CONFIG_SYS_FSL_SEC_COMPAT	4
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 #define CONFIG_NUM_DDR_CONTROLLERS	1
+#define CONFIG_SYS_FSL_IFC_BANK_COUNT	4
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v2.2"
 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
@@ -491,6 +492,7 @@
 #define CONFIG_TSECV2
 #define CONFIG_SYS_FSL_SEC_COMPAT	4
 #define CONFIG_NUM_DDR_CONTROLLERS	1
+#define CONFIG_SYS_FSL_IFC_BANK_COUNT	3
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #define CONFIG_NAND_FSL_IFC
 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
@@ -504,6 +506,7 @@
 #define CONFIG_TSECV2
 #define CONFIG_SYS_FSL_SEC_COMPAT	4
 #define CONFIG_NUM_DDR_CONTROLLERS	2
+#define CONFIG_SYS_FSL_IFC_BANK_COUNT	3
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #define CONFIG_NAND_FSL_IFC
 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
@@ -529,6 +532,7 @@
 #define CONFIG_SYS_NUM_FM2_10GEC	2
 #define CONFIG_NUM_DDR_CONTROLLERS	3
 #define CONFIG_SYS_FSL_DDR_VER		FSL_DDR_VER_4_7
+#define CONFIG_SYS_FSL_IFC_BANK_COUNT	8
 #define CONFIG_SYS_FMAN_V3
 #define CONFIG_SYS_FM_MURAM_SIZE	0x60000
 #define CONFIG_SYS_FSL_TBCLK_DIV	16
@@ -562,6 +566,7 @@
 #define CONFIG_SYS_NUM_FM2_10GEC	1
 #define CONFIG_NUM_DDR_CONTROLLERS	2
 #define CONFIG_SYS_FSL_DDR_VER		FSL_DDR_VER_4_7
+#define CONFIG_SYS_FSL_IFC_BANK_COUNT	8
 #define CONFIG_SYS_FMAN_V3
 #define CONFIG_SYS_FM_MURAM_SIZE	0x60000
 #define CONFIG_SYS_FSL_TBCLK_DIV	16
@@ -590,6 +595,7 @@
 #define CONFIG_SYS_NUM_FM1_DTSEC	4
 #define CONFIG_NUM_DDR_CONTROLLERS	1
 #define CONFIG_SYS_FSL_DDR_VER		FSL_DDR_VER_4_7
+#define CONFIG_SYS_FSL_IFC_BANK_COUNT	4
 #define CONFIG_SYS_FMAN_V3
 #define CONFIG_SYS_FM_MURAM_SIZE	0x60000
 #define CONFIG_SYS_FSL_TBCLK_DIV	16
@@ -612,6 +618,7 @@
 #define CONFIG_SYS_NUM_FM1_10GEC	2
 #define CONFIG_NUM_DDR_CONTROLLERS	2
 #define CONFIG_SYS_FSL_DDR_VER		FSL_DDR_VER_4_7
+#define CONFIG_SYS_FSL_IFC_BANK_COUNT	4
 #define CONFIG_SYS_FMAN_V3
 #define CONFIG_SYS_FM_MURAM_SIZE	0x60000
 #define CONFIG_SYS_FSL_TBCLK_DIV	16
diff --git a/arch/powerpc/include/asm/fsl_ifc.h b/arch/powerpc/include/asm/fsl_ifc.h
index ba41b73..debcb6b 100644
--- a/arch/powerpc/include/asm/fsl_ifc.h
+++ b/arch/powerpc/include/asm/fsl_ifc.h
@@ -21,6 +21,7 @@
 #ifndef __ASM_PPC_FSL_IFC_H
 #define __ASM_PPC_FSL_IFC_H
 
+#ifdef CONFIG_FSL_IFC
 #include <config.h>
 #include <common.h>
 
@@ -798,13 +799,15 @@ extern void init_early_memctl_regs(void);
 #define set_ifc_ftim(i, j, v) \
 			(out_be32(&(IFC_BASE_ADDR)->ftim_cs[i].ftim[j], v))
 
-#define FSL_IFC_BANK_COUNT	4
-
 enum ifc_chip_sel {
 	IFC_CS0,
 	IFC_CS1,
 	IFC_CS2,
 	IFC_CS3,
+	IFC_CS4,
+	IFC_CS5,
+	IFC_CS6,
+	IFC_CS7,
 };
 
 enum ifc_ftims {
@@ -907,6 +910,22 @@ struct fsl_ifc_gpcm {
 	u32 res4[0x1F3];
 };
 
+#ifdef CONFIG_SYS_FSL_IFC_BANK_COUNT
+#if (CONFIG_SYS_FSL_IFC_BANK_COUNT <= 8)
+#define CONFIG_SYS_FSL_IFC_CSPR_RES \
+	(0x25 - CONFIG_SYS_FSL_IFC_BANK_COUNT *	3)
+#define CONFIG_SYS_FSL_IFC_AMASK_RES \
+	(0x24 - CONFIG_SYS_FSL_IFC_BANK_COUNT *	3)
+#define CONFIG_SYS_FSL_IFC_CSOR_RES \
+	(0x24 - CONFIG_SYS_FSL_IFC_BANK_COUNT *	3)
+#define CONFIG_SYS_FSL_IFC_FTIM_RES \
+	(0x90 - CONFIG_SYS_FSL_IFC_BANK_COUNT *	0xc)
+#else
+#error IFC BANK count not vaild
+#endif
+#else
+#error IFC BANK count not defined
+#endif
 
 /*
  * IFC Controller Registers
@@ -918,24 +937,24 @@ struct fsl_ifc {
 		u32 cspr_ext;
 		u32 cspr;
 		u32 res2;
-	} cspr_cs[FSL_IFC_BANK_COUNT];
-	u32 res3[0x19];
+	} cspr_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT];
+	u32 res3[CONFIG_SYS_FSL_IFC_CSPR_RES];
 	struct {
 		u32 amask;
 		u32 res4[0x2];
-	} amask_cs[FSL_IFC_BANK_COUNT];
-	u32 res5[0x17];
+	} amask_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT];
+	u32 res5[CONFIG_SYS_FSL_IFC_AMASK_RES];
 	struct {
-		u32 csor_ext;
 		u32 csor;
+		u32 csor_ext;
 		u32 res6;
-	} csor_cs[FSL_IFC_BANK_COUNT];
-	u32 res7[0x19];
+	} csor_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT];
+	u32 res7[CONFIG_SYS_FSL_IFC_CSOR_RES];
 	struct {
 		u32 ftim[4];
 		u32 res8[0x8];
-	} ftim_cs[FSL_IFC_BANK_COUNT];
-	u32 res9[0x60];
+	} ftim_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT];
+	u32 res9[CONFIG_SYS_FSL_IFC_FTIM_RES];
 	u32 rb_stat;
 	u32 res10[0x2];
 	u32 ifc_gcr;
@@ -961,6 +980,7 @@ struct fsl_ifc {
 #undef CSPR_MSEL_NOR
 #define CSPR_MSEL_NOR	CSPR_MSEL_GPCM
 #endif
+#endif /* CONFIG_FSL_IFC */
 
 #endif /* __ASSEMBLY__ */
 #endif /* __ASM_PPC_FSL_IFC_H */
-- 
1.7.9.5

[U-Boot] [PATCH 04/21] powerpc/mpc85xx b8460 PCIe registers are not at QORIQ_CHASSIS2 location

[York Sun]

From: Ed Swarthout <ed.swarthout@freescale.com>

Even B4860 has chassis generation 2, but its PCIe registers are at
the same location as other corenet SoCs.

Signed-off-by: Ed Swarthout <ed.swarthout@freescale.com>
---
 arch/powerpc/include/asm/immap_85xx.h |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 99b6bb3..c09c127 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -2954,7 +2954,7 @@ struct ccsr_pman {
 #define CONFIG_SYS_MPC85xx_IFC_OFFSET		0x124000
 #define CONFIG_SYS_MPC85xx_GPIO_OFFSET		0x130000
 #define CONFIG_SYS_FSL_CORENET_RMAN_OFFSET	0x1e0000
-#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
+#if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && !defined(CONFIG_PPC_B4860)
 #define CONFIG_SYS_MPC85xx_PCIE1_OFFSET		0x240000
 #define CONFIG_SYS_MPC85xx_PCIE2_OFFSET		0x250000
 #define CONFIG_SYS_MPC85xx_PCIE3_OFFSET		0x260000
-- 
1.7.9.5

[U-Boot] [PATCH 05/21] powerpc/mpc85xx: Add setting of clock-frequency for T4/B4 clockgen node

[York Sun]

From: Tang Yuantian <Yuantian.Tang@freescale.com>

For T4/B4, the clockgen node compatible string is updated to version 2.
Add clock-frequency setting for this new version.

Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
---
 arch/powerpc/cpu/mpc85xx/fdt.c |    2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c
index 24eb978..cda6ad6 100644
--- a/arch/powerpc/cpu/mpc85xx/fdt.c
+++ b/arch/powerpc/cpu/mpc85xx/fdt.c
@@ -663,6 +663,8 @@ void ft_cpu_setup(void *blob, bd_t *bd)
 #ifdef CONFIG_FSL_CORENET
 	do_fixup_by_compat_u32(blob, "fsl,qoriq-clockgen-1.0",
 		"clock-frequency", CONFIG_SYS_CLK_FREQ, 1);
+	do_fixup_by_compat_u32(blob, "fsl,qoriq-clockgen-2",
+		"clock-frequency", CONFIG_SYS_CLK_FREQ, 1);
 #endif
 
 	fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
-- 
1.7.9.5

[U-Boot] [PATCH 06/21] t4240qds/eth: fixup ethernet for t4240qds

[York Sun]

From: Shengzhou Liu <Shengzhou.Liu@freescale.com>

1, Implemented board_ft_fman_fixup_port() to fix port for kernel.
2, Implemented fdt_fixup_board_enet() to fix node status of different
   slots and interfaces.
3, Adding detection of slot present for XGMII interface.
4, There is no PHY for XFI, so removed related phy address settings.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
---
 arch/powerpc/include/asm/fsl_serdes.h |    1 +
 board/freescale/t4qds/eth.c           |  104 ++++++++++++++++++++++++++++-----
 include/configs/t4qds.h               |    4 --
 3 files changed, 91 insertions(+), 18 deletions(-)

diff --git a/arch/powerpc/include/asm/fsl_serdes.h b/arch/powerpc/include/asm/fsl_serdes.h
index 6cd7379..c462455 100644
--- a/arch/powerpc/include/asm/fsl_serdes.h
+++ b/arch/powerpc/include/asm/fsl_serdes.h
@@ -91,6 +91,7 @@ enum srds {
 
 int is_serdes_configured(enum srds_prtcl device);
 void fsl_serdes_init(void);
+enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane);
 
 #ifdef CONFIG_FSL_CORENET
 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
diff --git a/board/freescale/t4qds/eth.c b/board/freescale/t4qds/eth.c
index a49c7d4..8d2c33f 100644
--- a/board/freescale/t4qds/eth.c
+++ b/board/freescale/t4qds/eth.c
@@ -52,7 +52,7 @@
 #define EMI1_SLOT4	4
 #define EMI1_SLOT5	5
 #define EMI1_SLOT7	7
-#define EMI2		8 /* tmp, FIXME */
+#define EMI2		8
 /* Slot6 and Slot8 do not have EMI connections */
 
 static int mdio_mux[NUM_FM_PORTS];
@@ -180,21 +180,86 @@ static int t4240qds_mdio_init(char *realbusname, u8 muxval)
 void board_ft_fman_fixup_port(void *blob, char * prop, phys_addr_t pa,
 				enum fm_port port, int offset)
 {
-	if (mdio_mux[port] == EMI1_RGMII)
-		fdt_set_phy_handle(blob, prop, pa, "phy_rgmii");
-
-	/* TODO: will do with dts */
+	if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
+		switch (port) {
+		case FM1_DTSEC9:
+			fdt_set_phy_handle(blob, prop, pa, "phy_sgmii4");
+			break;
+		case FM1_DTSEC10:
+			fdt_set_phy_handle(blob, prop, pa, "phy_sgmii3");
+			break;
+		case FM2_DTSEC9:
+			fdt_set_phy_handle(blob, prop, pa, "phy_sgmii12");
+			break;
+		case FM2_DTSEC10:
+			fdt_set_phy_handle(blob, prop, pa, "phy_sgmii11");
+			break;
+		default:
+			break;
+		}
+	}
 }
 
 void fdt_fixup_board_enet(void *fdt)
 {
-	/* TODO: will do with dts */
+	int i;
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	u32 prtcl2 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
+
+	prtcl2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
+	for (i = FM1_DTSEC1; i < NUM_FM_PORTS; i++) {
+		switch (fm_info_get_enet_if(i)) {
+		case PHY_INTERFACE_MODE_SGMII:
+			switch (mdio_mux[i]) {
+			case EMI1_SLOT1:
+				fdt_status_okay_by_alias(fdt, "emi1_slot1");
+				break;
+			case EMI1_SLOT2:
+				fdt_status_okay_by_alias(fdt, "emi1_slot2");
+				break;
+			case EMI1_SLOT3:
+				fdt_status_okay_by_alias(fdt, "emi1_slot3");
+				break;
+			case EMI1_SLOT4:
+				fdt_status_okay_by_alias(fdt, "emi1_slot4");
+				break;
+			default:
+				break;
+			}
+			break;
+		case PHY_INTERFACE_MODE_XGMII:
+			/* check if it's XFI interface for 10g */
+			if ((prtcl2 == 56) || (prtcl2 == 57)) {
+				fdt_status_okay_by_alias(fdt, "emi2_xfislot3");
+				break;
+			}
+			switch (i) {
+			case FM1_10GEC1:
+				fdt_status_okay_by_alias(fdt, "emi2_xauislot1");
+				break;
+			case FM1_10GEC2:
+				fdt_status_okay_by_alias(fdt, "emi2_xauislot2");
+				break;
+			case FM2_10GEC1:
+				fdt_status_okay_by_alias(fdt, "emi2_xauislot3");
+				break;
+			case FM2_10GEC2:
+				fdt_status_okay_by_alias(fdt, "emi2_xauislot4");
+				break;
+			default:
+				break;
+			}
+			break;
+		default:
+			break;
+		}
+	}
 }
 
 int board_eth_init(bd_t *bis)
 {
 #if defined(CONFIG_FMAN_ENET)
-	int i;
+	int i, idx, lane, slot;
 	struct memac_mdio_info dtsec_mdio_info;
 	struct memac_mdio_info tgec_mdio_info;
 	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
@@ -293,7 +358,7 @@ int board_eth_init(bd_t *bis)
 	}
 
 	for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
-		int idx = i - FM1_DTSEC1, lane, slot;
+		idx = i - FM1_DTSEC1;
 		switch (fm_info_get_enet_if(i)) {
 		case PHY_INTERFACE_MODE_SGMII:
 			lane = serdes_get_first_lane(FSL_SRDS_1,
@@ -334,8 +399,16 @@ int board_eth_init(bd_t *bis)
 	}
 
 	for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
+		idx = i - FM1_10GEC1;
 		switch (fm_info_get_enet_if(i)) {
 		case PHY_INTERFACE_MODE_XGMII:
+			lane = serdes_get_first_lane(FSL_SRDS_1,
+						XAUI_FM1_MAC9 + idx);
+			if (lane < 0)
+				break;
+			slot = lane_to_slot_fsm1[lane];
+			if (QIXIS_READ(present2) & (1 << (slot - 1)))
+				fm_disable_port(i);
 			mdio_mux[i] = EMI2;
 			fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
 			break;
@@ -344,7 +417,6 @@ int board_eth_init(bd_t *bis)
 		}
 	}
 
-
 #if (CONFIG_SYS_NUM_FMAN == 2)
 	switch (srds_prtcl_s2) {
 	case 1:
@@ -418,10 +490,6 @@ int board_eth_init(bd_t *bis)
 	case 56:
 	case 57:
 		/* XFI in Slot3, SGMII in Slot4 */
-		fm_info_set_phy_address(FM1_10GEC1, XFI_CARD_PORT1_PHY_ADDR);
-		fm_info_set_phy_address(FM1_10GEC2, XFI_CARD_PORT2_PHY_ADDR);
-		fm_info_set_phy_address(FM2_10GEC2, XFI_CARD_PORT3_PHY_ADDR);
-		fm_info_set_phy_address(FM2_10GEC1, XFI_CARD_PORT4_PHY_ADDR);
 		fm_info_set_phy_address(FM2_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
 		fm_info_set_phy_address(FM2_DTSEC2, SGMII_CARD_PORT2_PHY_ADDR);
 		fm_info_set_phy_address(FM2_DTSEC3, SGMII_CARD_PORT3_PHY_ADDR);
@@ -433,7 +501,7 @@ int board_eth_init(bd_t *bis)
 	}
 
 	for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) {
-		int idx = i - FM2_DTSEC1, lane, slot;
+		idx = i - FM2_DTSEC1;
 		switch (fm_info_get_enet_if(i)) {
 		case PHY_INTERFACE_MODE_SGMII:
 			lane = serdes_get_first_lane(FSL_SRDS_2,
@@ -477,8 +545,16 @@ int board_eth_init(bd_t *bis)
 	}
 
 	for (i = FM2_10GEC1; i < FM2_10GEC1 + CONFIG_SYS_NUM_FM2_10GEC; i++) {
+		idx = i - FM2_10GEC1;
 		switch (fm_info_get_enet_if(i)) {
 		case PHY_INTERFACE_MODE_XGMII:
+			lane = serdes_get_first_lane(FSL_SRDS_2,
+						XAUI_FM2_MAC9 + idx);
+			if (lane < 0)
+				break;
+			slot = lane_to_slot_fsm2[lane];
+			if (QIXIS_READ(present2) & (1 << (slot - 1)))
+				fm_disable_port(i);
 			mdio_mux[i] = EMI2;
 			fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
 			break;
diff --git a/include/configs/t4qds.h b/include/configs/t4qds.h
index a8346f0..ef8c5b2 100644
--- a/include/configs/t4qds.h
+++ b/include/configs/t4qds.h
@@ -649,10 +649,6 @@ unsigned long get_board_ddr_clk(void);
 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
-#define XFI_CARD_PORT1_PHY_ADDR	0x1 /* tmp, FIXME below addr */
-#define XFI_CARD_PORT2_PHY_ADDR	0x2
-#define XFI_CARD_PORT3_PHY_ADDR	0x3
-#define XFI_CARD_PORT4_PHY_ADDR	0x4
 #define QSGMII_CARD_PHY_ADDR	0x5
 #define FM1_10GEC1_PHY_ADDR	0x0
 #define FM1_10GEC2_PHY_ADDR	0x1
-- 
1.7.9.5

[U-Boot] [PATCH 07/21] net/fm: fixup ethernet for mEMAC

[York Sun]

From: Shengzhou Liu <Shengzhou.Liu@freescale.com>

- set proper compatible property name for mEMAC.
- fixed ft_fixup_port for dual-role mEMAC, which will lead to
  MAC node disabled incorrectly.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
---
 drivers/net/fm/fm.h   |    2 ++
 drivers/net/fm/init.c |   24 ++++++++++++++++++++++++
 2 files changed, 26 insertions(+)

diff --git a/drivers/net/fm/fm.h b/drivers/net/fm/fm.h
index 228df33..ba581e9 100644
--- a/drivers/net/fm/fm.h
+++ b/drivers/net/fm/fm.h
@@ -152,4 +152,6 @@ struct fm_eth {
 #define MAX_RXBUF_LOG2		11
 #define MAX_RXBUF_LEN		(1 << MAX_RXBUF_LOG2)
 
+#define PORT_IS_ENABLED(port)	fm_info[fm_port_to_index(port)].enabled
+
 #endif /* __FM_H__ */
diff --git a/drivers/net/fm/init.c b/drivers/net/fm/init.c
index d12ec9b..bcec525 100644
--- a/drivers/net/fm/init.c
+++ b/drivers/net/fm/init.c
@@ -238,6 +238,25 @@ static void ft_fixup_port(void *blob, struct fm_eth_info *info, char *prop)
 		return ;
 	}
 
+#ifdef CONFIG_SYS_FMAN_V3
+	/*
+	 * Physically FM1_DTSEC9 and FM1_10GEC1 use the same dual-role MAC, when
+	 * FM1_10GEC1 is enabled and  FM1_DTSEC9 is disabled, ensure that the
+	 * dual-role MAC is not disabled, ditto for other dual-role MACs.
+	 */
+	if (((info->port == FM1_DTSEC9) && (PORT_IS_ENABLED(FM1_10GEC1)))
+	    || ((info->port == FM1_DTSEC10) && (PORT_IS_ENABLED(FM1_10GEC2)))
+	    || ((info->port == FM1_10GEC1) && (PORT_IS_ENABLED(FM1_DTSEC9)))
+	    || ((info->port == FM1_10GEC2) && (PORT_IS_ENABLED(FM1_DTSEC10)))
+#if (CONFIG_SYS_NUM_FMAN == 2)
+	    || ((info->port == FM2_DTSEC9) && (PORT_IS_ENABLED(FM2_10GEC1)))
+	    || ((info->port == FM2_DTSEC10) && (PORT_IS_ENABLED(FM2_10GEC2)))
+	    || ((info->port == FM2_10GEC1) && (PORT_IS_ENABLED(FM2_DTSEC9)))
+	    || ((info->port == FM2_10GEC2) && (PORT_IS_ENABLED(FM2_DTSEC10)))
+#endif
+	)
+		return;
+#endif
 	/* board code might have caused offset to change */
 	off = fdt_node_offset_by_compat_reg(blob, prop, paddr);
 
@@ -255,10 +274,15 @@ void fdt_fixup_fman_ethernet(void *blob)
 {
 	int i;
 
+#ifdef CONFIG_SYS_FMAN_V3
+	for (i = 0; i < ARRAY_SIZE(fm_info); i++)
+		ft_fixup_port(blob, &fm_info[i], "fsl,fman-memac");
+#else
 	for (i = 0; i < ARRAY_SIZE(fm_info); i++) {
 		if (fm_info[i].type == FM_ETH_1G_E)
 			ft_fixup_port(blob, &fm_info[i], "fsl,fman-1g-mac");
 		else
 			ft_fixup_port(blob, &fm_info[i], "fsl,fman-10g-mac");
 	}
+#endif
 }
-- 
1.7.9.5

[U-Boot] [PATCH 08/21] powerpc/85xx: fix build error introduced by serdes_get_prtcl

[York Sun]

From: Shengzhou Liu <Shengzhou.Liu@freescale.com>

Removed unused declare serdes_get_prtcl() which was no longer needed.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
---
 arch/powerpc/include/asm/fsl_serdes.h |    1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/powerpc/include/asm/fsl_serdes.h b/arch/powerpc/include/asm/fsl_serdes.h
index c462455..6cd7379 100644
--- a/arch/powerpc/include/asm/fsl_serdes.h
+++ b/arch/powerpc/include/asm/fsl_serdes.h
@@ -91,7 +91,6 @@ enum srds {
 
 int is_serdes_configured(enum srds_prtcl device);
 void fsl_serdes_init(void);
-enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane);
 
 #ifdef CONFIG_FSL_CORENET
 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
-- 
1.7.9.5

[U-Boot] [PATCH 09/21] net/phy: add VSC8574 support

[York Sun]

From: Shaohui Xie <Shaohui.Xie@freescale.com>

The VSC8574 is a quad-port Gigabit Ethernet transceiver with four SerDes
interfaces for quad-port dual media capability. This driver supports SGMII
and QSGMII MAC mode. For now SGMII mode is tested.

Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
---
 drivers/net/phy/vitesse.c |   67 +++++++++++++++++++++++++++++++++++++++++++++
 include/phy.h             |    2 ++
 2 files changed, 69 insertions(+)

diff --git a/drivers/net/phy/vitesse.c b/drivers/net/phy/vitesse.c
index 6c5cb99..61f863e 100644
--- a/drivers/net/phy/vitesse.c
+++ b/drivers/net/phy/vitesse.c
@@ -48,6 +48,19 @@
 #define MIIM_VSC8601_SKEW_CTRL		0x1c
 
 #define PHY_EXT_PAGE_ACCESS    0x1f
+#define PHY_EXT_PAGE_ACCESS_GENERAL	0x10
+#define PHY_EXT_PAGE_ACCESS_EXTENDED3	0x3
+
+/* Vitesse VSC8574 control register */
+#define MIIM_VSC8574_MAC_SERDES_CON	0x10
+#define MIIM_VSC8574_MAC_SERDES_ANEG	0x80
+#define MIIM_VSC8574_GENERAL18		0x12
+#define MIIM_VSC8574_GENERAL19		0x13
+
+/* Vitesse VSC8574 gerenal purpose register 18 */
+#define MIIM_VSC8574_18G_SGMII		0x80f0
+#define MIIM_VSC8574_18G_QSGMII		0x80e0
+#define MIIM_VSC8574_18G_CMDSTAT	0x8000
 
 /* CIS8201 */
 static int vitesse_config(struct phy_device *phydev)
@@ -145,6 +158,49 @@ static int vsc8601_config(struct phy_device *phydev)
 	return 0;
 }
 
+static int vsc8574_config(struct phy_device *phydev)
+{
+	u32 val;
+	/* configure regiser 19G for MAC */
+	phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS,
+			PHY_EXT_PAGE_ACCESS_GENERAL);
+
+	val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8574_GENERAL19);
+	if (phydev->interface == PHY_INTERFACE_MODE_QSGMII) {
+		/* set bit 15:14 to '01' for QSGMII mode */
+		val = (val & 0x3fff) | (1 << 14);
+		phy_write(phydev, MDIO_DEVAD_NONE,
+				MIIM_VSC8574_GENERAL19, val);
+		/* Enable 4 ports MAC QSGMII */
+		phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8574_GENERAL18,
+				MIIM_VSC8574_18G_QSGMII);
+	} else {
+		/* set bit 15:14 to '00' for SGMII mode */
+		val = val & 0x3fff;
+		phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8574_GENERAL19, val);
+		/* Enable 4 ports MAC SGMII */
+		phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8574_GENERAL18,
+				MIIM_VSC8574_18G_SGMII);
+	}
+	val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8574_GENERAL18);
+	/* When bit 15 is cleared the command has completed */
+	while (val & MIIM_VSC8574_18G_CMDSTAT)
+		val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8574_GENERAL18);
+
+	/* Enable Serdes Auto-negotiation */
+	phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS,
+			PHY_EXT_PAGE_ACCESS_EXTENDED3);
+	val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8574_MAC_SERDES_CON);
+	val = val | MIIM_VSC8574_MAC_SERDES_ANEG;
+	phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8574_MAC_SERDES_CON, val);
+
+	phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS, 0);
+
+	genphy_config_aneg(phydev);
+
+	return 0;
+}
+
 static struct phy_driver VSC8211_driver = {
 	.name	= "Vitesse VSC8211",
 	.uid	= 0xfc4b0,
@@ -185,6 +241,16 @@ static struct phy_driver VSC8234_driver = {
 	.shutdown = &genphy_shutdown,
 };
 
+static struct phy_driver VSC8574_driver = {
+	.name = "Vitesse VSC8574",
+	.uid = 0x704a0,
+	.mask = 0xffff0,
+	.features = PHY_GBIT_FEATURES,
+	.config = &vsc8574_config,
+	.startup = &vitesse_startup,
+	.shutdown = &genphy_shutdown,
+};
+
 static struct phy_driver VSC8601_driver = {
 	.name = "Vitesse VSC8601",
 	.uid = 0x70420,
@@ -244,6 +310,7 @@ int phy_vitesse_init(void)
 	phy_register(&VSC8244_driver);
 	phy_register(&VSC8211_driver);
 	phy_register(&VSC8221_driver);
+	phy_register(&VSC8574_driver);
 	phy_register(&VSC8662_driver);
 	phy_register(&cis8201_driver);
 	phy_register(&cis8204_driver);
diff --git a/include/phy.h b/include/phy.h
index 58ca273..44d5eaf 100644
--- a/include/phy.h
+++ b/include/phy.h
@@ -52,6 +52,7 @@ typedef enum {
 	PHY_INTERFACE_MODE_MII,
 	PHY_INTERFACE_MODE_GMII,
 	PHY_INTERFACE_MODE_SGMII,
+	PHY_INTERFACE_MODE_QSGMII,
 	PHY_INTERFACE_MODE_TBI,
 	PHY_INTERFACE_MODE_RMII,
 	PHY_INTERFACE_MODE_RGMII,
@@ -67,6 +68,7 @@ static const char *phy_interface_strings[] = {
 	[PHY_INTERFACE_MODE_MII]		= "mii",
 	[PHY_INTERFACE_MODE_GMII]		= "gmii",
 	[PHY_INTERFACE_MODE_SGMII]		= "sgmii",
+	[PHY_INTERFACE_MODE_QSGMII]		= "qsgmii",
 	[PHY_INTERFACE_MODE_TBI]		= "tbi",
 	[PHY_INTERFACE_MODE_RMII]		= "rmii",
 	[PHY_INTERFACE_MODE_RGMII]		= "rgmii",
-- 
1.7.9.5

[U-Boot] [PATCH 10/21] T4240/net: use QSGMII card PHY address by default

[York Sun]

From: Shaohui Xie <Shaohui.Xie@freescale.com>

Use QSGMII card PHY address as default SGMII card PHY address, QSGMII card
PHY address is variable depends on different slot.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
---
 board/freescale/t4qds/eth.c |  123 +++++++++++++++++++++++--------------------
 include/configs/t4qds.h     |    1 -
 2 files changed, 67 insertions(+), 57 deletions(-)

diff --git a/board/freescale/t4qds/eth.c b/board/freescale/t4qds/eth.c
index 8d2c33f..2232eea 100644
--- a/board/freescale/t4qds/eth.c
+++ b/board/freescale/t4qds/eth.c
@@ -71,6 +71,13 @@ static const char *mdio_names[] = {
 
 static u8 lane_to_slot_fsm1[] = {1, 1, 1, 1, 2, 2, 2, 2};
 static u8 lane_to_slot_fsm2[] = {3, 3, 3, 3, 4, 4, 4, 4};
+static u8 slot_qsgmii_phyaddr[5][4] = {
+	{0, 0, 0, 0},/* not used, to make index match slot No. */
+	{0, 1, 2, 3},
+	{4, 5, 6, 7},
+	{8, 9, 0xa, 0xb},
+	{0xc, 0xd, 0xe, 0xf},
+};
 
 static const char *t4240qds_mdio_name_for_muxval(u8 muxval)
 {
@@ -313,44 +320,48 @@ int board_eth_init(bd_t *bis)
 	case 28:
 	case 36:
 		/* SGMII in Slot1 and Slot2 */
-		fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT2_PHY_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_PORT3_PHY_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC4, SGMII_CARD_PORT4_PHY_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
+		fm_info_set_phy_address(FM1_DTSEC1, slot_qsgmii_phyaddr[2][0]);
+		fm_info_set_phy_address(FM1_DTSEC2, slot_qsgmii_phyaddr[2][1]);
+		fm_info_set_phy_address(FM1_DTSEC3, slot_qsgmii_phyaddr[2][2]);
+		fm_info_set_phy_address(FM1_DTSEC4, slot_qsgmii_phyaddr[2][3]);
+		fm_info_set_phy_address(FM1_DTSEC5, slot_qsgmii_phyaddr[1][0]);
+		fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]);
 		if ((srds_prtcl_s2 != 56) && (srds_prtcl_s2 != 57)) {
 			fm_info_set_phy_address(FM1_DTSEC9,
-						SGMII_CARD_PORT4_PHY_ADDR);
+						slot_qsgmii_phyaddr[1][3]);
 			fm_info_set_phy_address(FM1_DTSEC10,
-						SGMII_CARD_PORT3_PHY_ADDR);
+						slot_qsgmii_phyaddr[1][2]);
 		}
 		break;
 	case 38:
-		fm_info_set_phy_address(FM1_DTSEC5, QSGMII_CARD_PHY_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC6, QSGMII_CARD_PHY_ADDR);
+		fm_info_set_phy_address(FM1_DTSEC1, slot_qsgmii_phyaddr[2][0]);
+		fm_info_set_phy_address(FM1_DTSEC2, slot_qsgmii_phyaddr[2][1]);
+		fm_info_set_phy_address(FM1_DTSEC3, slot_qsgmii_phyaddr[2][2]);
+		fm_info_set_phy_address(FM1_DTSEC4, slot_qsgmii_phyaddr[2][3]);
+		fm_info_set_phy_address(FM1_DTSEC5, slot_qsgmii_phyaddr[1][0]);
+		fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]);
 		if ((srds_prtcl_s2 != 56) && (srds_prtcl_s2 != 57)) {
 			fm_info_set_phy_address(FM1_DTSEC9,
-						QSGMII_CARD_PHY_ADDR);
+						slot_qsgmii_phyaddr[1][3]);
 			fm_info_set_phy_address(FM1_DTSEC10,
-						QSGMII_CARD_PHY_ADDR);
+						slot_qsgmii_phyaddr[1][2]);
 		}
 		break;
 	case 40:
 	case 46:
 	case 48:
-		fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
+		fm_info_set_phy_address(FM1_DTSEC5, slot_qsgmii_phyaddr[1][0]);
+		fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]);
 		if ((srds_prtcl_s2 != 56) && (srds_prtcl_s2 != 57)) {
 			fm_info_set_phy_address(FM1_DTSEC10,
-						SGMII_CARD_PORT3_PHY_ADDR);
+						slot_qsgmii_phyaddr[1][3]);
 			fm_info_set_phy_address(FM1_DTSEC9,
-						SGMII_CARD_PORT4_PHY_ADDR);
+						slot_qsgmii_phyaddr[1][2]);
 		}
-		fm_info_set_phy_address(FM1_DTSEC1, QSGMII_CARD_PHY_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC2, QSGMII_CARD_PHY_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC3, QSGMII_CARD_PHY_ADDR);
-		fm_info_set_phy_address(FM1_DTSEC4, QSGMII_CARD_PHY_ADDR);
+		fm_info_set_phy_address(FM1_DTSEC1, slot_qsgmii_phyaddr[2][0]);
+		fm_info_set_phy_address(FM1_DTSEC2, slot_qsgmii_phyaddr[2][1]);
+		fm_info_set_phy_address(FM1_DTSEC3, slot_qsgmii_phyaddr[2][2]);
+		fm_info_set_phy_address(FM1_DTSEC4, slot_qsgmii_phyaddr[2][3]);
 		break;
 	default:
 		puts("Invalid SerDes1 protocol for T4240QDS\n");
@@ -436,64 +447,64 @@ int board_eth_init(bd_t *bis)
 	case 26:
 		/* XAUI/HiGig in Slot3, SGMII in Slot4 */
 		fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR);
-		fm_info_set_phy_address(FM2_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
-		fm_info_set_phy_address(FM2_DTSEC2, SGMII_CARD_PORT2_PHY_ADDR);
-		fm_info_set_phy_address(FM2_DTSEC3, SGMII_CARD_PORT3_PHY_ADDR);
-		fm_info_set_phy_address(FM2_DTSEC4, SGMII_CARD_PORT4_PHY_ADDR);
+		fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
+		fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
+		fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
+		fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
 		break;
 	case 28:
 	case 36:
 		/* SGMII in Slot3 and Slot4 */
-		fm_info_set_phy_address(FM2_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
-		fm_info_set_phy_address(FM2_DTSEC2, SGMII_CARD_PORT2_PHY_ADDR);
-		fm_info_set_phy_address(FM2_DTSEC3, SGMII_CARD_PORT3_PHY_ADDR);
-		fm_info_set_phy_address(FM2_DTSEC4, SGMII_CARD_PORT4_PHY_ADDR);
-		fm_info_set_phy_address(FM2_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR);
-		fm_info_set_phy_address(FM2_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
-		fm_info_set_phy_address(FM2_DTSEC9, SGMII_CARD_PORT4_PHY_ADDR);
-		fm_info_set_phy_address(FM2_DTSEC10, SGMII_CARD_PORT3_PHY_ADDR);
+		fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
+		fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
+		fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
+		fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
+		fm_info_set_phy_address(FM2_DTSEC5, slot_qsgmii_phyaddr[3][0]);
+		fm_info_set_phy_address(FM2_DTSEC6, slot_qsgmii_phyaddr[3][1]);
+		fm_info_set_phy_address(FM2_DTSEC9, slot_qsgmii_phyaddr[3][3]);
+		fm_info_set_phy_address(FM2_DTSEC10, slot_qsgmii_phyaddr[3][2]);
 		break;
 	case 38:
 		/* QSGMII in Slot3 and Slot4 */
-		fm_info_set_phy_address(FM2_DTSEC1, QSGMII_CARD_PHY_ADDR);
-		fm_info_set_phy_address(FM2_DTSEC2, QSGMII_CARD_PHY_ADDR);
-		fm_info_set_phy_address(FM2_DTSEC3, QSGMII_CARD_PHY_ADDR);
-		fm_info_set_phy_address(FM2_DTSEC4, QSGMII_CARD_PHY_ADDR);
-		fm_info_set_phy_address(FM2_DTSEC5, QSGMII_CARD_PHY_ADDR);
-		fm_info_set_phy_address(FM2_DTSEC6, QSGMII_CARD_PHY_ADDR);
-		fm_info_set_phy_address(FM2_DTSEC9, QSGMII_CARD_PHY_ADDR);
-		fm_info_set_phy_address(FM2_DTSEC10, QSGMII_CARD_PHY_ADDR);
+		fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
+		fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
+		fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
+		fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
+		fm_info_set_phy_address(FM2_DTSEC5, slot_qsgmii_phyaddr[3][0]);
+		fm_info_set_phy_address(FM2_DTSEC6, slot_qsgmii_phyaddr[3][1]);
+		fm_info_set_phy_address(FM2_DTSEC9, slot_qsgmii_phyaddr[3][3]);
+		fm_info_set_phy_address(FM2_DTSEC10, slot_qsgmii_phyaddr[3][2]);
 		break;
 	case 40:
 	case 46:
 	case 48:
 		/* SGMII in Slot3 */
-		fm_info_set_phy_address(FM2_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR);
-		fm_info_set_phy_address(FM2_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
-		fm_info_set_phy_address(FM2_DTSEC9, SGMII_CARD_PORT4_PHY_ADDR);
-		fm_info_set_phy_address(FM2_DTSEC10, SGMII_CARD_PORT3_PHY_ADDR);
+		fm_info_set_phy_address(FM2_DTSEC5, slot_qsgmii_phyaddr[3][0]);
+		fm_info_set_phy_address(FM2_DTSEC6, slot_qsgmii_phyaddr[3][1]);
+		fm_info_set_phy_address(FM2_DTSEC9, slot_qsgmii_phyaddr[3][3]);
+		fm_info_set_phy_address(FM2_DTSEC10, slot_qsgmii_phyaddr[3][2]);
 		/* QSGMII in Slot4 */
-		fm_info_set_phy_address(FM2_DTSEC1, QSGMII_CARD_PHY_ADDR);
-		fm_info_set_phy_address(FM2_DTSEC2, QSGMII_CARD_PHY_ADDR);
-		fm_info_set_phy_address(FM2_DTSEC3, QSGMII_CARD_PHY_ADDR);
-		fm_info_set_phy_address(FM2_DTSEC4, QSGMII_CARD_PHY_ADDR);
+		fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
+		fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
+		fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
+		fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
 		break;
 	case 50:
 	case 52:
 	case 54:
 		fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR);
-		fm_info_set_phy_address(FM2_DTSEC1, QSGMII_CARD_PHY_ADDR);
-		fm_info_set_phy_address(FM2_DTSEC2, QSGMII_CARD_PHY_ADDR);
-		fm_info_set_phy_address(FM2_DTSEC3, QSGMII_CARD_PHY_ADDR);
-		fm_info_set_phy_address(FM2_DTSEC4, QSGMII_CARD_PHY_ADDR);
+		fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
+		fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
+		fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
+		fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
 		break;
 	case 56:
 	case 57:
 		/* XFI in Slot3, SGMII in Slot4 */
-		fm_info_set_phy_address(FM2_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
-		fm_info_set_phy_address(FM2_DTSEC2, SGMII_CARD_PORT2_PHY_ADDR);
-		fm_info_set_phy_address(FM2_DTSEC3, SGMII_CARD_PORT3_PHY_ADDR);
-		fm_info_set_phy_address(FM2_DTSEC4, SGMII_CARD_PORT4_PHY_ADDR);
+		fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
+		fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
+		fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
+		fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
 		break;
 	default:
 		puts("Invalid SerDes2 protocol for T4240QDS\n");
diff --git a/include/configs/t4qds.h b/include/configs/t4qds.h
index ef8c5b2..b5462b7 100644
--- a/include/configs/t4qds.h
+++ b/include/configs/t4qds.h
@@ -649,7 +649,6 @@ unsigned long get_board_ddr_clk(void);
 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
-#define QSGMII_CARD_PHY_ADDR	0x5
 #define FM1_10GEC1_PHY_ADDR	0x0
 #define FM1_10GEC2_PHY_ADDR	0x1
 #define FM2_10GEC1_PHY_ADDR	0x2
-- 
1.7.9.5

[U-Boot] [PATCH 11/21] T4/usb: move usb 2.0 utmi dual phy init code to cpu_init.c

[York Sun]

From: Roy Zang <tie-fei.zang@freescale.com>

This is what we have done for the UTMI PHY on P3041/P5020. Then the PHY
initialization can be reused in kernel without  ?usb start? command.

Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
---
 arch/powerpc/cpu/mpc85xx/cpu_init.c |   22 ++++++++++++++++++++++
 drivers/usb/host/ehci-fsl.c         |   21 ---------------------
 2 files changed, 22 insertions(+), 21 deletions(-)

diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index de9d916..8b12dd2 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -623,6 +623,28 @@ skip_l2:
 	}
 #endif
 
+#if defined(CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE)
+		ccsr_usb_phy_t *usb_phy =
+			(void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR;
+		setbits_be32(&usb_phy->pllprg[1],
+				CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN |
+				CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN |
+				CONFIG_SYS_FSL_USB_PLLPRG2_MFI |
+				CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN);
+		setbits_be32(&usb_phy->port1.ctrl,
+				CONFIG_SYS_FSL_USB_CTRL_PHY_EN);
+		setbits_be32(&usb_phy->port1.drvvbuscfg,
+				CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN);
+		setbits_be32(&usb_phy->port1.pwrfltcfg,
+				CONFIG_SYS_FSL_USB_PWRFLT_CR_EN);
+		setbits_be32(&usb_phy->port2.ctrl,
+				CONFIG_SYS_FSL_USB_CTRL_PHY_EN);
+		setbits_be32(&usb_phy->port2.drvvbuscfg,
+				CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN);
+		setbits_be32(&usb_phy->port2.pwrfltcfg,
+				CONFIG_SYS_FSL_USB_PWRFLT_CR_EN);
+#endif
+
 #ifdef CONFIG_FMAN_ENET
 	fman_enet_init();
 #endif
diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
index 81a70c0..f54b408 100644
--- a/drivers/usb/host/ehci-fsl.c
+++ b/drivers/usb/host/ehci-fsl.c
@@ -89,27 +89,6 @@ int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
 
 	if (!strcmp(phy_type, "utmi")) {
 #if defined(CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY)
-#if defined(CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE)
-		ccsr_usb_phy_t *usb_phy =
-			(void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR;
-		setbits_be32(&usb_phy->pllprg[1],
-				CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN |
-				CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN |
-				CONFIG_SYS_FSL_USB_PLLPRG2_MFI |
-				CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN);
-		setbits_be32(&usb_phy->port1.ctrl,
-				CONFIG_SYS_FSL_USB_CTRL_PHY_EN);
-		setbits_be32(&usb_phy->port1.drvvbuscfg,
-				CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN);
-		setbits_be32(&usb_phy->port1.pwrfltcfg,
-				CONFIG_SYS_FSL_USB_PWRFLT_CR_EN);
-		setbits_be32(&usb_phy->port2.ctrl,
-				CONFIG_SYS_FSL_USB_CTRL_PHY_EN);
-		setbits_be32(&usb_phy->port2.drvvbuscfg,
-				CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN);
-		setbits_be32(&usb_phy->port2.pwrfltcfg,
-				CONFIG_SYS_FSL_USB_PWRFLT_CR_EN);
-#endif
 		setbits_be32(&ehci->control, PHY_CLK_SEL_UTMI);
 		setbits_be32(&ehci->control, UTMI_PHY_EN);
 		udelay(1000); /* delay required for PHY Clk to appear */
-- 
1.7.9.5

[U-Boot] [PATCH 12/21] powerpc/mpc85xx: Update workaround for DDR erratum A-004934

[York Sun]

The workaround has been updated to use a slightly different magic number.
Change from 0x00003000 to 0x30003000.

Signed-off-by: York Sun <yorksun@freescale.com>
---
 arch/powerpc/cpu/mpc85xx/ddr-gen3.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/powerpc/cpu/mpc85xx/ddr-gen3.c b/arch/powerpc/cpu/mpc85xx/ddr-gen3.c
index ef0dd1d..c5b4720 100644
--- a/arch/powerpc/cpu/mpc85xx/ddr-gen3.c
+++ b/arch/powerpc/cpu/mpc85xx/ddr-gen3.c
@@ -142,7 +142,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 		}
 	}
 #ifdef CONFIG_SYS_FSL_ERRATUM_A_004934
-	out_be32(&ddr->debug[28], 0x00003000);
+	out_be32(&ddr->debug[28], 0x30003000);
 #endif
 
 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003474
-- 
1.7.9.5

[U-Boot] [PATCH 13/21] powerpc/mpc8xxx: Allow board file to override DDR address assignment

[York Sun]

This gives boards flexibility to assign other than default addresses to each
DDR controller. For example, DDR controler 2 can have 0 as the base and DDR
controller 1 has higher memory.

Signed-off-by: York Sun <yorksun@freescale.com>
---
 arch/powerpc/cpu/mpc8xxx/ddr/main.c |    7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/main.c b/arch/powerpc/cpu/mpc8xxx/ddr/main.c
index 1a8d593..7a8636d 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/main.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/main.c
@@ -186,7 +186,7 @@ const char * step_to_string(unsigned int step) {
 	return step_string_tbl[s];
 }
 
-unsigned long long step_assign_addresses(fsl_ddr_info_t *pinfo,
+static unsigned long long __step_assign_addresses(fsl_ddr_info_t *pinfo,
 			  unsigned int dbw_cap_adj[])
 {
 	int i, j;
@@ -354,6 +354,11 @@ unsigned long long step_assign_addresses(fsl_ddr_info_t *pinfo,
 	return total_mem;
 }
 
+/* Use weak function to allow board file to override the address assignment */
+__attribute__((weak, alias("__step_assign_addresses")))
+unsigned long long step_assign_addresses(fsl_ddr_info_t *pinfo,
+			  unsigned int dbw_cap_adj[]);
+
 unsigned long long
 fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
 				       unsigned int size_only)
-- 
1.7.9.5

[U-Boot] [PATCH 14/21] powerpc/b4860qds: Assign DDR address in board file

[York Sun]

B4860QDS requires DDRC2 has 0 as base address and DDRC1 has higher address.
This is the requirement for DSP cores to run in 32-bit address space.

Signed-off-by: York Sun <yorksun@freescale.com>
---
 board/freescale/b4860qds/ddr.c |   72 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 72 insertions(+)

diff --git a/board/freescale/b4860qds/ddr.c b/board/freescale/b4860qds/ddr.c
index dd4c0f6..f19f338 100644
--- a/board/freescale/b4860qds/ddr.c
+++ b/board/freescale/b4860qds/ddr.c
@@ -13,6 +13,7 @@
 #include <asm/fsl_ddr_sdram.h>
 #include <asm/fsl_ddr_dimm_params.h>
 #include <asm/fsl_law.h>
+#include <../arch/powerpc/cpu/mpc8xxx/ddr/ddr.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -188,3 +189,74 @@ phys_size_t initdram(int board_type)
 	puts("    DDR: ");
 	return dram_size;
 }
+
+unsigned long long step_assign_addresses(fsl_ddr_info_t *pinfo,
+			  unsigned int dbw_cap_adj[])
+{
+	int i, j;
+	unsigned long long total_mem, current_mem_base, total_ctlr_mem;
+	unsigned long long rank_density, ctlr_density = 0;
+
+	current_mem_base = 0ull;
+	total_mem = 0;
+	/*
+	 * This board has soldered DDR chips. DDRC1 has two rank.
+	 * DDRC2 has only one rank.
+	 * Assigning DDRC2 to lower address and DDRC1 to higher address.
+	 */
+	if (pinfo->memctl_opts[0].memctl_interleaving) {
+		rank_density = pinfo->dimm_params[0][0].rank_density >>
+					dbw_cap_adj[0];
+		ctlr_density = rank_density;
+
+		debug("rank density is 0x%llx, ctlr density is 0x%llx\n",
+			rank_density, ctlr_density);
+		for (i = CONFIG_NUM_DDR_CONTROLLERS - 1; i >= 0; i--) {
+			switch (pinfo->memctl_opts[i].memctl_interleaving_mode) {
+			case FSL_DDR_CACHE_LINE_INTERLEAVING:
+			case FSL_DDR_PAGE_INTERLEAVING:
+			case FSL_DDR_BANK_INTERLEAVING:
+			case FSL_DDR_SUPERBANK_INTERLEAVING:
+				total_ctlr_mem = 2 * ctlr_density;
+				break;
+			default:
+				panic("Unknown interleaving mode");
+			}
+			pinfo->common_timing_params[i].base_address =
+						current_mem_base;
+			pinfo->common_timing_params[i].total_mem =
+						total_ctlr_mem;
+			total_mem = current_mem_base + total_ctlr_mem;
+			debug("ctrl %d base 0x%llx\n", i, current_mem_base);
+			debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem);
+		}
+	} else {
+		/*
+		 * Simple linear assignment if memory
+		 * controllers are not interleaved.
+		 */
+		for (i = CONFIG_NUM_DDR_CONTROLLERS - 1; i >= 0; i--) {
+			total_ctlr_mem = 0;
+			pinfo->common_timing_params[i].base_address =
+						current_mem_base;
+			for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
+				/* Compute DIMM base addresses. */
+				unsigned long long cap =
+					pinfo->dimm_params[i][j].capacity;
+				pinfo->dimm_params[i][j].base_address =
+					current_mem_base;
+				debug("ctrl %d dimm %d base 0x%llx\n",
+					i, j, current_mem_base);
+				current_mem_base += cap;
+				total_ctlr_mem += cap;
+			}
+			debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem);
+			pinfo->common_timing_params[i].total_mem =
+							total_ctlr_mem;
+			total_mem += total_ctlr_mem;
+		}
+	}
+	debug("Total mem by %s is 0x%llx\n", __func__, total_mem);
+
+	return total_mem;
+}
-- 
1.7.9.5

[U-Boot] [PATCH 15/21] powerpc/t4qds: Fix disabling remote I2C connection

[York Sun]

From: Ed Swarthout <Ed.Swarthout@freescale.com>

Only clear IRE bit in qixis brdcfg5 register and keep other bits
unchanged.

Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
---
 board/freescale/t4qds/t4240qds_qixis.h |    2 +-
 board/freescale/t4qds/t4qds.c          |    4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/board/freescale/t4qds/t4240qds_qixis.h b/board/freescale/t4qds/t4240qds_qixis.h
index efb718d..485353d 100644
--- a/board/freescale/t4qds/t4240qds_qixis.h
+++ b/board/freescale/t4qds/t4240qds_qixis.h
@@ -42,7 +42,7 @@
 #define QIXIS_DDRCLK_125		0x2
 #define QIXIS_DDRCLK_133		0x3
 
-#define BRDCFG5_RESET			0x00
+#define BRDCFG5_IRE			0x20	/* i2c Remote i2c1 enable */
 
 #define BRDCFG12_SD3EN_MASK		0x20
 #define BRDCFG12_SD3MX_MASK		0x08
diff --git a/board/freescale/t4qds/t4qds.c b/board/freescale/t4qds/t4qds.c
index 06243b3..2f4575b 100644
--- a/board/freescale/t4qds/t4qds.c
+++ b/board/freescale/t4qds/t4qds.c
@@ -505,8 +505,8 @@ int board_early_init_r(void)
 	setup_portals();
 #endif
 
-	/* Disable remote I2C connectoin */
-	QIXIS_WRITE(brdcfg[5], BRDCFG5_RESET);
+	/* Disable remote I2C connection to qixis fpga */
+	QIXIS_WRITE(brdcfg[5], QIXIS_READ(brdcfg[5]) & ~BRDCFG5_IRE);
 
 	/*
 	 * Adjust core voltage according to voltage ID
-- 
1.7.9.5

[U-Boot] [PATCH 16/21] T4240/eth: fix SGMII card PHY address

[York Sun]

From: Shaohui Xie <Shaohui.Xie@freescale.com>

QSGMII card assumed to be used by default, but if SGMII card is used,
it will use different PHY address, but we don't know which card is used
until we access PHY on the card. So we check the card type slot by slot,
if we can read a PHY ID by reading a SGMII PHY address on a slot, then
the slot must have a SGMII card pluged, we mark all ports on that slot,
and fix dts to use the SGMII card PHY address when doing dts fixup
for the marked ports.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
---
 board/freescale/t4qds/eth.c |  137 +++++++++++++++++++++++++++++++++++++++++--
 1 file changed, 133 insertions(+), 4 deletions(-)

diff --git a/board/freescale/t4qds/eth.c b/board/freescale/t4qds/eth.c
index 2232eea..ec0afce 100644
--- a/board/freescale/t4qds/eth.c
+++ b/board/freescale/t4qds/eth.c
@@ -78,6 +78,7 @@ static u8 slot_qsgmii_phyaddr[5][4] = {
 	{8, 9, 0xa, 0xb},
 	{0xc, 0xd, 0xe, 0xf},
 };
+static u8 qsgmiiphy_fix[NUM_FM_PORTS] = {0};
 
 static const char *t4240qds_mdio_name_for_muxval(u8 muxval)
 {
@@ -189,17 +190,87 @@ void board_ft_fman_fixup_port(void *blob, char * prop, phys_addr_t pa,
 {
 	if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
 		switch (port) {
+		case FM1_DTSEC1:
+			if (qsgmiiphy_fix[port])
+				fdt_set_phy_handle(blob, prop, pa,
+						"sgmii_phy21");
+			break;
+		case FM1_DTSEC2:
+			if (qsgmiiphy_fix[port])
+				fdt_set_phy_handle(blob, prop, pa,
+						"sgmii_phy22");
+			break;
+		case FM1_DTSEC3:
+			if (qsgmiiphy_fix[port])
+				fdt_set_phy_handle(blob, prop, pa,
+						"sgmii_phy23");
+			break;
+		case FM1_DTSEC4:
+			if (qsgmiiphy_fix[port])
+				fdt_set_phy_handle(blob, prop, pa,
+						"sgmii_phy24");
+			break;
+		case FM1_DTSEC6:
+			if (qsgmiiphy_fix[port])
+				fdt_set_phy_handle(blob, prop, pa,
+						"sgmii_phy12");
+			break;
 		case FM1_DTSEC9:
-			fdt_set_phy_handle(blob, prop, pa, "phy_sgmii4");
+			if (qsgmiiphy_fix[port])
+				fdt_set_phy_handle(blob, prop, pa,
+						"sgmii_phy14");
+			else
+				fdt_set_phy_handle(blob, prop, pa,
+						"phy_sgmii4");
 			break;
 		case FM1_DTSEC10:
-			fdt_set_phy_handle(blob, prop, pa, "phy_sgmii3");
+			if (qsgmiiphy_fix[port])
+				fdt_set_phy_handle(blob, prop, pa,
+						"sgmii_phy13");
+			else
+				fdt_set_phy_handle(blob, prop, pa,
+						"phy_sgmii3");
+			break;
+		case FM2_DTSEC1:
+			if (qsgmiiphy_fix[port])
+				fdt_set_phy_handle(blob, prop, pa,
+						"sgmii_phy41");
+			break;
+		case FM2_DTSEC2:
+			if (qsgmiiphy_fix[port])
+				fdt_set_phy_handle(blob, prop, pa,
+						"sgmii_phy42");
+			break;
+		case FM2_DTSEC3:
+			if (qsgmiiphy_fix[port])
+				fdt_set_phy_handle(blob, prop, pa,
+						"sgmii_phy43");
+			break;
+		case FM2_DTSEC4:
+			if (qsgmiiphy_fix[port])
+				fdt_set_phy_handle(blob, prop, pa,
+						"sgmii_phy44");
+			break;
+		case FM2_DTSEC6:
+			if (qsgmiiphy_fix[port])
+				fdt_set_phy_handle(blob, prop, pa,
+						"sgmii_phy32");
 			break;
 		case FM2_DTSEC9:
-			fdt_set_phy_handle(blob, prop, pa, "phy_sgmii12");
+			if (qsgmiiphy_fix[port])
+				fdt_set_phy_handle(blob, prop, pa,
+						"sgmii_phy34");
+			else
+				fdt_set_phy_handle(blob, prop, pa,
+						"phy_sgmii12");
 			break;
 		case FM2_DTSEC10:
-			fdt_set_phy_handle(blob, prop, pa, "phy_sgmii11");
+			if (qsgmiiphy_fix[port])
+				fdt_set_phy_handle(blob, prop, pa,
+						"sgmii_phy33");
+			else
+				fdt_set_phy_handle(blob, prop, pa,
+						"phy_sgmii11");
 			break;
 		default:
 			break;
@@ -263,6 +334,62 @@ void fdt_fixup_board_enet(void *fdt)
 	}
 }
 
+static void initialize_qsgmiiphy_fix(void)
+{
+	int i;
+	unsigned short reg;
+
+	for (i = 1; i <= 4; i++) {
+		/*
+		 * Try to read if a SGMII card is used, we do it slot by slot.
+		 * if a SGMII PHY address is valid on a slot, then we mark
+		 * all ports on the slot, then fix the PHY address for the
+		 * marked port when doing dtb fixup.
+		 */
+		if (miiphy_read(mdio_names[i],
+			SGMII_CARD_PORT1_PHY_ADDR, MII_PHYSID2, &reg) != 0) {
+			debug("Slot%d PHY ID register 2 read failed\n", i);
+			continue;
+		}
+
+		debug("Slot%d MII_PHYSID2 @ 0x1c= 0x%04x\n", i, reg);
+
+		if (reg == 0xFFFF) {
+			/* No physical device present@this address */
+			continue;
+		}
+
+		switch (i) {
+		case 1:
+			qsgmiiphy_fix[FM1_DTSEC5] = 1;
+			qsgmiiphy_fix[FM1_DTSEC6] = 1;
+			qsgmiiphy_fix[FM1_DTSEC9] = 1;
+			qsgmiiphy_fix[FM1_DTSEC10] = 1;
+			break;
+		case 2:
+			qsgmiiphy_fix[FM1_DTSEC1] = 1;
+			qsgmiiphy_fix[FM1_DTSEC2] = 1;
+			qsgmiiphy_fix[FM1_DTSEC3] = 1;
+			qsgmiiphy_fix[FM1_DTSEC4] = 1;
+			break;
+		case 3:
+			qsgmiiphy_fix[FM2_DTSEC5] = 1;
+			qsgmiiphy_fix[FM2_DTSEC6] = 1;
+			qsgmiiphy_fix[FM2_DTSEC9] = 1;
+			qsgmiiphy_fix[FM2_DTSEC10] = 1;
+			break;
+		case 4:
+			qsgmiiphy_fix[FM2_DTSEC1] = 1;
+			qsgmiiphy_fix[FM2_DTSEC2] = 1;
+			qsgmiiphy_fix[FM2_DTSEC3] = 1;
+			qsgmiiphy_fix[FM2_DTSEC4] = 1;
+			break;
+		default:
+			break;
+		}
+	}
+}
+
 int board_eth_init(bd_t *bis)
 {
 #if defined(CONFIG_FMAN_ENET)
@@ -575,6 +702,8 @@ int board_eth_init(bd_t *bis)
 	}
 #endif /* CONFIG_SYS_NUM_FMAN */
 
+	initialize_qsgmiiphy_fix();
+
 	cpu_eth_init(bis);
 #endif /* CONFIG_FMAN_ENET */
 
-- 
1.7.9.5

[U-Boot] [PATCH 17/21] powerpc/srio: Remove duplicate macro definitions

[York Sun]

From: Liu Gang <Gang.Liu@freescale.com>

There are some duplicate SRIO macro definitions should be remove
in below header files:

	include/configs/P3041DS.h
	include/configs/P4080DS.h
	include/configs/P5020DS.h

Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
---
 include/configs/P3041DS.h |    4 ----
 include/configs/P4080DS.h |    4 ----
 include/configs/P5020DS.h |    4 ----
 3 files changed, 12 deletions(-)

diff --git a/include/configs/P3041DS.h b/include/configs/P3041DS.h
index a0a4a3c..468cc67 100644
--- a/include/configs/P3041DS.h
+++ b/include/configs/P3041DS.h
@@ -40,10 +40,6 @@
 #define CONFIG_SRIO2			/* SRIO port 2 */
 #define CONFIG_SYS_DPAA_RMAN
 
-#define CONFIG_SYS_SRIO
-#define CONFIG_SRIO1			/* SRIO port 1 */
-#define CONFIG_SRIO2			/* SRIO port 2 */
-
 #define CONFIG_ICS307_REFCLK_HZ		25000000  /* ICS307 ref clk freq */
 
 #include "corenet_ds.h"
diff --git a/include/configs/P4080DS.h b/include/configs/P4080DS.h
index 257258b..7a8373a 100644
--- a/include/configs/P4080DS.h
+++ b/include/configs/P4080DS.h
@@ -36,10 +36,6 @@
 #define CONFIG_SRIO1			/* SRIO port 1 */
 #define CONFIG_SRIO2			/* SRIO port 2 */
 
-#define CONFIG_SYS_SRIO
-#define CONFIG_SRIO1			/* SRIO port 1 */
-#define CONFIG_SRIO2			/* SRIO port 2 */
-
 #define CONFIG_ICS307_REFCLK_HZ		33333000  /* ICS307 ref clk freq */
 
 #include "corenet_ds.h"
diff --git a/include/configs/P5020DS.h b/include/configs/P5020DS.h
index a32b610..6a4bee9 100644
--- a/include/configs/P5020DS.h
+++ b/include/configs/P5020DS.h
@@ -41,10 +41,6 @@
 #define CONFIG_SYS_FSL_RAID_ENGINE
 #define CONFIG_SYS_DPAA_RMAN
 
-#define CONFIG_SYS_SRIO
-#define CONFIG_SRIO1			/* SRIO port 1 */
-#define CONFIG_SRIO2			/* SRIO port 2 */
-
 #define CONFIG_ICS307_REFCLK_HZ		25000000  /* ICS307 ref clk freq */
 
 #include "corenet_ds.h"
-- 
1.7.9.5

[U-Boot] [PATCH 18/21] powerpc/boot: Change the macro of Boot from SRIO and PCIE master module

[York Sun]

From: Liu Gang <Gang.Liu@freescale.com>

Change the macro "CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER" to
"CONFIG_SRIO_PCIE_BOOT_MASTER", remove them from
arch/powerpc/include/asm/config_mpc85xx.h file, and add those macros
in configuration header file of each board which can support the
master module of Boot from SRIO and PCIE.

Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
---
 README                                    |    3 +++
 arch/powerpc/cpu/mpc85xx/cpu_init.c       |    2 +-
 arch/powerpc/cpu/mpc8xxx/srio.c           |    4 ++--
 arch/powerpc/include/asm/config_mpc85xx.h |    4 ----
 drivers/pci/fsl_pci_init.c                |    6 +++---
 include/configs/P2041RDB.h                |    1 +
 include/configs/P3041DS.h                 |    1 +
 include/configs/P4080DS.h                 |    1 +
 include/configs/P5020DS.h                 |    1 +
 9 files changed, 13 insertions(+), 10 deletions(-)

diff --git a/README b/README
index 7f2506a..626b86f 100644
--- a/README
+++ b/README
@@ -3753,6 +3753,9 @@ Low Level (hardware related) configuration options:
 - CONFIG_SRIO2:
 		Board has SRIO 2 port available
 
+- CONFIG_SRIO_PCIE_BOOT_MASTER
+		Board can support master function for Boot from SRIO and PCIE
+
 - CONFIG_SYS_SRIOn_MEM_VIRT:
 		Virtual Address of SRIO port 'n' memory region
 
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 8b12dd2..b90c8a8 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -564,7 +564,7 @@ skip_l2:
 
 #ifdef CONFIG_SYS_SRIO
 	srio_init();
-#ifdef CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER 
+#ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
 	char *s = getenv("bootmaster");
 	if (s) {
 		if (!strcmp(s, "SRIO1")) {
diff --git a/arch/powerpc/cpu/mpc8xxx/srio.c b/arch/powerpc/cpu/mpc8xxx/srio.c
index 6e6f7dc..90d1065 100644
--- a/arch/powerpc/cpu/mpc8xxx/srio.c
+++ b/arch/powerpc/cpu/mpc8xxx/srio.c
@@ -24,7 +24,7 @@
 #include <asm/fsl_srio.h>
 #include <asm/errno.h>
 
-#ifdef CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
+#ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
 #define SRIO_PORT_ACCEPT_ALL 0x10000001
 #define SRIO_IB_ATMU_AR 0x80f55000
 #define SRIO_OB_ATMU_AR_MAINT 0x80077000
@@ -299,7 +299,7 @@ void srio_init(void)
 	}
 }
 
-#ifdef CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
+#ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
 void srio_boot_master(int port)
 {
 	struct ccsr_rio *srio = (void *)CONFIG_SYS_FSL_SRIO_ADDR;
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index 7a1cdc7..0eb828f 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -337,7 +337,6 @@
 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
-#define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS	2
 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM	9
 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM	5
@@ -370,7 +369,6 @@
 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
-#define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS	2
 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM	9
 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM	5
@@ -412,7 +410,6 @@
 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A005
 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
-#define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS	2
 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM	9
 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM	5
@@ -447,7 +444,6 @@
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
-#define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS	2
 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM	9
 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM	5
diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c
index d881375..32055d5 100644
--- a/drivers/pci/fsl_pci_init.c
+++ b/drivers/pci/fsl_pci_init.c
@@ -205,7 +205,7 @@ static int fsl_pci_setup_inbound_windows(struct pci_controller *hose,
 	return 1;
 }
 
-#ifdef CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
+#ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
 static void fsl_pcie_boot_master(pit_t *pi)
 {
 	/* configure inbound window for slave's u-boot image */
@@ -382,7 +382,7 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info)
 	/* see if we are a PCIe or PCI controller */
 	pci_hose_read_config_byte(hose, dev, FSL_PCIE_CAP_ID, &pcie_cap);
 
-#ifdef CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
+#ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
 	/* boot from PCIE --master */
 	char *s = getenv("bootmaster");
 	char pcie[6];
@@ -632,7 +632,7 @@ int fsl_pci_init_port(struct fsl_pci_info *pci_info,
 	if (fsl_is_pci_agent(hose)) {
 		fsl_pci_config_unlock(hose);
 		hose->last_busno = hose->first_busno;
-#ifdef CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
+#ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
 	} else {
 		/* boot from PCIE --master releases slave's core 0 */
 		char *s = getenv("bootmaster");
diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h
index bbc53ce..ebef17f 100644
--- a/include/configs/P2041RDB.h
+++ b/include/configs/P2041RDB.h
@@ -77,6 +77,7 @@
 #define CONFIG_SYS_SRIO
 #define CONFIG_SRIO1			/* SRIO port 1 */
 #define CONFIG_SRIO2			/* SRIO port 2 */
+#define CONFIG_SRIO_PCIE_BOOT_MASTER
 #define CONFIG_SYS_DPAA_RMAN		/* RMan */
 
 #define CONFIG_FSL_LAW			/* Use common FSL init code */
diff --git a/include/configs/P3041DS.h b/include/configs/P3041DS.h
index 468cc67..fd2fa7f 100644
--- a/include/configs/P3041DS.h
+++ b/include/configs/P3041DS.h
@@ -38,6 +38,7 @@
 #define CONFIG_SYS_SRIO
 #define CONFIG_SRIO1			/* SRIO port 1 */
 #define CONFIG_SRIO2			/* SRIO port 2 */
+#define CONFIG_SRIO_PCIE_BOOT_MASTER
 #define CONFIG_SYS_DPAA_RMAN
 
 #define CONFIG_ICS307_REFCLK_HZ		25000000  /* ICS307 ref clk freq */
diff --git a/include/configs/P4080DS.h b/include/configs/P4080DS.h
index 7a8373a..9dad61c 100644
--- a/include/configs/P4080DS.h
+++ b/include/configs/P4080DS.h
@@ -35,6 +35,7 @@
 #define CONFIG_SYS_SRIO
 #define CONFIG_SRIO1			/* SRIO port 1 */
 #define CONFIG_SRIO2			/* SRIO port 2 */
+#define CONFIG_SRIO_PCIE_BOOT_MASTER
 
 #define CONFIG_ICS307_REFCLK_HZ		33333000  /* ICS307 ref clk freq */
 
diff --git a/include/configs/P5020DS.h b/include/configs/P5020DS.h
index 6a4bee9..1e3e1d8 100644
--- a/include/configs/P5020DS.h
+++ b/include/configs/P5020DS.h
@@ -38,6 +38,7 @@
 #define CONFIG_SYS_SRIO
 #define CONFIG_SRIO1			/* SRIO port 1 */
 #define CONFIG_SRIO2			/* SRIO port 2 */
+#define CONFIG_SRIO_PCIE_BOOT_MASTER
 #define CONFIG_SYS_FSL_RAID_ENGINE
 #define CONFIG_SYS_DPAA_RMAN
 
-- 
1.7.9.5

[U-Boot] [PATCH 19/21] powerpc/b4860qds: Add the tlb entries for SRIO interfaces

[York Sun]

From: Liu Gang <Gang.Liu@freescale.com>

Add the tlb entries based on the configuration of the SRIO interfaces.
Every SRIO interface has 256M space:

	#define CONFIG_SYS_SRIO1_MEM_VIRT   0xa0000000
	#define CONFIG_SYS_SRIO1_MEM_PHYS   0xc20000000ull

	#define CONFIG_SYS_SRIO2_MEM_VIRT   0xb0000000
	#define CONFIG_SYS_SRIO2_MEM_PHYS   0xc30000000ull

Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
---
 board/freescale/b4860qds/tlb.c |   19 +++++++++++++++++--
 1 file changed, 17 insertions(+), 2 deletions(-)

diff --git a/board/freescale/b4860qds/tlb.c b/board/freescale/b4860qds/tlb.c
index 373cb78..6d634bf 100644
--- a/board/freescale/b4860qds/tlb.c
+++ b/board/freescale/b4860qds/tlb.c
@@ -111,8 +111,6 @@ struct fsl_e_tlb_entry tlb_table[] = {
 #ifdef CONFIG_SYS_NAND_BASE
 	/*
 	 * *I*G - NAND
-	 * entry 14 and 15 has been used hard coded, they will be disabled
-	 * in cpu_init_f, so we use entry 16 for nand.
 	 */
 	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
 			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
@@ -122,6 +120,23 @@ struct fsl_e_tlb_entry tlb_table[] = {
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 12, BOOKE_PAGESZ_4K, 1),
 
+	/*
+	 * *I*G - SRIO
+	 * entry 14 and 15 has been used hard coded, they will be disabled
+	 * in cpu_init_f, so we use entry 16 for SRIO2.
+	 */
+#ifdef CONFIG_SYS_SRIO1_MEM_PHYS
+	/* *I*G* - SRIO1 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_SRIO1_MEM_VIRT, CONFIG_SYS_SRIO1_MEM_PHYS,
+		MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 13, BOOKE_PAGESZ_256M, 1),
+#endif
+#ifdef CONFIG_SYS_SRIO2_MEM_PHYS
+	/* *I*G* - SRIO2 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_SRIO2_MEM_VIRT, CONFIG_SYS_SRIO2_MEM_PHYS,
+		MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 16, BOOKE_PAGESZ_256M, 1),
+#endif
 };
 
 int num_tlb_entries = ARRAY_SIZE(tlb_table);
-- 
1.7.9.5

[U-Boot] [PATCH 20/21] powerpc/b4860qds: Master module for boot from SRIO and PCIE

[York Sun]

From: Liu Gang <Gang.Liu@freescale.com>

For the powerpc processors with PCIE and SRIO interface, boot location can be
configured from one PCIE or SRIO interface by RCW. The processor booting from
PCIE or SRIO can do without flash for u-boot image. The image can be fetched
from another processor's memory space by PCIE or SRIO link connected between
them.

The processor booting from PCIE or SRIO is slave, the processor booting from
normal flash memory space is master, and it can help slave to boot from
master's memory space.

When boot from PCIE or SRIO, slave's core should be in holdoff after powered
on for some specific requirements. Master will release the slave's core at
the right time by PCIE or SRIO interface.

Environment and requirement:

master:
    1. NOR flash for its own u-boot image, ucode and ENV space.
    2. Slave's u-boot image is in master NOR flash.
    3. Normally boot from local NOR flash.
    4. Configure PCIE or SRIO system if needed.
slave:
    1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV.
    2. Boot location should be set to one PCIE or SRIO interface by RCW.
    3. RCW should configure the SerDes, PCIE or SRIO interfaces correctly.
	4. Must set all the cores in holdoff by RCW.
	5. Must be powered on before master's boot.

For the master module, need to finish these processes:
    1. Initialize the PCIE or SRIO port and address space.
    2. Set inbound PCIE or SRIO windows covered slave's u-boot image stored
	   in master's NOR flash.
	3. Set outbound windows in order to configure slave's registers
	   for the core's releasing.
    4. Should set the environment variable "bootmaster" to "PCIE1" or
	   "SRIO1", "SRIO2" using the following command:

			setenv bootmaster PCIE1 (or setenv bootmaster SRIO1)
			saveenv

Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
---
 include/configs/B4860QDS.h |    1 +
 1 file changed, 1 insertion(+)

diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h
index b09119a..81cd584 100644
--- a/include/configs/B4860QDS.h
+++ b/include/configs/B4860QDS.h
@@ -64,6 +64,7 @@
 #define CONFIG_SYS_SRIO
 #define CONFIG_SRIO1			/* SRIO port 1 */
 #define CONFIG_SRIO2			/* SRIO port 2 */
+#define CONFIG_SRIO_PCIE_BOOT_MASTER
 #endif
 
 #define CONFIG_FSL_LAW			/* Use common FSL init code */
-- 
1.7.9.5

[U-Boot] [PATCH 21/21] powerpc/b4860qds: Slave module for boot from SRIO and PCIE

[York Sun]

From: Liu Gang <Gang.Liu@freescale.com>

When boot from PCIE or SRIO, slave's core should be in holdoff after
powered on for some specific requirements. Master will release the
slave's core at the right time by PCIE or SRIO interface.

Slave's ucode and ENV can be stored in master's memory space, then slave
can fetch them through PCIE or SRIO interface.

NOTE: Because the slave can not erase, write master's NOR flash by
	  PCIE or SRIO interface, so it can not modify the ENV parameters
	  stored in master's NOR flash using "saveenv" or other commands.

environment and requirement:

master:
	1. NOR flash for its own u-boot image, ucode and ENV space.
	2. Slave's u-boot image is in master NOR flash.
	3. Put the slave's ucode and ENV into it's own memory space.
	4. Normally boot from local NOR flash.
	5. Configure PCIE or SRIO system if needed.
slave:
	1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV.
	2. Boot location should be set to one PCIE or SRIO interface by RCW.
	3. RCW should configure the SerDes, PCIE or SRIO interfaces correctly.
	4. Must set all the cores in holdoff by RCW.
	5. Must be powered on before master's boot.

For the slave module, need to finish these processes:
	1. Set the boot location to one PCIE or SRIO interface by RCW.
    2. Set a specific TLB entry for the boot process.
	3. Set a LAW entry with the TargetID of one PCIE or SRIO for the boot.
	4. Set a specific TLB entry in order to fetch ucode and ENV from
	   master.
	5. Set a LAW entry with the TargetID one of the PCIE ports for
	   ucode and ENV.
	6. Slave's u-boot image should be generated specifically by
	   make xxxx_SRIO_PCIE_BOOT_config.
	   This will set SYS_TEXT_BASE=0xFFF80000 and other configurations.

Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
---
 arch/powerpc/include/asm/immap_85xx.h |    1 +
 board/freescale/b4860qds/tlb.c        |   19 +++++++++++++++++++
 boards.cfg                            |    1 +
 include/configs/B4860QDS.h            |   32 +++++++++++++++++++++++++++-----
 4 files changed, 48 insertions(+), 5 deletions(-)

diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index c09c127..65d788a 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1844,6 +1844,7 @@ typedef struct ccsr_gur {
 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT	25
 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL	0x00ff0000
 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT	16
+#define FSL_CORENET_RCWSR6_BOOT_LOC	0x0f800000
 #endif
 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S1_PLL1	0x00800000
 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S1_PLL2	0x00400000
diff --git a/board/freescale/b4860qds/tlb.c b/board/freescale/b4860qds/tlb.c
index 6d634bf..0ea4976 100644
--- a/board/freescale/b4860qds/tlb.c
+++ b/board/freescale/b4860qds/tlb.c
@@ -52,6 +52,15 @@ struct fsl_e_tlb_entry tlb_table[] = {
 	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
 			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 			0, 0, BOOKE_PAGESZ_1M, 1),
+#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
+	/*
+	 * SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the
+	 * space is at 0xfff00000, it covered the 0xfffff000.
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR,
+			CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
+			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
+			0, 0, BOOKE_PAGESZ_1M, 1),
 #else
 	SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
@@ -137,6 +146,16 @@ struct fsl_e_tlb_entry tlb_table[] = {
 		MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 16, BOOKE_PAGESZ_256M, 1),
 #endif
+#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
+	/*
+	 * SRIO_PCIE_BOOT-SLAVE. 1M space from 0xffe00000 for
+	 * fetching ucode and ENV from master
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR,
+		CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
+		0, 17, BOOKE_PAGESZ_1M, 1),
+#endif
 };
 
 int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/boards.cfg b/boards.cfg
index 024a29e..1d44446 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -893,6 +893,7 @@ T4160QDS_SPIFLASH            powerpc     mpc85xx     t4qds               freesca
 B4860QDS                     powerpc     mpc85xx     b4860qds            freescale      -           B4860QDS:PPC_B4860
 B4860QDS_NAND		     powerpc     mpc85xx     b4860qds            freescale      -           B4860QDS:PPC_B4860,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000
 B4860QDS_SPIFLASH            powerpc     mpc85xx     b4860qds            freescale	-           B4860QDS:PPC_B4860,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000
+B4860QDS_SRIO_PCIE_BOOT	     powerpc     mpc85xx     b4860qds            freescale      -           B4860QDS:PPC_B4860,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000
 B4420QDS                     powerpc     mpc85xx     b4860qds            freescale	-	    B4860QDS:PPC_B4420
 B4420QDS_NAND		     powerpc     mpc85xx     b4860qds            freescale      -           B4860QDS:PPC_B4420,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000
 B4420QDS_SPIFLASH            powerpc     mpc85xx     b4860qds            freescale	-           B4860QDS:PPC_B4420,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000
diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h
index 81cd584..00ee5ac 100644
--- a/include/configs/B4860QDS.h
+++ b/include/configs/B4860QDS.h
@@ -34,6 +34,15 @@
 #define CONFIG_RESET_VECTOR_ADDRESS	0xfffffffc
 #endif
 
+#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
+/* Set 1M boot space */
+#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
+#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
+		(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
+#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
+#define CONFIG_SYS_NO_FLASH
+#endif
+
 /* High Level Configuration Options */
 #define CONFIG_BOOKE
 #define CONFIG_E6500
@@ -86,14 +95,15 @@
 #define CONFIG_ENV_OVERWRITE
 
 #ifdef CONFIG_SYS_NO_FLASH
+#if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL)
 #define CONFIG_ENV_IS_NOWHERE
+#endif
 #else
 #define CONFIG_FLASH_CFI_DRIVER
 #define CONFIG_SYS_FLASH_CFI
 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 #endif
 
-#ifndef CONFIG_SYS_NO_FLASH
 #if defined(CONFIG_SPIFLASH)
 #define CONFIG_SYS_EXTRA_ENV_RELOC
 #define CONFIG_ENV_IS_IN_SPI_FLASH
@@ -115,16 +125,18 @@
 #define CONFIG_ENV_IS_IN_NAND
 #define CONFIG_ENV_SIZE			CONFIG_SYS_NAND_BLOCK_SIZE
 #define CONFIG_ENV_OFFSET		(5 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
+#define CONFIG_ENV_IS_IN_REMOTE
+#define CONFIG_ENV_ADDR		0xffe20000
+#define CONFIG_ENV_SIZE		0x2000
+#elif defined(CONFIG_ENV_IS_NOWHERE)
+#define CONFIG_ENV_SIZE		0x2000
 #else
 #define CONFIG_ENV_IS_IN_FLASH
 #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 #define CONFIG_ENV_SIZE		0x2000
 #define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
 #endif
-#else /* CONFIG_SYS_NO_FLASH */
-#define CONFIG_ENV_SIZE                0x2000
-#define CONFIG_ENV_SECT_SIZE   0x20000 /* 128K (one sector) */
-#endif
 
 #ifndef __ASSEMBLY__
 unsigned long get_board_sys_clk(void);
@@ -593,6 +605,16 @@ unsigned long get_board_ddr_clk(void);
 #elif defined(CONFIG_NAND)
 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 #define CONFIG_SYS_QE_FMAN_FW_ADDR	(6 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
+/*
+ * Slave has no ucode locally, it can fetch this from remote. When implementing
+ * in two corenet boards, slave's ucode could be stored in master's memory
+ * space, the address can be mapped from slave TLB->slave LAW->
+ * slave SRIO or PCIE outbound window->master inbound window->
+ * master LAW->the ucode address in master's memory space.
+ */
+#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
+#define CONFIG_SYS_QE_FMAN_FW_ADDR	0xFFE00000
 #else
 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 #define CONFIG_SYS_QE_FMAN_FW_ADDR		0xEFF40000
-- 
1.7.9.5

[U-Boot] [PATCH 05/21] powerpc/mpc85xx: Add setting of clock-frequency for T4/B4 clockgen node

[Wolfgang Denk]

Dear York Sun,

In message <1363973052-25918-3-git-send-email-yorksun@freescale.com> you wrote:
> From: Tang Yuantian <Yuantian.Tang@freescale.com>
> 
> For T4/B4, the clockgen node compatible string is updated to version 2.
> Add clock-frequency setting for this new version.
> 
> Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
> ---
>  arch/powerpc/cpu/mpc85xx/fdt.c |    2 ++
>  1 file changed, 2 insertions(+)

CHECK: Alignment should match open parenthesis
#125: FILE: arch/powerpc/cpu/mpc85xx/fdt.c:667:
+       do_fixup_by_compat_u32(blob, "fsl,qoriq-clockgen-2",
+               "clock-frequency", CONFIG_SYS_CLK_FREQ, 1);


Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Gew?hnlich glaubt der Mensch,  wenn er nur Worte h?rt,  es m?sse sich
dabei doch auch was denken lassen.                 -- Goethe, Faust I

[U-Boot] [PATCH 07/21] net/fm: fixup ethernet for mEMAC

[Wolfgang Denk]

Dear York Sun,

In message <1363973052-25918-5-git-send-email-yorksun@freescale.com> you wrote:
> From: Shengzhou Liu <Shengzhou.Liu@freescale.com>
> 
> - set proper compatible property name for mEMAC.
> - fixed ft_fixup_port for dual-role mEMAC, which will lead to
>   MAC node disabled incorrectly.
> 
> Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
> ---
>  drivers/net/fm/fm.h   |    2 ++
>  drivers/net/fm/init.c |   24 ++++++++++++++++++++++++
>  2 files changed, 26 insertions(+)

CHECK: Logical continuations should be on the previous line
#143: FILE: drivers/net/fm/init.c:248:
+       if (((info->port == FM1_DTSEC9) && (PORT_IS_ENABLED(FM1_10GEC1)))
+           || ((info->port == FM1_DTSEC10) && (PORT_IS_ENABLED(FM1_10GEC2)))

CHECK: Logical continuations should be on the previous line
#144: FILE: drivers/net/fm/init.c:249:
+           || ((info->port == FM1_DTSEC10) && (PORT_IS_ENABLED(FM1_10GEC2)))
+           || ((info->port == FM1_10GEC1) && (PORT_IS_ENABLED(FM1_DTSEC9)))

CHECK: Logical continuations should be on the previous line
#145: FILE: drivers/net/fm/init.c:250:
+           || ((info->port == FM1_10GEC1) && (PORT_IS_ENABLED(FM1_DTSEC9)))
+           || ((info->port == FM1_10GEC2) && (PORT_IS_ENABLED(FM1_DTSEC10)))

CHECK: Logical continuations should be on the previous line
#147: FILE: drivers/net/fm/init.c:252:
+#if (CONFIG_SYS_NUM_FMAN == 2)
+           || ((info->port == FM2_DTSEC9) && (PORT_IS_ENABLED(FM2_10GEC1)))

CHECK: Logical continuations should be on the previous line
#148: FILE: drivers/net/fm/init.c:253:
+           || ((info->port == FM2_DTSEC9) && (PORT_IS_ENABLED(FM2_10GEC1)))
+           || ((info->port == FM2_DTSEC10) && (PORT_IS_ENABLED(FM2_10GEC2)))

CHECK: Logical continuations should be on the previous line
#149: FILE: drivers/net/fm/init.c:254:
+           || ((info->port == FM2_DTSEC10) && (PORT_IS_ENABLED(FM2_10GEC2)))
+           || ((info->port == FM2_10GEC1) && (PORT_IS_ENABLED(FM2_DTSEC9)))

CHECK: Logical continuations should be on the previous line
#150: FILE: drivers/net/fm/init.c:255:
+           || ((info->port == FM2_10GEC1) && (PORT_IS_ENABLED(FM2_DTSEC9)))
+           || ((info->port == FM2_10GEC2) && (PORT_IS_ENABLED(FM2_DTSEC10)))


Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
"Whoever undertakes to set himself up as a judge of Truth  and  Know-
ledge is shipwrecked by the laughter of the gods."  - Albert Einstein

[U-Boot] [PATCH 09/21] net/phy: add VSC8574 support

[Wolfgang Denk]

Dear York Sun,

In message <1363973052-25918-7-git-send-email-yorksun@freescale.com> you wrote:
> From: Shaohui Xie <Shaohui.Xie@freescale.com>
> 
> The VSC8574 is a quad-port Gigabit Ethernet transceiver with four SerDes
> interfaces for quad-port dual media capability. This driver supports SGMII
> and QSGMII MAC mode. For now SGMII mode is tested.
> 
> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
> ---
>  drivers/net/phy/vitesse.c |   67 +++++++++++++++++++++++++++++++++++++++++++++
>  include/phy.h             |    2 ++
>  2 files changed, 69 insertions(+)

CHECK: Alignment should match open parenthesis
#151: FILE: drivers/net/phy/vitesse.c:166:
+       phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS,
+                       PHY_EXT_PAGE_ACCESS_GENERAL);

CHECK: Alignment should match open parenthesis
#158: FILE: drivers/net/phy/vitesse.c:173:
+               phy_write(phydev, MDIO_DEVAD_NONE,
+                               MIIM_VSC8574_GENERAL19, val);

CHECK: Alignment should match open parenthesis
#161: FILE: drivers/net/phy/vitesse.c:176:
+               phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8574_GENERAL18,
+                               MIIM_VSC8574_18G_QSGMII);

CHECK: Alignment should match open parenthesis
#168: FILE: drivers/net/phy/vitesse.c:183:
+               phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8574_GENERAL18,
+                               MIIM_VSC8574_18G_SGMII);

CHECK: Alignment should match open parenthesis
#177: FILE: drivers/net/phy/vitesse.c:192:
+       phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS,
+                       PHY_EXT_PAGE_ACCESS_EXTENDED3);


Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
All easy problems have already been solved.

[U-Boot] [PATCH 14/21] powerpc/b4860qds: Assign DDR address in board file

[Wolfgang Denk]

Dear York Sun,

In message <1363973052-25918-12-git-send-email-yorksun@freescale.com> you wrote:
> B4860QDS requires DDRC2 has 0 as base address and DDRC1 has higher address.
> This is the requirement for DSP cores to run in 32-bit address space.
> 
> Signed-off-by: York Sun <yorksun@freescale.com>
> ---
>  board/freescale/b4860qds/ddr.c |   72 ++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 72 insertions(+)

CHECK: Alignment should match open parenthesis
#151: FILE: board/freescale/b4860qds/ddr.c:213:
+               debug("rank density is 0x%llx, ctlr density is 0x%llx\n",
+                       rank_density, ctlr_density);

WARNING: line over 80 characters
#153: FILE: board/freescale/b4860qds/ddr.c:215:
+                       switch (pinfo->memctl_opts[i].memctl_interleaving_mode) {

CHECK: Alignment should match open parenthesis
#187: FILE: board/freescale/b4860qds/ddr.c:249:
+                               debug("ctrl %d dimm %d base 0x%llx\n",
+                                       i, j, current_mem_base);


Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Work 8 hours, sleep 8 hours; but not the same 8 hours.

[U-Boot] [PATCH 16/21] T4240/eth: fix SGMII card PHY address

[Wolfgang Denk]

Dear York Sun,

In message <1363973052-25918-14-git-send-email-yorksun@freescale.com> you wrote:
> From: Shaohui Xie <Shaohui.Xie@freescale.com>
> 
> QSGMII card assumed to be used by default, but if SGMII card is used,
> it will use different PHY address, but we don't know which card is used
> until we access PHY on the card. So we check the card type slot by slot,
> if we can read a PHY ID by reading a SGMII PHY address on a slot, then
> the slot must have a SGMII card pluged, we mark all ports on that slot,
> and fix dts to use the SGMII card PHY address when doing dts fixup
> for the marked ports.
> 
> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
> ---
>  board/freescale/t4qds/eth.c |  137 +++++++++++++++++++++++++++++++++++++++++--
>  1 file changed, 133 insertions(+), 4 deletions(-)

CHECK: Alignment should match open parenthesis
#139: FILE: board/freescale/t4qds/eth.c:196:
+                               fdt_set_phy_handle(blob, prop, pa,
+                                               "sgmii_phy21");

CHECK: Alignment should match open parenthesis
#144: FILE: board/freescale/t4qds/eth.c:201:
+                               fdt_set_phy_handle(blob, prop, pa,
+                                               "sgmii_phy22");

CHECK: Alignment should match open parenthesis
#149: FILE: board/freescale/t4qds/eth.c:206:
+                               fdt_set_phy_handle(blob, prop, pa,
+                                               "sgmii_phy23");

CHECK: Alignment should match open parenthesis
#154: FILE: board/freescale/t4qds/eth.c:211:
+                               fdt_set_phy_handle(blob, prop, pa,
+                                               "sgmii_phy24");

CHECK: Alignment should match open parenthesis
#159: FILE: board/freescale/t4qds/eth.c:216:
+                               fdt_set_phy_handle(blob, prop, pa,
+                                               "sgmii_phy12");

CHECK: Alignment should match open parenthesis
#165: FILE: board/freescale/t4qds/eth.c:221:
+                               fdt_set_phy_handle(blob, prop, pa,
+                                               "sgmii_phy14");

CHECK: Alignment should match open parenthesis
#168: FILE: board/freescale/t4qds/eth.c:224:
+                               fdt_set_phy_handle(blob, prop, pa,
+                                               "phy_sgmii4");

CHECK: Alignment should match open parenthesis
#174: FILE: board/freescale/t4qds/eth.c:229:
+                               fdt_set_phy_handle(blob, prop, pa,
+                                               "sgmii_phy13");

CHECK: Alignment should match open parenthesis
#177: FILE: board/freescale/t4qds/eth.c:232:
+                               fdt_set_phy_handle(blob, prop, pa,
+                                               "phy_sgmii3");

CHECK: Alignment should match open parenthesis
#182: FILE: board/freescale/t4qds/eth.c:237:
+                               fdt_set_phy_handle(blob, prop, pa,
+                                               "sgmii_phy41");

CHECK: Alignment should match open parenthesis
#187: FILE: board/freescale/t4qds/eth.c:242:
+                               fdt_set_phy_handle(blob, prop, pa,
+                                               "sgmii_phy42");

CHECK: Alignment should match open parenthesis
#192: FILE: board/freescale/t4qds/eth.c:247:
+                               fdt_set_phy_handle(blob, prop, pa,
+                                               "sgmii_phy43");

CHECK: Alignment should match open parenthesis
#197: FILE: board/freescale/t4qds/eth.c:252:
+                               fdt_set_phy_handle(blob, prop, pa,
+                                               "sgmii_phy44");

CHECK: Alignment should match open parenthesis
#202: FILE: board/freescale/t4qds/eth.c:257:
+                               fdt_set_phy_handle(blob, prop, pa,
+                                               "sgmii_phy32");

CHECK: Alignment should match open parenthesis
#208: FILE: board/freescale/t4qds/eth.c:262:
+                               fdt_set_phy_handle(blob, prop, pa,
+                                               "sgmii_phy34");

CHECK: Alignment should match open parenthesis
#211: FILE: board/freescale/t4qds/eth.c:265:
+                               fdt_set_phy_handle(blob, prop, pa,
+                                               "phy_sgmii12");

CHECK: Alignment should match open parenthesis
#217: FILE: board/freescale/t4qds/eth.c:270:
+                               fdt_set_phy_handle(blob, prop, pa,
+                                               "sgmii_phy33");

CHECK: Alignment should match open parenthesis
#220: FILE: board/freescale/t4qds/eth.c:273:
+                               fdt_set_phy_handle(blob, prop, pa,
+                                               "phy_sgmii11");

CHECK: Alignment should match open parenthesis
#241: FILE: board/freescale/t4qds/eth.c:350:
+               if (miiphy_read(mdio_names[i],
+                       SGMII_CARD_PORT1_PHY_ADDR, MII_PHYSID2, &reg) != 0) {


Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
A witty saying proves nothing, but saying  something  pointless  gets
people's attention.

[U-Boot] [PATCH 19/21] powerpc/b4860qds: Add the tlb entries for SRIO interfaces

[Wolfgang Denk]

Dear York Sun,

In message <1363973052-25918-17-git-send-email-yorksun@freescale.com> you wrote:
> From: Liu Gang <Gang.Liu@freescale.com>
> 
> Add the tlb entries based on the configuration of the SRIO interfaces.
> Every SRIO interface has 256M space:
> 
> 	#define CONFIG_SYS_SRIO1_MEM_VIRT   0xa0000000
> 	#define CONFIG_SYS_SRIO1_MEM_PHYS   0xc20000000ull
> 
> 	#define CONFIG_SYS_SRIO2_MEM_VIRT   0xb0000000
> 	#define CONFIG_SYS_SRIO2_MEM_PHYS   0xc30000000ull
> 
> Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
> ---
>  board/freescale/b4860qds/tlb.c |   19 +++++++++++++++++--
>  1 file changed, 17 insertions(+), 2 deletions(-)

CHECK: Alignment should match open parenthesis
#147: FILE: board/freescale/b4860qds/tlb.c:131:
+       SET_TLB_ENTRY(1, CONFIG_SYS_SRIO1_MEM_VIRT, CONFIG_SYS_SRIO1_MEM_PHYS,
+               MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,

CHECK: Alignment should match open parenthesis
#153: FILE: board/freescale/b4860qds/tlb.c:137:
+       SET_TLB_ENTRY(1, CONFIG_SYS_SRIO2_MEM_VIRT, CONFIG_SYS_SRIO2_MEM_PHYS,
+               MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,


Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
In theory, there is no difference between  theory  and  practice.  In
practice, however, there is.

[U-Boot] [PATCH 21/21] powerpc/b4860qds: Slave module for boot from SRIO and PCIE

[Wolfgang Denk]

Dear York Sun,

In message <1363973052-25918-19-git-send-email-yorksun@freescale.com> you wrote:
> From: Liu Gang <Gang.Liu@freescale.com>
> 
> When boot from PCIE or SRIO, slave's core should be in holdoff after
> powered on for some specific requirements. Master will release the
> slave's core at the right time by PCIE or SRIO interface.
> 
> Slave's ucode and ENV can be stored in master's memory space, then slave
> can fetch them through PCIE or SRIO interface.
...

CHECK: Alignment should match open parenthesis
#180: FILE: board/freescale/b4860qds/tlb.c:61:
+       SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR,
+                       CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,

CHECK: Alignment should match open parenthesis
#196: FILE: board/freescale/b4860qds/tlb.c:155:
+       SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR,
+               CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,


Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
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someone who is busy.               - Terry Pratchett, _Going_Postal_

[U-Boot] [PATCH 03/21] fsl_ifc: add support for different IFC bank count

[Andy Fleming]

On Fri, Mar 22, 2013 at 12:23 PM, York Sun <yorksun@freescale.com> wrote:

> From: Mingkai Hu <Mingkai.hu@freescale.com>
>
> Calculate reserved fields according to IFC bank count
>
> 1. Move csor_ext register behind csor register and fix res offset
> 2. move ifc bank count to config_mpc85xx.h to support 8 bank count
>
> There's no IFC controller instead of eLBC controller on some platforms,
> such as MPC8536, P2041, P3041, P4080 etc, so there's no macro definition
> for the number of IFC chip select(CONFIG_SYS_FSL_IFC_BANK_COUNT) which
> is used in the IFC controller header file fsl_ifc.h on these platforms.
>


This paragraph is pretty confusing. Is this just explaining that
IFC_BANK_COUNT isn't being defined for devices that don't use IFC? Or is it
explaining why you have to guard fsl_ifc.h with a #ifdef?



>
> Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
> ---
>  arch/powerpc/cpu/mpc85xx/cpu.c            |    2 +-
>  arch/powerpc/cpu/mpc8xxx/fsl_ifc.c        |   58
> ++++++++++++++++++++++++++++-
>  arch/powerpc/include/asm/config_mpc85xx.h |    7 ++++
>  arch/powerpc/include/asm/fsl_ifc.h        |   42 +++++++++++++++------
>  4 files changed, 96 insertions(+), 13 deletions(-)
>
> diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c
> b/arch/powerpc/cpu/mpc85xx/cpu.c
> index df2ab6d..379a7df 100644
> --- a/arch/powerpc/cpu/mpc85xx/cpu.c
> +++ b/arch/powerpc/cpu/mpc85xx/cpu.c
> @@ -34,8 +34,8 @@
>  #include <asm/io.h>
>  #include <asm/mmu.h>
>  #include <asm/fsl_ifc.h>
> -#include <asm/fsl_law.h>
>  #include <asm/fsl_lbc.h>
> +#include <asm/fsl_law.h>
>  #include <post.h>
>  #include <asm/processor.h>
>  #include <asm/fsl_ddr_sdram.h>
> diff --git a/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c
> b/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c
> index 56b319f..f0da355 100644
> --- a/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c
> +++ b/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c
> @@ -26,7 +26,7 @@ void print_ifc_regs(void)
>         int i, j;
>
>         printf("IFC Controller Registers\n");
> -       for (i = 0; i < FSL_IFC_BANK_COUNT; i++) {
> +       for (i = 0; i < CONFIG_SYS_FSL_IFC_BANK_COUNT; i++) {
>                 printf("CSPR%d:0x%08X\tAMASK%d:0x%08X\tCSOR%d:0x%08X\n",
>                         i, get_ifc_cspr(i), i, get_ifc_amask(i),
>                         i, get_ifc_csor(i));
> @@ -94,4 +94,60 @@ void init_early_memctl_regs(void)
>         set_ifc_amask(IFC_CS3, CONFIG_SYS_AMASK3);
>         set_ifc_csor(IFC_CS3, CONFIG_SYS_CSOR3);
>  #endif
> +
> +#ifdef CONFIG_SYS_CSPR4_EXT
> +       set_ifc_cspr_ext(IFC_CS4, CONFIG_SYS_CSPR4_EXT);
> +#endif
> +#if defined(CONFIG_SYS_CSPR4) && defined(CONFIG_SYS_CSOR4)
>


There seem to be a large number of CONFIG options associated with each and
every new bank. It's following the pattern of the existing code, so I'll
accept it, but I can't help but think that some of these config options are
entirely redundant (would we ever have CSPR4, and *not* CSOR4?). This is,
admittedly, based only on a high-level view of the code -- I'm not familiar
with the specifics of the IFC design.

[...]


diff --git a/arch/powerpc/include/asm/fsl_ifc.h
b/arch/powerpc/include/asm/fsl_ifc.h
index ba41b73..debcb6b 100644
--- a/arch/powerpc/include/asm/fsl_ifc.h
+++ b/arch/powerpc/include/asm/fsl_ifc.h
@@ -21,6 +21,7 @@
 #ifndef __ASM_PPC_FSL_IFC_H
 #define __ASM_PPC_FSL_IFC_H

+#ifdef CONFIG_FSL_IFC
 #include <config.h>
 #include <common.h>


[...]

@@ -907,6 +910,22 @@ struct fsl_ifc_gpcm {
        u32 res4[0x1F3];
 };

+#ifdef CONFIG_SYS_FSL_IFC_BANK_COUNT
+#if (CONFIG_SYS_FSL_IFC_BANK_COUNT <= 8)
+#define CONFIG_SYS_FSL_IFC_CSPR_RES \
+       (0x25 - CONFIG_SYS_FSL_IFC_BANK_COUNT * 3)
+#define CONFIG_SYS_FSL_IFC_AMASK_RES \
+       (0x24 - CONFIG_SYS_FSL_IFC_BANK_COUNT * 3)
+#define CONFIG_SYS_FSL_IFC_CSOR_RES \
+       (0x24 - CONFIG_SYS_FSL_IFC_BANK_COUNT * 3)
+#define CONFIG_SYS_FSL_IFC_FTIM_RES \
+       (0x90 - CONFIG_SYS_FSL_IFC_BANK_COUNT * 0xc)


These aren't really config values. They are values derived from a CONFIG
value, and they only have local scope (so there's no need for the very
global scoping of the names).

Also... Are these correct? 0x25 is a strange amount of gap in register
space.

All that aside, I think we should just define the register offsets to cover
all existing (or even predicted) registers, and make the gap hard-coded as
before. There's no real advantage to specifying only as many as are
implemented, and this method seems ripe for potential bugs in the future.


+#else
+#error IFC BANK count not vaild
+#endif
+#else
+#error IFC BANK count not defined
+#endif

 /*
  * IFC Controller Registers
@@ -918,24 +937,24 @@ struct fsl_ifc {
                u32 cspr_ext;
                u32 cspr;
                u32 res2;
-       } cspr_cs[FSL_IFC_BANK_COUNT];
-       u32 res3[0x19];
+       } cspr_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT];
+       u32 res3[CONFIG_SYS_FSL_IFC_CSPR_RES];
        struct {
                u32 amask;
                u32 res4[0x2];
-       } amask_cs[FSL_IFC_BANK_COUNT];
-       u32 res5[0x17];
+       } amask_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT];
+       u32 res5[CONFIG_SYS_FSL_IFC_AMASK_RES];
        struct {
-               u32 csor_ext;
                u32 csor;
+               u32 csor_ext;
                u32 res6;
-       } csor_cs[FSL_IFC_BANK_COUNT];
-       u32 res7[0x19];
+       } csor_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT];
+       u32 res7[CONFIG_SYS_FSL_IFC_CSOR_RES];
        struct {
                u32 ftim[4];
                u32 res8[0x8];
-       } ftim_cs[FSL_IFC_BANK_COUNT];
-       u32 res9[0x60];
+       } ftim_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT];
+       u32 res9[CONFIG_SYS_FSL_IFC_FTIM_RES];
        u32 rb_stat;
        u32 res10[0x2];
        u32 ifc_gcr;
@@ -961,6 +980,7 @@ struct fsl_ifc {
 #undef CSPR_MSEL_NOR
 #define CSPR_MSEL_NOR  CSPR_MSEL_GPCM
 #endif
+#endif /* CONFIG_FSL_IFC */

 #endif /* __ASSEMBLY__ */
 #endif /* __ASM_PPC_FSL_IFC_H */
--
1.7.9.5


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[U-Boot] [PATCH 03/21] fsl_ifc: add support for different IFC bank count

[Hu Mingkai-B21284]

Hi Andy,

Please find my replies in line.

Thanks,
Mingkai

From: Andy Fleming [mailto:afleming at gmail.com]
Sent: Saturday, May 11, 2013 5:49 AM
To: sun york-R58495; Hu Mingkai-B21284
Cc: Fleming Andy-AFLEMING; U-Boot list
Subject: Re: [U-Boot] [PATCH 03/21] fsl_ifc: add support for different IFC bank count



On Fri, Mar 22, 2013 at 12:23 PM, York Sun <yorksun at freescale.com<mailto:yorksun@freescale.com>> wrote:
From: Mingkai Hu <Mingkai.hu at freescale.com<mailto:Mingkai.hu@freescale.com>>

Calculate reserved fields according to IFC bank count

1. Move csor_ext register behind csor register and fix res offset
2. move ifc bank count to config_mpc85xx.h to support 8 bank count

There's no IFC controller instead of eLBC controller on some platforms,
such as MPC8536, P2041, P3041, P4080 etc, so there's no macro definition
for the number of IFC chip select(CONFIG_SYS_FSL_IFC_BANK_COUNT) which
is used in the IFC controller header file fsl_ifc.h on these platforms.


This paragraph is pretty confusing. Is this just explaining that IFC_BANK_COUNT isn't being defined for devices that don't use IFC? Or is it explaining why you have to guard fsl_ifc.h with a #ifdef?
[Mingkai] Both. Some devices doesn't use IFC, thus, there's no IFC_BANK_COUNT for these devices. While some common files include fsl_ifc.h, which needs IFC_BANK_COUNT definition, that's the reason why I have to guard fsl_ifc.h. I will change it to the following:

3. Guard fsl_ifc.h with CONFIG_FSL_IFC to eliminate the compile error on some devices that doesn't have IFC controller.


Signed-off-by: Mingkai Hu <Mingkai.hu at freescale.com<mailto:Mingkai.hu@freescale.com>>
---
 arch/powerpc/cpu/mpc85xx/cpu.c            |    2 +-
 arch/powerpc/cpu/mpc8xxx/fsl_ifc.c        |   58 ++++++++++++++++++++++++++++-
 arch/powerpc/include/asm/config_mpc85xx.h |    7 ++++
 arch/powerpc/include/asm/fsl_ifc.h        |   42 +++++++++++++++------
 4 files changed, 96 insertions(+), 13 deletions(-)

diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index df2ab6d..379a7df 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -34,8 +34,8 @@
 #include <asm/io.h>
 #include <asm/mmu.h>
 #include <asm/fsl_ifc.h>
-#include <asm/fsl_law.h>
 #include <asm/fsl_lbc.h>
+#include <asm/fsl_law.h>
 #include <post.h>
 #include <asm/processor.h>
 #include <asm/fsl_ddr_sdram.h>
diff --git a/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c b/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c
index 56b319f..f0da355 100644
--- a/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c
+++ b/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c
@@ -26,7 +26,7 @@ void print_ifc_regs(void)
        int i, j;

        printf("IFC Controller Registers\n");
-       for (i = 0; i < FSL_IFC_BANK_COUNT; i++) {
+       for (i = 0; i < CONFIG_SYS_FSL_IFC_BANK_COUNT; i++) {
                printf("CSPR%d:0x%08X\tAMASK%d:0x%08X\tCSOR%d:0x%08X\n",
                        i, get_ifc_cspr(i), i, get_ifc_amask(i),
                        i, get_ifc_csor(i));
@@ -94,4 +94,60 @@ void init_early_memctl_regs(void)
        set_ifc_amask(IFC_CS3, CONFIG_SYS_AMASK3);
        set_ifc_csor(IFC_CS3, CONFIG_SYS_CSOR3);
 #endif
+
+#ifdef CONFIG_SYS_CSPR4_EXT
+       set_ifc_cspr_ext(IFC_CS4, CONFIG_SYS_CSPR4_EXT);
+#endif
+#if defined(CONFIG_SYS_CSPR4) && defined(CONFIG_SYS_CSOR4)


There seem to be a large number of CONFIG options associated with each and every new bank. It's following the pattern of the existing code, so I'll accept it, but I can't help but think that some of these config options are entirely redundant (would we ever have CSPR4, and *not* CSOR4?). This is, admittedly, based only on a high-level view of the code -- I'm not familiar with the specifics of the IFC design.

[...]

[Mingkai] These codes are redundant, we can factor this out in another separate patch.
Prabhakar, what would you say here?

diff --git a/arch/powerpc/include/asm/fsl_ifc.h b/arch/powerpc/include/asm/fsl_ifc.h
index ba41b73..debcb6b 100644
--- a/arch/powerpc/include/asm/fsl_ifc.h
+++ b/arch/powerpc/include/asm/fsl_ifc.h
@@ -21,6 +21,7 @@
 #ifndef __ASM_PPC_FSL_IFC_H
 #define __ASM_PPC_FSL_IFC_H

+#ifdef CONFIG_FSL_IFC
 #include <config.h>
 #include <common.h>

[...]

@@ -907,6 +910,22 @@ struct fsl_ifc_gpcm {
        u32 res4[0x1F3];
 };

+#ifdef CONFIG_SYS_FSL_IFC_BANK_COUNT
+#if (CONFIG_SYS_FSL_IFC_BANK_COUNT <= 8)
+#define CONFIG_SYS_FSL_IFC_CSPR_RES \
+       (0x25 - CONFIG_SYS_FSL_IFC_BANK_COUNT * 3)
+#define CONFIG_SYS_FSL_IFC_AMASK_RES \
+       (0x24 - CONFIG_SYS_FSL_IFC_BANK_COUNT * 3)
+#define CONFIG_SYS_FSL_IFC_CSOR_RES \
+       (0x24 - CONFIG_SYS_FSL_IFC_BANK_COUNT * 3)
+#define CONFIG_SYS_FSL_IFC_FTIM_RES \
+       (0x90 - CONFIG_SYS_FSL_IFC_BANK_COUNT * 0xc)


These aren't really config values. They are values derived from a CONFIG value, and they only have local scope (so there's no need for the very global scoping of the names).

Also... Are these correct? 0x25 is a strange amount of gap in register space.
[Mingkai]They're correct. I've test it on T4, C293QDS and P1010RDB platform when I submitted this patch.
The value 0x25 is caused by the fact that the 0x25 is represents the length of cspr (148 bytes) in unit 4 bytes.
Here is the magic math: 148 / 4 = 37 = 0x25

All that aside, I think we should just define the register offsets to cover all existing (or even predicted) registers, and make the gap hard-coded as before. There's no real advantage to specifying only as many as are implemented, and this method seems ripe for potential bugs in the future.

[Mingkai] I modified the code as follows,

First define the different register space length in bytes as follows:

#define IFC_CSPR_REG_LEN        148
#define IFC_AMASK_REG_LEN       140
#define IFC_CSOR_REG_LEN        140
#define IFC_FTIM_REG_LEN        576

Then in the struct, use the register space length minus the actual used space and get the reserved space as the red line indicates.

struct fsl_ifc {
        u32 ifc_rev;
        u32 res1[0x2];
        struct {
                u32 cspr_ext;
                u32 cspr;
                u32 res2;
        } cspr_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT];
        u32 res3[IFC_CSPR_REG_LEN - sizeof(cspr_cs)];
        struct {
                u32 amask;
                u32 res4[0x2];
        } amask_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT];
        u32 res5[IFC_AMASK_REG_LEN - sizeof(amask_cs)];
        struct {
                u32 csor;
                u32 csor_ext;
                u32 res6;
        } csor_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT];
        u32 res7[IFC_CSOR_REG_LEN - sizeof(csor_cs)];
        struct {
                u32 ftim[4];
                u32 res8[0x8];
        } ftim_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT];
        u32 res9[IFC_FTIM_REG_LEN - sizeof(ftim_cs)];
}

BTW, the patch can't be applied to your mpc85xx public tree cleanly, so if you think this modification is ok, I will submit a new patch based on the latest git tree base.

Thanks,
Mingkai

+#else
+#error IFC BANK count not vaild
+#endif
+#else
+#error IFC BANK count not defined
+#endif

 /*
  * IFC Controller Registers
@@ -918,24 +937,24 @@ struct fsl_ifc {
                u32 cspr_ext;
                u32 cspr;
                u32 res2;
-       } cspr_cs[FSL_IFC_BANK_COUNT];
-       u32 res3[0x19];
+       } cspr_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT];
+       u32 res3[CONFIG_SYS_FSL_IFC_CSPR_RES];
        struct {
                u32 amask;
                u32 res4[0x2];
-       } amask_cs[FSL_IFC_BANK_COUNT];
-       u32 res5[0x17];
+       } amask_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT];
+       u32 res5[CONFIG_SYS_FSL_IFC_AMASK_RES];
        struct {
-               u32 csor_ext;
                u32 csor;
+               u32 csor_ext;
                u32 res6;
-       } csor_cs[FSL_IFC_BANK_COUNT];
-       u32 res7[0x19];
+       } csor_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT];
+       u32 res7[CONFIG_SYS_FSL_IFC_CSOR_RES];
        struct {
                u32 ftim[4];
                u32 res8[0x8];
-       } ftim_cs[FSL_IFC_BANK_COUNT];
-       u32 res9[0x60];
+       } ftim_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT];
+       u32 res9[CONFIG_SYS_FSL_IFC_FTIM_RES];
        u32 rb_stat;
        u32 res10[0x2];
        u32 ifc_gcr;
@@ -961,6 +980,7 @@ struct fsl_ifc {
 #undef CSPR_MSEL_NOR
 #define CSPR_MSEL_NOR  CSPR_MSEL_GPCM
 #endif
+#endif /* CONFIG_FSL_IFC */

 #endif /* __ASSEMBLY__ */
 #endif /* __ASM_PPC_FSL_IFC_H */
--
1.7.9.5


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[U-Boot] [PATCH 03/21] fsl_ifc: add support for different IFC bank count

[Fleming Andy-AFLEMING]

On May 14, 2013, at 3:59, "Hu Mingkai-B21284" <B21284 at freescale.com<mailto:B21284@freescale.com>> wrote:

Hi Andy,

Please find my replies in line.

Thanks,
Mingkai


There's no IFC controller instead of eLBC controller on some platforms,
such as MPC8536, P2041, P3041, P4080 etc, so there's no macro definition
for the number of IFC chip select(CONFIG_SYS_FSL_IFC_BANK_COUNT) which
is used in the IFC controller header file fsl_ifc.h on these platforms.


This paragraph is pretty confusing. Is this just explaining that IFC_BANK_COUNT isn't being defined for devices that don't use IFC? Or is it explaining why you have to guard fsl_ifc.h with a #ifdef?
[Mingkai] Both. Some devices doesn?t use IFC, thus, there?s no IFC_BANK_COUNT for these devices. While some common files include fsl_ifc.h, which needs IFC_BANK_COUNT definition, that?s the reason why I have to guard fsl_ifc.h. I will change it to the following:

3. Guard fsl_ifc.h with CONFIG_FSL_IFC to eliminate the compile error on some devices that doesn?t have IFC controller.


That's good, thanks


diff --git a/arch/powerpc/include/asm/fsl_ifc.h b/arch/powerpc/include/asm/fsl_ifc.h
index ba41b73..debcb6b 100644
--- a/arch/powerpc/include/asm/fsl_ifc.h
+++ b/arch/powerpc/include/asm/fsl_ifc.h
@@ -21,6 +21,7 @@
 #ifndef __ASM_PPC_FSL_IFC_H
 #define __ASM_PPC_FSL_IFC_H

+#ifdef CONFIG_FSL_IFC
 #include <config.h>
 #include <common.h>

[...]

@@ -907,6 +910,22 @@ struct fsl_ifc_gpcm {
        u32 res4[0x1F3];
 };

+#ifdef CONFIG_SYS_FSL_IFC_BANK_COUNT
+#if (CONFIG_SYS_FSL_IFC_BANK_COUNT <= 8)
+#define CONFIG_SYS_FSL_IFC_CSPR_RES \
+       (0x25 - CONFIG_SYS_FSL_IFC_BANK_COUNT * 3)
+#define CONFIG_SYS_FSL_IFC_AMASK_RES \
+       (0x24 - CONFIG_SYS_FSL_IFC_BANK_COUNT * 3)
+#define CONFIG_SYS_FSL_IFC_CSOR_RES \
+       (0x24 - CONFIG_SYS_FSL_IFC_BANK_COUNT * 3)
+#define CONFIG_SYS_FSL_IFC_FTIM_RES \
+       (0x90 - CONFIG_SYS_FSL_IFC_BANK_COUNT * 0xc)


These aren't really config values. They are values derived from a CONFIG value, and they only have local scope (so there's no need for the very global scoping of the names).

Also... Are these correct? 0x25 is a strange amount of gap in register space.
[Mingkai]They?re correct. I?ve test it on T4, C293QDS and P1010RDB platform when I submitted this patch.
The value 0x25 is caused by the fact that the 0x25 is represents the length of cspr (148 bytes) in unit 4 bytes.
Here is the magic math: 148 / 4 = 37 = 0x25

All that aside, I think we should just define the register offsets to cover all existing (or even predicted) registers, and make the gap hard-coded as before. There's no real advantage to specifying only as many as are implemented, and this method seems ripe for potential bugs in the future.

[Mingkai] I modified the code as follows,

First define the different register space length in bytes as follows:

#define IFC_CSPR_REG_LEN        148
#define IFC_AMASK_REG_LEN       140
#define IFC_CSOR_REG_LEN        140
#define IFC_FTIM_REG_LEN        576

Then in the struct, use the register space length minus the actual used space and get the reserved space as the red line indicates.

struct fsl_ifc {
        u32 ifc_rev;
        u32 res1[0x2];
        struct {
                u32 cspr_ext;
                u32 cspr;
                u32 res2;
        } cspr_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT];
        u32 res3[IFC_CSPR_REG_LEN - sizeof(cspr_cs)];


That's a bit clearer. However, it needs to be u8 if you are going to specify bytes.


        struct {
                u32 amask;
                u32 res4[0x2];
        } amask_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT];
        u32 res5[IFC_AMASK_REG_LEN - sizeof(amask_cs)];
        struct {
                u32 csor;
                u32 csor_ext;
                u32 res6;
        } csor_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT];
        u32 res7[IFC_CSOR_REG_LEN - sizeof(csor_cs)];
        struct {
                u32 ftim[4];
                u32 res8[0x8];
        } ftim_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT];
        u32 res9[IFC_FTIM_REG_LEN - sizeof(ftim_cs)];
}

BTW, the patch can?t be applied to your mpc85xx public tree cleanly, so if you think this modification is ok, I will submit a new patch based on the latest git tree base.

Ok, thanks!

Andy