From: York Sun <yorksun@freescale.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 10/21] T4240/net: use QSGMII card PHY address by default
Date: Fri, 22 Mar 2013 10:24:01 -0700 [thread overview]
Message-ID: <1363973052-25918-8-git-send-email-yorksun@freescale.com> (raw)
In-Reply-To: <1363973052-25918-1-git-send-email-yorksun@freescale.com>
From: Shaohui Xie <Shaohui.Xie@freescale.com>
Use QSGMII card PHY address as default SGMII card PHY address, QSGMII card
PHY address is variable depends on different slot.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
---
board/freescale/t4qds/eth.c | 123 +++++++++++++++++++++++--------------------
include/configs/t4qds.h | 1 -
2 files changed, 67 insertions(+), 57 deletions(-)
diff --git a/board/freescale/t4qds/eth.c b/board/freescale/t4qds/eth.c
index 8d2c33f..2232eea 100644
--- a/board/freescale/t4qds/eth.c
+++ b/board/freescale/t4qds/eth.c
@@ -71,6 +71,13 @@ static const char *mdio_names[] = {
static u8 lane_to_slot_fsm1[] = {1, 1, 1, 1, 2, 2, 2, 2};
static u8 lane_to_slot_fsm2[] = {3, 3, 3, 3, 4, 4, 4, 4};
+static u8 slot_qsgmii_phyaddr[5][4] = {
+ {0, 0, 0, 0},/* not used, to make index match slot No. */
+ {0, 1, 2, 3},
+ {4, 5, 6, 7},
+ {8, 9, 0xa, 0xb},
+ {0xc, 0xd, 0xe, 0xf},
+};
static const char *t4240qds_mdio_name_for_muxval(u8 muxval)
{
@@ -313,44 +320,48 @@ int board_eth_init(bd_t *bis)
case 28:
case 36:
/* SGMII in Slot1 and Slot2 */
- fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT2_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_PORT3_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC4, SGMII_CARD_PORT4_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC1, slot_qsgmii_phyaddr[2][0]);
+ fm_info_set_phy_address(FM1_DTSEC2, slot_qsgmii_phyaddr[2][1]);
+ fm_info_set_phy_address(FM1_DTSEC3, slot_qsgmii_phyaddr[2][2]);
+ fm_info_set_phy_address(FM1_DTSEC4, slot_qsgmii_phyaddr[2][3]);
+ fm_info_set_phy_address(FM1_DTSEC5, slot_qsgmii_phyaddr[1][0]);
+ fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]);
if ((srds_prtcl_s2 != 56) && (srds_prtcl_s2 != 57)) {
fm_info_set_phy_address(FM1_DTSEC9,
- SGMII_CARD_PORT4_PHY_ADDR);
+ slot_qsgmii_phyaddr[1][3]);
fm_info_set_phy_address(FM1_DTSEC10,
- SGMII_CARD_PORT3_PHY_ADDR);
+ slot_qsgmii_phyaddr[1][2]);
}
break;
case 38:
- fm_info_set_phy_address(FM1_DTSEC5, QSGMII_CARD_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC6, QSGMII_CARD_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC1, slot_qsgmii_phyaddr[2][0]);
+ fm_info_set_phy_address(FM1_DTSEC2, slot_qsgmii_phyaddr[2][1]);
+ fm_info_set_phy_address(FM1_DTSEC3, slot_qsgmii_phyaddr[2][2]);
+ fm_info_set_phy_address(FM1_DTSEC4, slot_qsgmii_phyaddr[2][3]);
+ fm_info_set_phy_address(FM1_DTSEC5, slot_qsgmii_phyaddr[1][0]);
+ fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]);
if ((srds_prtcl_s2 != 56) && (srds_prtcl_s2 != 57)) {
fm_info_set_phy_address(FM1_DTSEC9,
- QSGMII_CARD_PHY_ADDR);
+ slot_qsgmii_phyaddr[1][3]);
fm_info_set_phy_address(FM1_DTSEC10,
- QSGMII_CARD_PHY_ADDR);
+ slot_qsgmii_phyaddr[1][2]);
}
break;
case 40:
case 46:
case 48:
- fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC5, slot_qsgmii_phyaddr[1][0]);
+ fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]);
if ((srds_prtcl_s2 != 56) && (srds_prtcl_s2 != 57)) {
fm_info_set_phy_address(FM1_DTSEC10,
- SGMII_CARD_PORT3_PHY_ADDR);
+ slot_qsgmii_phyaddr[1][3]);
fm_info_set_phy_address(FM1_DTSEC9,
- SGMII_CARD_PORT4_PHY_ADDR);
+ slot_qsgmii_phyaddr[1][2]);
}
- fm_info_set_phy_address(FM1_DTSEC1, QSGMII_CARD_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC2, QSGMII_CARD_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC3, QSGMII_CARD_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC4, QSGMII_CARD_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC1, slot_qsgmii_phyaddr[2][0]);
+ fm_info_set_phy_address(FM1_DTSEC2, slot_qsgmii_phyaddr[2][1]);
+ fm_info_set_phy_address(FM1_DTSEC3, slot_qsgmii_phyaddr[2][2]);
+ fm_info_set_phy_address(FM1_DTSEC4, slot_qsgmii_phyaddr[2][3]);
break;
default:
puts("Invalid SerDes1 protocol for T4240QDS\n");
@@ -436,64 +447,64 @@ int board_eth_init(bd_t *bis)
case 26:
/* XAUI/HiGig in Slot3, SGMII in Slot4 */
fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR);
- fm_info_set_phy_address(FM2_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
- fm_info_set_phy_address(FM2_DTSEC2, SGMII_CARD_PORT2_PHY_ADDR);
- fm_info_set_phy_address(FM2_DTSEC3, SGMII_CARD_PORT3_PHY_ADDR);
- fm_info_set_phy_address(FM2_DTSEC4, SGMII_CARD_PORT4_PHY_ADDR);
+ fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
+ fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
+ fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
+ fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
break;
case 28:
case 36:
/* SGMII in Slot3 and Slot4 */
- fm_info_set_phy_address(FM2_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
- fm_info_set_phy_address(FM2_DTSEC2, SGMII_CARD_PORT2_PHY_ADDR);
- fm_info_set_phy_address(FM2_DTSEC3, SGMII_CARD_PORT3_PHY_ADDR);
- fm_info_set_phy_address(FM2_DTSEC4, SGMII_CARD_PORT4_PHY_ADDR);
- fm_info_set_phy_address(FM2_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR);
- fm_info_set_phy_address(FM2_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
- fm_info_set_phy_address(FM2_DTSEC9, SGMII_CARD_PORT4_PHY_ADDR);
- fm_info_set_phy_address(FM2_DTSEC10, SGMII_CARD_PORT3_PHY_ADDR);
+ fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
+ fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
+ fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
+ fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
+ fm_info_set_phy_address(FM2_DTSEC5, slot_qsgmii_phyaddr[3][0]);
+ fm_info_set_phy_address(FM2_DTSEC6, slot_qsgmii_phyaddr[3][1]);
+ fm_info_set_phy_address(FM2_DTSEC9, slot_qsgmii_phyaddr[3][3]);
+ fm_info_set_phy_address(FM2_DTSEC10, slot_qsgmii_phyaddr[3][2]);
break;
case 38:
/* QSGMII in Slot3 and Slot4 */
- fm_info_set_phy_address(FM2_DTSEC1, QSGMII_CARD_PHY_ADDR);
- fm_info_set_phy_address(FM2_DTSEC2, QSGMII_CARD_PHY_ADDR);
- fm_info_set_phy_address(FM2_DTSEC3, QSGMII_CARD_PHY_ADDR);
- fm_info_set_phy_address(FM2_DTSEC4, QSGMII_CARD_PHY_ADDR);
- fm_info_set_phy_address(FM2_DTSEC5, QSGMII_CARD_PHY_ADDR);
- fm_info_set_phy_address(FM2_DTSEC6, QSGMII_CARD_PHY_ADDR);
- fm_info_set_phy_address(FM2_DTSEC9, QSGMII_CARD_PHY_ADDR);
- fm_info_set_phy_address(FM2_DTSEC10, QSGMII_CARD_PHY_ADDR);
+ fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
+ fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
+ fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
+ fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
+ fm_info_set_phy_address(FM2_DTSEC5, slot_qsgmii_phyaddr[3][0]);
+ fm_info_set_phy_address(FM2_DTSEC6, slot_qsgmii_phyaddr[3][1]);
+ fm_info_set_phy_address(FM2_DTSEC9, slot_qsgmii_phyaddr[3][3]);
+ fm_info_set_phy_address(FM2_DTSEC10, slot_qsgmii_phyaddr[3][2]);
break;
case 40:
case 46:
case 48:
/* SGMII in Slot3 */
- fm_info_set_phy_address(FM2_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR);
- fm_info_set_phy_address(FM2_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
- fm_info_set_phy_address(FM2_DTSEC9, SGMII_CARD_PORT4_PHY_ADDR);
- fm_info_set_phy_address(FM2_DTSEC10, SGMII_CARD_PORT3_PHY_ADDR);
+ fm_info_set_phy_address(FM2_DTSEC5, slot_qsgmii_phyaddr[3][0]);
+ fm_info_set_phy_address(FM2_DTSEC6, slot_qsgmii_phyaddr[3][1]);
+ fm_info_set_phy_address(FM2_DTSEC9, slot_qsgmii_phyaddr[3][3]);
+ fm_info_set_phy_address(FM2_DTSEC10, slot_qsgmii_phyaddr[3][2]);
/* QSGMII in Slot4 */
- fm_info_set_phy_address(FM2_DTSEC1, QSGMII_CARD_PHY_ADDR);
- fm_info_set_phy_address(FM2_DTSEC2, QSGMII_CARD_PHY_ADDR);
- fm_info_set_phy_address(FM2_DTSEC3, QSGMII_CARD_PHY_ADDR);
- fm_info_set_phy_address(FM2_DTSEC4, QSGMII_CARD_PHY_ADDR);
+ fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
+ fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
+ fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
+ fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
break;
case 50:
case 52:
case 54:
fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR);
- fm_info_set_phy_address(FM2_DTSEC1, QSGMII_CARD_PHY_ADDR);
- fm_info_set_phy_address(FM2_DTSEC2, QSGMII_CARD_PHY_ADDR);
- fm_info_set_phy_address(FM2_DTSEC3, QSGMII_CARD_PHY_ADDR);
- fm_info_set_phy_address(FM2_DTSEC4, QSGMII_CARD_PHY_ADDR);
+ fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
+ fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
+ fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
+ fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
break;
case 56:
case 57:
/* XFI in Slot3, SGMII in Slot4 */
- fm_info_set_phy_address(FM2_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
- fm_info_set_phy_address(FM2_DTSEC2, SGMII_CARD_PORT2_PHY_ADDR);
- fm_info_set_phy_address(FM2_DTSEC3, SGMII_CARD_PORT3_PHY_ADDR);
- fm_info_set_phy_address(FM2_DTSEC4, SGMII_CARD_PORT4_PHY_ADDR);
+ fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
+ fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
+ fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
+ fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
break;
default:
puts("Invalid SerDes2 protocol for T4240QDS\n");
diff --git a/include/configs/t4qds.h b/include/configs/t4qds.h
index ef8c5b2..b5462b7 100644
--- a/include/configs/t4qds.h
+++ b/include/configs/t4qds.h
@@ -649,7 +649,6 @@ unsigned long get_board_ddr_clk(void);
#define SGMII_CARD_PORT2_PHY_ADDR 0x1D
#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
-#define QSGMII_CARD_PHY_ADDR 0x5
#define FM1_10GEC1_PHY_ADDR 0x0
#define FM1_10GEC2_PHY_ADDR 0x1
#define FM2_10GEC1_PHY_ADDR 0x2
--
1.7.9.5
next prev parent reply other threads:[~2013-03-22 17:24 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-03-22 17:23 [U-Boot] [PATCH 03/21] fsl_ifc: add support for different IFC bank count York Sun
2013-03-22 17:23 ` [U-Boot] [PATCH 04/21] powerpc/mpc85xx b8460 PCIe registers are not at QORIQ_CHASSIS2 location York Sun
2013-03-22 17:23 ` [U-Boot] [PATCH 05/21] powerpc/mpc85xx: Add setting of clock-frequency for T4/B4 clockgen node York Sun
2013-03-22 20:54 ` Wolfgang Denk
2013-03-22 17:23 ` [U-Boot] [PATCH 06/21] t4240qds/eth: fixup ethernet for t4240qds York Sun
2013-03-22 17:23 ` [U-Boot] [PATCH 07/21] net/fm: fixup ethernet for mEMAC York Sun
2013-03-22 20:55 ` Wolfgang Denk
2013-03-22 17:23 ` [U-Boot] [PATCH 08/21] powerpc/85xx: fix build error introduced by serdes_get_prtcl York Sun
2013-03-22 17:24 ` [U-Boot] [PATCH 09/21] net/phy: add VSC8574 support York Sun
2013-03-22 20:55 ` Wolfgang Denk
2013-03-22 17:24 ` York Sun [this message]
2013-03-22 17:24 ` [U-Boot] [PATCH 11/21] T4/usb: move usb 2.0 utmi dual phy init code to cpu_init.c York Sun
2013-03-22 17:24 ` [U-Boot] [PATCH 12/21] powerpc/mpc85xx: Update workaround for DDR erratum A-004934 York Sun
2013-03-22 17:24 ` [U-Boot] [PATCH 13/21] powerpc/mpc8xxx: Allow board file to override DDR address assignment York Sun
2013-03-22 17:24 ` [U-Boot] [PATCH 14/21] powerpc/b4860qds: Assign DDR address in board file York Sun
2013-03-22 20:57 ` Wolfgang Denk
2013-03-22 17:24 ` [U-Boot] [PATCH 15/21] powerpc/t4qds: Fix disabling remote I2C connection York Sun
2013-03-22 17:24 ` [U-Boot] [PATCH 16/21] T4240/eth: fix SGMII card PHY address York Sun
2013-03-22 20:57 ` Wolfgang Denk
2013-03-22 17:24 ` [U-Boot] [PATCH 17/21] powerpc/srio: Remove duplicate macro definitions York Sun
2013-03-22 17:24 ` [U-Boot] [PATCH 18/21] powerpc/boot: Change the macro of Boot from SRIO and PCIE master module York Sun
2013-03-22 17:24 ` [U-Boot] [PATCH 19/21] powerpc/b4860qds: Add the tlb entries for SRIO interfaces York Sun
2013-03-22 20:58 ` Wolfgang Denk
2013-03-22 17:24 ` [U-Boot] [PATCH 20/21] powerpc/b4860qds: Master module for boot from SRIO and PCIE York Sun
2013-03-22 17:24 ` [U-Boot] [PATCH 21/21] powerpc/b4860qds: Slave " York Sun
2013-03-22 20:58 ` Wolfgang Denk
2013-05-10 21:49 ` [U-Boot] [PATCH 03/21] fsl_ifc: add support for different IFC bank count Andy Fleming
2013-05-14 8:59 ` Hu Mingkai-B21284
2013-05-14 14:43 ` Fleming Andy-AFLEMING
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